CN101872314A - Dynamic scheduling interrupt controller for multiprocessors - Google Patents

Dynamic scheduling interrupt controller for multiprocessors Download PDF

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CN101872314A
CN101872314A CN 201010124826 CN201010124826A CN101872314A CN 101872314 A CN101872314 A CN 101872314A CN 201010124826 CN201010124826 CN 201010124826 CN 201010124826 A CN201010124826 A CN 201010124826A CN 101872314 A CN101872314 A CN 101872314A
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processor
interrupt
cache
associated
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CN 201010124826
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Chinese (zh)
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CN101872314B (en )
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安德鲁·沃尔夫
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勒斯塔尔技术有限责任公司
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/48Program initiating; Program switching, e.g. by interrupt
    • G06F9/4806Task transfer initiation or dispatching
    • G06F9/4812Task transfer initiation or dispatching by interrupt, e.g. masked

Abstract

Technologies are generally described herein for handling interrupts within a multiprocessor computing system. A priority level associated with a current task for each processor of the multiprocessor computing system can be maintained. Cache state information associated with each processor can also be maintained. Upon receiving an interrupt to the multiprocessor computing system, a cache locality score for each processor can be determined based on the maintained cache state information. A value can be computed that balances, for each processor, the priority level and the cache locality score. A processor for servicing the interrupt can be determined based on the computed value. The determined processor can be signaled to service the interrupt. Tracking state information related to processor cores can support rapid allocation of an arriving interrupt to a processor core without collecting processor core state information at interrupt time.

Description

用于多处理器的动态调度中断控制器 Dynamic scheduling for multiprocessor interrupt controller

背景技术[0001] 中断可以用信号通知计算系统要通过执行中断处理程序来服务的事件,该中断处理程序也可已知为中断服务例程(ISR)。 BACKGROUND [0001] may signal an interrupt to the computing system to perform the service by the interrupt handler event, the interrupt handler may also be known as an interrupt service routine (ISR). 这种信号事件可以称为中断请求(IRQ)。 This event may signal called an interrupt request (IRQ). 处理器可以经过上下文切换来从其当前任务转换到执行与所接收到的中断关联的中断处理程序。 The processor may pass a context switch to transition to its current task associated with the interrupt received to execute the interrupt handler. 从当前处理器任务的转换可以认为是中断当前任务。 From the current processor task of conversion it can be considered interrupt the current task. 在多处理器计算系统中将接收到的中断分配给特定的处理器或者处理器核来进行执行会导致额外的复杂化。 Received in a multiprocessor computing system interrupt assigned to a specific processor or processor core for execution cause additional complications. 关于这些考虑以及其他考虑提出了本发明。 On these considerations, and other considerations put forward the present invention.

附图说明 BRIEF DESCRIPTION

[0002] 本发明的上述特征和其他特征由下面的描述和所附的权利要求结合附图变得更为完全清楚。 [0002] The above features and other features of the invention are shown become more fully understood from the following description and appended claims in conjunction. 这些附图理解为仅仅描绘了根据本发明的一些实施例,并且因此不能认为对其范围进行限制,本发明将通过使用附图以附加的特性和细节来进行描述,其中: These drawings depict only understood to some embodiments, and therefore not to be considered limiting of its scope, the present invention with additional specificity and detail be described by use of the accompanying drawings, in which according to the invention:

[0003] 图1是示出了多处理器的工作环境的框图; [0003] FIG. 1 is a block diagram illustrating a multi-processor environment;

[0004] 图2是示出了具有中断控制器的多核处理器的框图; [0004] FIG. 2 is a block diagram illustrating a multi-core processor having an interrupt controller;

[0005] 图3是示出了在多核处理器内的中断控制器的框图; [0005] FIG. 3 is a block diagram illustrating the interrupt controller in the multicore processor;

[0006] 图4是示出了中断控制器使用的核处理器状态信息的数据结构图; [0006] FIG. 4 is a diagram illustrating a data structure of the processor core state information used by the interrupt controller;

[0007] 图5是示出了用于将中断指派给当前空闲或者为最低优先级任务服务的处理器核的过程的流程图; [0007] FIG. 5 is a diagram illustrating a flowchart of a process for interrupting the current idle or lowest priority task and services assigned to the processor core;

[0008] 图6是示出了用于基于高速缓存(cache)状态信息将中断指派给处理器核的过程的流程图; [0008] FIG 6 is a flowchart showing a process (Cache) cache status information based on an interrupt assigned to the processor core;

[0009] 图7是示出了用于基于组合的优先级和高速缓存状态信息将中断指派给处理器核的过程的流程图;并且 [0009] FIG. 7 is a flowchart illustrating a cache based on a priority and interrupt status information assigned to a combination of the process of the processor core; and

[0010] 图8是示出了示例性的计算系统的框图,该计算系统都是根据这里提出的实施例中的至少一些实施例来布置的。 [0010] FIG. 8 is a block diagram illustrating an exemplary computing system, at least some embodiments of the computing system embodiments herein are according to the proposed arrangement.

具体实施方式 detailed description

[0011] 在下面的详细描述中参照附图,这些附图形成公开内容的一部分。 [0011] Referring to the drawings in the following detailed description, the accompanying drawings which form a part of the disclosure. 在图中,相似的符号通常标识相似的部件,除非上下文给出相反的指示。 In the drawings, similar symbols typically identify similar components, unless the context indicates to the contrary. 在详细的描述中描述的说明性的实施例、附图和权利要求并非旨在进行限制。 Illustrative embodiments, the drawings and the claims described in the detailed description is not intended to be limiting. 可以利用其他的实施例,并且可以进行其他修改,而并未脱离本发明提出的主题的精神或者范围。 Other embodiments may be utilized, and other changes may be made while not departing from the spirit or scope of the subject matter of the present invention proposed. 容易理解,本发明的方面,如这里一般地描述的以及在附图中所示出的那样,可以在不同配置的各种变化中进行布置、替换、组合、分离和设计,它们全都是这里所明确预期的。 Readily understood that aspects of the invention, and as shown in the figures as generally described herein, may be arranged, substituted, combined, separated, and designed in a variety of different configurations of variations, all of which are herein clear expectations.

[0012] 下面的公开内容尤其是涉及与将中断分配给多处理器中的特定处理器核的技术相关的方法、装置、系统和计算机程序产品。 [0012] The following disclosure relates in particular to the interrupt processor core assigned to a specific multiprocessor technology associated method, apparatus, system, and computer program product. 通过使用这里所提出的技术和概念,中断控制器可以基于处理器核可用性的各种度量的评估和被高速缓存的、与中断的中断处理程序相关的数据以及指令的位置来动态地将中断指派给处理器核。 By the use of the technologies and concepts presented herein, the interrupt controller may dynamically assign an interrupt based on various metrics assess the availability of a processor core and the cache, and the position data associated with the interrupt instruction interrupt handler to the processor core. 现在参照附图,其中在多个附图中同样的数字表示同样的元件,其中描述了在多处理器系统中的中断优化方面。 Referring now to the drawings, wherein like numerals denote like elements throughout the several figures, aspects of which are described in a multiprocessor system interrupt optimization.

[0013] 这里所描述的技术一般地涉及在多处理器计算系统中处理中断。 [0013] The techniques described herein relate generally to handle interrupts in a multiprocessor computing system. 可以维护与多处理器计算系统的各处理器的当前任务关联的优先级水平。 You can maintain the level of priority associated with the current task each processor and multi-processor computing system. 也可以维护与各处理器关联的高速缓存状态信息。 You can also maintain cache status information associated with each processor. 当接收到至多处理器计算系统的中断时,可以基于所维护的高速缓存状态信息来确定各处理器的高速缓存局部性分数(cache locality score)。 Upon receiving the interrupt to multiprocessor computing system, the information can be determined fraction of each cache locality processor (cache locality score) based on the cache status maintained. 可以计算针对各处理器平衡优先级水平和高速缓存局部性分数的值。 It may be calculated equilibrium value and priority level cache locality score for each processor. 可以基于所计算的值来确定用于为中断服务的处理器。 It can be calculated based on the value determined for the interrupt service processor. 可以用信号通知所确定的处理器来为中断服务。 It may signal the determined processor to interrupt service. 跟踪与处理器核相关的状态信息可以支持快速地将中断分配给处理器核,而无需延迟用以在中断时间从处理器核收集状态信息。 Tracking status information associated with the processor core can support fast interrupt assigned to the processor core, without the need to interrupt latency time information collected from the processor core state.

[0014] 现在回到图1,功能性框图100示出了根据这里说明的实施例的多处理器110的工作环境。 [0014] Returning now to FIG. 1, a functional block diagram 100 illustrating an embodiment of a multi-processor environment 110 in accordance with the described herein. 多处理器110可以合并多个处理器或者处理器核。 The processor 110 may incorporate multiple processors or multiple processor cores. 多核通常可以支持并行处理、并行任务、并行线程、分离的顺序过程或者它们的任意组合。 Multicore may generally support parallel processing, parallel tasks, parallel threads, separate sequential processes, or any combination thereof. 多处理器110可以访问存储器120。 Multi-processor 110 may access memory 120. 多处理器110可以对存储器120进行读取和写入。 Multi-processor 110 can read from and write to the memory 120. 这种读和写可以与同多处理器110的多核工作关联的指令及数据相关。 Such reads and writes can be associated with the work associated with the multi-core processor 110 is a multi-instructions and data. 通常,在多处理器110内的每个处理器核可以单独地访问存储器120。 Typically, each processor within the multi-core processor 110 may access the memory 120 individually. 存储器120可以是随机存取存储器(RAM)、静态RAM(SRAM)、动态RAM(DRAM)、同步DRAM (SDRAM)或者任意类型的易失性或者非易失性存储器。 The memory 120 may be random access memory (RAM), static RAM (SRAM), dynamic RAM (DRAM), volatile synchronous DRAM (SDRAM), or any type of memory or non-volatile.

[0015] 与多处理器110的多个核上的工作关联的指令和数据可以被存储在存储介质130 装置上。 [0015] operatively associated with the plurality of multi-core processor 110 commands and data may be stored on a storage medium device 130. 存储介质130可以支持信息的非易失性存储。 Storage medium 130 may support a non-volatile storage of information. 存储介质130可以被多处理器110 内的多个处理器核访问。 Storage medium 130 may be a plurality of processor cores in a multi-processor 110 to access. 存储介质130可以存储用于在多处理器110内的多个处理器核上执行的软件132。 Storage medium 130 may store software used within the multi-processor core 110 executing on a plurality of processor 132. 例如(并不作为限制),计算机可读介质可以包括计算机存储介质和通信介质。 For example (and not limitation), computer readable media may comprise computer storage media and communication media. 计算机存储介质可以包括以用于存储信息如计算机可读的指令、数据结构、程序模块或者其他数据的任意方法或者技术来实现的易失性、非易失性、可移动以及不可移动介质。 Computer storage media may include volatile, non- volatile computer-readable instructions, data structures, program modules or other data in any method or technology for storage of information to be achieved, the movable and non-removable media. 计算机存储介质可以包括(但并不局限于)RAM、只读存储器(ROM)、可擦除可编程ROM(EPROM)、电可擦除可编程ROM(EEPROM)、闪存、其他固态存储器技术、光盘(CD-ROM)、数字多用盘(DVD)、高清DVD、蓝光盘、其他光学存储装置、磁盒、磁带、磁盘存储装置、其他磁性存储设备、或者可以用于存储所希望的信息以及可以被多处理器110访问的任意其他介质。 Computer storage media may include (but are not limited to) the RAM, a read only memory (ROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), flash memory, other solid state memory technology, CD-ROM (CD-ROM), digital versatile disc (DVD), HD DVD, blu-ray disc, other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage, other magnetic storage devices, or the information may be used to store the desired and may be 110 any other medium accessible to multiple processors.

[0016] 与多处理器110关联的软件132或者其他指令、代码、模块或者程序可以包括用于对中断事件进行响应的模块。 [0016] 110 associated with the multiprocessor 132 or other software, instructions, code, or program module may include a module in response to the interrupt event. 这种模块可以称为中断服务例程(ISR)或者动态调度中断处理程序134。 This module can be referred to an interrupt service routine (ISR) or dynamic scheduling interrupt handler 134. 动态调度中断处理程序134可以被配置用于如这里所提出的那样支持中断的动态调度。 Dynamic scheduling interrupt handler 134 may be configured to support dynamic scheduling as set forth herein interrupted. 中断处理程序134可以响应于在多处理器110处接收到关联的中断来被执行。 Interrupt handler 134 in response to receiving an interrupt to an associated multi-processor 110 to be executed. 中断处理程序134可以与特定的中断事件、中断的特定原因、中断的来源或者特定的中断信号线关联。 Specific reason for the interrupt handler 134 can interrupt with a particular event, interrupt, the interrupt source or associated with a particular interrupt signal line. 中断处理程序134可以中断或者抢占与多处理器110关联的其他操作。 The interrupt handler 134 can interrupt or preempt other operations 110 associated with multiple processors. 这种抢占可以支持快速响应于中断到达多处理器110来执行中断处理程序134。 This preemption can support fast interrupt response to the arrival multi-processor 110 to execute the interrupt handler 134. 快速响应可以支持各种软件模块的实时的、硬实时的、软实时的或者近实时的操作。 Quick response can support a variety of real-time software modules, hard real-time, soft real-time or near real-time operation. 中断处理程序134模块的一个例子可以与设备驱动器或者其他软件、固件关联,或者是与支持外部设备关联的模块。 An example of an interrupt handler module 134 may be other device driver software, firmware, or association, or the external device associated with the module support. 被支持的设备或者关联的接口电路可以认为是与设备驱动器、ISR或者中断处理程序134关联的中断的来源。 Supported interface circuit or device that may be associated with the source of the interrupt device driver, ISR or the interrupt handler 134 is associated. 在接收到中断信号时,所关联的中断处理程序134可以立即执行、 在特定的时限内执行或者根据与中断处理程序134和其他操作关联的优先级水平来执行。 Upon receiving the interrupt signal, the interrupt handler associated 134 may execute immediately, or be performed in accordance with the execution priority level interrupt handler 134 and other associated operations within a particular time frame. [0017] 外部时钟140可以提供时钟信号给多处理器110。 [0017] The external clock 140 may provide a clock signal to the multi-processor 110. 外部时钟140可以包括晶体振荡器或者任意其他时钟或者振荡器源。 External crystal oscillator 140 may include a clock or oscillator or any other clock source. 外部时钟140可以包括时钟驱动器电路。 External clock 140 may include a clock driver circuit. 与外部时钟140关联的时钟信号可以用于将多处理器110内的各个电路定时和同步。 Clock 140 associated with the external clock signal to the respective circuits may be used for timing and synchronization within the multiprocessor 110. 多处理器110 也可以接口到实时时钟(RTC) 145。 Multi-processor 110 may be an interface to the real-time clock (RTC) 145. 实时时钟145可以用于维护人类的时间,例如时刻、星期几、日历日、年等等。 Real-time clock 145 can be used for the preservation of human time, such as time, day of week, calendar day, year and so on. RTC 145可以生成与定时器、报警器或者看门狗(watchdog)电路有关的至多处理器110的中断事件。 RTC 145 may be generated relating to the timer or watchdog alarm (Watchdog) circuit 110 to multiprocessor interrupt event.

[0018] 接口至多处理器110的各种设备可以生成中断。 Various devices [0018] up to the interface processor 110 may generate an interrupt. 这种中断可以用信号通知多处理器110响应于中断请求服务。 Such interruptions can service the interrupt request signal the multi-processor 110 in response. 可以执行中断处理程序134来服务设备的中断。 You can execute the interrupt handler 134 to interrupt service equipment. 作为非限制性的例子,在图1中示出了一些不同的设备。 As a non-limiting example, in FIG. 1 shows a number of different devices. 例如中断设备可以是网络接口150。 For example interrupting device may be a network interface 150. 网络接口150可以用于附接到网络155上。 Network interface 150 may be used to attach the network 155. 当从网络155接收到数据包时,网络接口150可以生成中断。 When receiving a packet from the network 155, network interface 150 may generate an interrupt. 于是,可以执行与网络接口150关联的中断处理程序134来从网络接口150接收数据包。 Thus, 134 may be performed to receive packets from the network interface 150 and network interface 150 associated with the interrupt handler. 类似地,无线电接口160可以使用天线165来发送和接收无线数据包给无线网络或者移动通信系统。 Similarly, the radio interface 160 may use antenna 165 for transmitting and receiving wireless data packet network or a wireless mobile communication system.

[0019] 一个或多个接口总线170也可以接口到多处理器110。 [0019] One or more interface bus 170 may also be interfaced to the multiprocessor 110. 接口总线的例子可以包括工业标准架构(ISA)总线、外设部件互联(PCI)总线、高速PCI (PCI-Express)总线、图形加速端口(AGP)总线、通用串行总线(USB)、高级技术附件(AT A)总线、串行高级技术附件(SATA)总线、小型计算机系统接口(SCSI)和其他使用在计算机和嵌入式处理器系统中的这种总线和接口。 Examples of the interface bus may include Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, a high speed PCI (PCI-Express) bus, an accelerated graphics port (AGP) bus, a universal serial bus (USB), Advanced Technology Annex (aT a) bus, a serial advanced technology attachment (SATA) bus, a small computer system interface (SCSI), and others using the computer system and an embedded processor and bus interfaces such. 总线或者与总线关联的接口电路可以包括一种或多种用于中断多处理器110的中断机制。 Associated with the bus or bus interface circuit may include one or more multi-processor interrupt mechanism for interrupting 110. 模拟接口180可以连接到多处理器110。 Analog interface 180 may be coupled to the multiprocessor 110. 模拟接口180可以包括数模转换器、模数转换器,或者包括二者。 Analog interface 180 may comprise a digital, analog to digital converter, or comprises both. 模拟接口180可以用于视频信号、音频信号、红外信号、 雷达信号或者任何其他模拟信号。 Analog interface 180 can be used for video signals, audio signals, infrared signals, radar signals or any other analog signals. 模拟接口180或者支持模拟接口180的电路可以生成至多处理器110的中断。 Analog interface circuit 180 or the analog interface 180 may support up to generate an interrupt processor 110. 一个或多个人机接口190可以连接至多处理器110。 One or more human-machine interface 190 can be connected to up to 110 processors. 人机接口190 可以包括视频显示器、键盘、鼠标、光笔、投影仪、语音识别、开关、按键、指示器或者用于从人接收输入或者将输出提供给人的任何其他机制。 Human interface 190 may include a video display, a keyboard, a mouse, a light pen, a projector, voice recognition, switches, buttons, indicators or for receiving input from a human or any other mechanism providing an output gives. 人机接口190或者与其关联的电路可以提供中断给多处理器110。 Human interface circuitry 190 associated therewith or may provide an interrupt to the multiprocessor 110.

[0020] 现在参照图2,框图示出了根据这里所描述的实施例的具有中断控制器的多核处理器。 [0020] Referring now to FIG. 2, a block diagram illustrating a multi-core processor interrupt controller according to embodiments described herein having. 多处理器Iio可以具有多个内部处理器核如核1直到核N 210A-210E。 Multiprocessor Iio may have a plurality of internal processor cores, such as core 1 through core N 210A-210E. 它们可以共同地或者一般地称为处理器核210。 They may be collectively or generally referred to as the processor core 210. 到达多处理器110的中断可以来自外部接口230。 Reaches the multiprocessor 110 may interrupt from the external interface 230. 与外部接口230关联的中断可以源自外部设备,如参照图1所讨论的那样。 230 associated with the external interrupt interface to an external device may be derived, as described with reference to FIG. 1 discussed. 类似地,多处理器110内部的设备可以产生中断。 Similarly, a multi-processor inside the device 110 may generate an interrupt. 例如,定时器240、电源管理机构242、直接存储器访问(DMA) 控制器244或者其他芯片上的外围设备246可以生成中断,该中断类似于源自外部接口230 的中断。 For example, a timer 240, a power management mechanism 242, a direct memory access (DMA) controller 244, or other peripheral devices on the chip 246 may generate an interrupt, the interrupt from the external interface 230 is similar.

[0021] 来自内部设备和外部接口230的各种中断信号可以分别承载于至动态调度中断控制器220的中断线225上。 [0021] from a variety of internal and external device interface 230 can interrupt signals are carried to the break 225 in the dynamic scheduling interrupt controller 220. 每个中断线225可以与单独的动态调度中断处理程序134关联,或者多于一个中断线225可以与动态调度中断处理程序134关联。 Each interrupt handler 225 may be a separate dynamic scheduling with associated interrupt 134, or 225 may be more than one interrupt handler 134 associated with the dynamic scheduling interrupt. 中断控制器220可以通过中断总线215与处理器核210接口。 Interrupt bus 215 and the processor 220 may be core 210 by interrupting the interface controller. 中断总线215可以是串行总线、并行总线或者用于在中断控制器220和多处理器核210之间互通信号的任意通道。 Interrupt bus 215 may be a serial bus, a parallel bus or for any channel interrupt signals communicate between the multiple processor cores 220 and the controller 210. 中断总线215可以是通用系统总线、输入/输出(I/O)总线或者存储器总线。 Interrupt bus 215 may be a general system bus, input / output (I / O) bus or a memory bus. 中断总线215也可以用于在中断控制器220和多处理器核210之间互通信号。 Interrupt bus 215 may also be used to communicate signals between the interrupt controller 220 and a multi-core processor 210. 中断总线215可以承载中断控制器220和处理器核210之间的与中断信息相关的消息。 Interrupt bus 215 may carry an interrupt message to the interrupt-related information between the controller 220 and the processor core 210. 在中断总线215上互通的消息可以编码为信号、 脉冲、逻辑电平、包、帧或者本领域中已知的任何其他表示。 Interworking messages on the interrupt bus 215 may be encoded as a signal pulse, the logic level, package, or any other frame known in the art FIG.

[0022] 中断可以通过抢占处理器执行资源来延迟当前执行过程。 [0022] interrupt the currently executing process can be delayed by preemptive processor execution resources. 从当前任务交换至中断处理程序134可以通过上下文切换来进行。 134 may be switched to the current task context switch interrupt routine. 上下文切换会导致操作完全混乱。 Context switching operation will lead to complete chaos. 上下文切换会导致放弃和重新执行操作。 Context switching will lead to give up and re-execute the operation. 上下文切换会导致清空内部缓存器,或者改变高速缓存。 Context switching will result clear the internal buffer, or change the cache. 缓存行(cache line)和转换后备缓存(TLB)条目可能会被来自中断处理程序134的数据或代码无效。 Cache line (cache line) and a translation lookaside buffer (TLB) entry might be invalid from the interrupt handler 134 of the data or code. 高速缓存可以将近来被访问的数据或者代码维护在更快的高速缓存存储器中用于随后的快速访问。 Data or code cache can be accessed recently maintained for subsequent quick access in a faster cache memory. 这会是有利的,因为重复访问以及引用局部性的概念意味着近来被访问的存储器位置、或者附近的位置可能是在近期再访问的候选。 This is advantageous because the memory location and repeat visits concept of locality of reference means that have been recently accessed, or near the location may be a candidate in the recent re-visit. 如果与中断处理程序134 关联的代码或者数据被以修改后的状态被高速缓存在其他处理器核中,则中断响应等待时间和中断处理时间会被延迟。 If 134 associated with the interrupt handler code or data in a modified state is cached in the other processor core, the interrupt response latency time and the interrupt processing is delayed.

[0023] 在中断频繁、中断服务例程涉及大量代码或者数据的系统中,或者当全部计算时间中的大量计算时间用于为中断服务时,会提高破坏效应。 [0023] In frequent interrupt, the interrupt service routine to a system of large amounts of code or data, or when a large amount of calculation time Calculation time for all interrupt service, the damaging effects will increase. 在其中有复杂的计算任务的通用或者专用计算系统中会出现这种情况,其中复杂的计算任务涉及与实时调度联系的大量数据。 In which complex computing tasks of general or special purpose computing system will appear in this case, where the complex computing tasks involving large amounts of data and real-time scheduling link. 在服务器计算机中会出现类似情况,服务器计算机处理大量的网络业务或者存储系统I/O操作。 A similar situation arises in the server computer, the server computer process a large amount of network traffic or storage system I / O operations. 嵌入式计算系统是嵌入在通常支持控制和通信功能的设备或者系统中的专用计算系统。 Embedded computing systems embedded in the device or system generally support control and communication functions in a special purpose computing system. 例如,嵌入式处理器可以用于发动机控制器、机器入控制器、通信设备、调制解调器、移动电话、远程控制以及本领域中已知的各种其他应用。 For example, an embedded processor may be a controller for an engine, the machine controller, a communications device, a modem, a mobile telephone, remote control, and known in the art, a variety of other applications. 嵌入式计算系统会使用其大量计算时间来响应中断。 Embedded computing systems that will be used to calculate a lot of time to respond to interrupts. 因此,本发明认识到在嵌入式环境中工作的多处理器110的效率可以充分地受益于改进的、用于以有效和高效的方式将资源分配给中断的技术。 Accordingly, the present invention recognizes that the work efficiency of the multiprocessor 110 in an embedded environment may benefit from improved sufficiently for an effective and efficient way to allocate resources to the interrupt in the art.

[0024] 中断可在计算系统中周期性地或者至少反复地执行。 [0024] interrupt can be performed periodically or repeatedly at least in a computing system. 在执行特定中断处理程序134的每个例程中可能共同使用相同的代码和数据。 In each perform a particular interrupt handler routine 134 may use the same common code and data. 在代码和数据资源已经分配给做出响应的处理器核的情况下,可以支持提高执行中断处理程序134时的效率。 In the case of code and data resources have been allocated to respond to the processor core, can support 134 to improve efficiency when executing the interrupt handler. 这种预先分配也可以涉及代码或者数据已经高速缓存在做出响应的处理器核处,由此得到提高的高速缓存效率。 Such pre-allocation code or data may also relate to already cached in the processor core responsive, to thereby obtain improved efficiency of the cache. 于是,本发明认识到,将特定中断处理程序134的执行分配给处理过该中断处理程序134的先前实例的处理器核可以提高效率。 Accordingly, the present invention recognizes that the particular interrupt handler 134 assigned to execute the interrupt handler processed the previous example processor core 134 may improve efficiency.

[0025] 然而,当中断到达时,执行过特定中断处理程序134的先前实例的处理器核可能忙于执行任务。 [0025] However, when an interrupt arrives, the particular interrupt handler executed the previous example processor core 134 may be busy performing tasks. 该任务可以称为该处理器核的当前任务。 This task can be referred to the current task of the processor core. 如果当前任务是高优先级任务, 则上下文切换到执行中断处理程序134可能被延迟或者是要禁止的有破坏性的。 If the current task is a high priority task, the context switch to execute the interrupt handler 134 may be delayed or be prohibited destructive. 如果处理器的当前任务是低优先级任务,则当前任务可以被抢占或者延迟,以便执行中断处理程序134。 If the current task processor is a low priority task, the current task can be preempted or delayed, in order to execute the interrupt handler 134. 在两种情况中,其他处理器核可能是空闲的或者执行甚至优先级更低的任务,因此与抢占或者等待优选的处理器相比,将中断指派给其他处理器之一可支持提高系统效率。 In both cases, the other processor cores may be idle or perform even lower priority task as compared with preemptive or wait preferred processor interrupt assigned to one of the other processors support system efficiency . 将中断给特定处理器核的这种分配可以平衡在以前执行过中断处理程序134的处理器上执行中断处理程序134的高速缓存效率与将中断处理程序134的执行指派给另外的当前空闲或者至少当前处理最低优先级任务的处理器的优点。 Interrupt to a particular processor core perform this assignment can be balanced before the interrupt on the processor over the interrupt handler 134 performs processing efficiency program cache 134 and the execution of the interrupt handler 134 currently assigned to another idle or at least advantage of the current processor task of lowest priority treatment. 可以通过将中断分配的这两个因素相加、组合或者一同加权来建立分数或者开销。 These two factors can be assigned interrupt addition, combinations or weighted together to establish scores or overhead.

[0026] 现在参照图3,框图300示出了根据这里提出的实施例的方面的多核处理器内的中断控制器220。 [0026] Referring now to Figure 3, a block diagram 300 illustrates an interrupt controller within the aspects of an embodiment presented herein multicore processor 220. 中断控制器220可以接收和锁存在一个或多个中断线225上到达的中断请求。 Interrupt controller 220 may receive an interrupt request is latched and the one or more interrupt lines 225 on arrival. 响应于中断请求事件,中断控制器220可以识别哪个处理器核210可以执行中断处理程序134因此为中断服务。 Event in response to the interrupt request, the interrupt controller 220 may identify which processor core 210 may execute the interrupt handler 134 is thus interrupt. 中断控制器220可以监视与多处理器系统关联的各种状态信息。 Interrupt controller 220 may monitor the multiprocessor system associated with various states. 根据监视该状态信息,中断控制器220可以确定和存储与多处理器110相关的系统状态信息的本地表示。 The monitoring indicates the status information, the interrupt controller system status information associated with the plurality of processors 110 and 220 may determine a local store. 这些表示可以是多处理器110内的状态信息的副本或者估计量。 These representations may be a copy or estimate the state information within the multi-processor 110.

[0027] 与处理器核210相关的状态信息可以涉及优先级水平、高速缓存或者其他关于希望用特别的处理器核210为中断服务的有关状态信息。 [0027] associated with the processor core 210 state information may relate to the priority level cache or other information about a particular wish of the processor core 210 is about the status of service interruption. 每个处理器核210可以具有Ll高速缓存320A-320C。 Each processor core 210 may have Ll cache 320A-320C. Ll高速缓存320A-320C是第一级高速缓存并且可以共同地或者一般地称为Ll高速缓存320。 Ll cache 320A-320C is a first-level cache and may be collectively or generally referred to as Ll cache 320. 每个处理器核210还可以具有L2高速缓存325A-325B。 Each processor core 210 may also have L2 caches 325A-325B. L2高速缓存325A-325B是第二级高速缓存并且可以共同地或者一般地称为L2高速缓存325。 L2 caches 325A-325B is a second-level cache and may be collectively or generally referred to as the L2 cache 325. L2高速缓存325可以在处理器核之间被共享,如通过L2高速缓存325A所示出的那样,或者L2 高速缓存325可以被一个处理器核专用,如通过L2高速缓存325B所示出的那样。 L2 cache 325 may be shared between the processor core, such as cache 325A, as shown, by L2 or L2 cache 325 may be a dedicated processor core, as shown by the L2 cache 325B as . Ll高速缓存320可以存储近来已经被从存储器120访问的代码或数据。 Ll cache 320 may store or have been recently accessed data from the code memory 120. 在TLB中或者在高速缓存中,页表信息也可以被高速缓存为TLB条目。 In the cache or TLB, the page table information may be cached for the TLB entry. L2高速缓存325可以存储如下的高速缓存条目:这些高速缓存条目从Ll高速缓存320已经过期,然而仍然足够新近以维持被高速缓存。 L2 cache 325 may store a cache entry: These cache entries have expired from the Ll cache 320, but still enough to sustain the newly cached. 通常,Ll高速缓存320会比L2高速缓存325更小并且更快。 Typically, Ll cache 320 than the L2 cache 325 is smaller and faster. 如本领域中已知的那样,也可以使用更少层或者附加层的高速缓存。 As it is known in the art that may be used cache fewer layers or additional layers. 在每个等级,单独的缓存块、缓存行或者缓存区可以用于代码、数据和TLB条目。 In each level, a single cache block, or the buffer cache line may be used for code, data, and the TLB entry. 这些缓存区也可以以任意组合来共享高速缓存存储器空间。 The buffer may be any combination of shared cache memory space.

[0028] 处理器核210可各自执行当前任务305A-305C。 [0028] The processor core 210 may each perform the current task 305A-305C. 当前任务305A-305C也可以共同地或者一般地称为当前任务305。 The current task 305A-305C can be collectively or generally referred to as the current task 305. 中断控制器220可以监视和存储表示在各处理器核210 上的当前任务305的优先级水平的信息。 Interrupt controller 220 may monitor and store information indicating the current task priority level 305 at each of the processor core 210. 这可以通过让负责任务切换的操作系统代码在每次设置任务开始执行时将当前任务优先级写入中断控制器220来实现。 This can be responsible for task switching allows the operating system code each time the task is set to begin a write current task priority interrupt controller 220 is implemented. 在一些例子中,任务切换或者线程切换可以由硬件或者硬件和软件的某个组合来执行,负责切换任务的电路或者模块可以将当前任务优先级用信号通知或者写入中断控制器220。 In some examples, the task switching or thread switching may be performed by hardware or a combination of hardware and software, responsible for task switching circuits or modules may be the current task priority of the interrupt signal the controller 220 or writing. 在一些附加的例子中,从各处理器核210至中断控制器220的中断总线215或者专用信号线可以布置用于指示当前执行任务或者线程的当前优先级水平。 In some additional examples, the controller 220 or a dedicated interrupt bus signal line 215 may be arranged for indicating the currently executing task or the current priority level from each thread interrupt to the processor core 210. 在另外一些例子中,可以使用指示最低可能优先级的缺省值来指示处理器核210空闲。 In some other instances, may be used to indicate the lowest possible priority to indicate the default value of the processor core 210 is idle.

[0029] 在中断控制器220处维护的状态信息可以用于确定哪个处理器核210空闲或者正在执行低优先级任务。 [0029] In the state of the interrupt controller 220 maintains the information may be used to determine which processor core 210 is performing idle or low priority task. 中断控制器220可以被布置用于使用该当前任务优先级信息的本地存储的副本来选择用于为中断服务的处理器核210。 Interrupt controller 220 may be arranged for the use of locally stored copy of the current task priority information for selecting the interrupt service processor core 210. 被选择的处理器核210可以是空闲的或者可以具有最低的当前任务优先级水平。 The selected processor core 210 may be idle or may have the lowest current task priority level. 中断控制器220可以被配置为发送消息给与所选择的处理器核210对应的本地中断控制器330。 Interrupt controller 220 may be configured to correspond to the processor core 210 to transmit a message given to the selected local interrupt controller 330. 该消息可以指出哪个中断请求服务并且可以指示所选择的处理器核210为该中断服务。 The message may indicate which interrupt service request and may indicate the selected processor core 210 for the service interruption. 这种方式可以用于将中断快速地指派给处理器核210并且可以用于支持减少对当前执行任务305的影响。 This approach can be used to quickly interrupt assigned to the processor core 210 and can be used to support the mission to reduce the impact of the current 305.

[0030] 中断控制器220可以被布置用于基于执行中断处理程序134的最少开销来将中断动态地指派给处理器核210。 [0030] The interrupt controller 220 may be arranged to execute the interrupt handler based on the least cost to 134 dynamically assigned to interrupt the processor core 210. 中断控制器220可以被初始化以响应于各特别的中断。 Interrupt controller 220 may be initialized in response to each particular interrupt. 在初始化过程中,可以针对各中断创建数据结构或者类似的存储器或电路。 In the initialization process, you can create a data structure or a similar memory or circuitry for each interrupt. 在一些例子中, 可以使用该结构来跟踪与中断处理程序134关联的任何代码是否当前被高速缓存在各处理器核210处。 Whether any code In some examples, the structure may be used to track the associated interrupt handler 134 currently cached in the processor core 210. 在一些附加的例子中,该结构可以用来跟踪与中断处理程序134关联的任何数据是否当前被高速缓存在各处理器核210处。 Whether any data some additional examples, the structure may be used to track the associated interrupt handler 134 currently cached in the processor core 210. 该结构也可以用于跟踪同与中断处理程序134关联的代码或者数据对应的任何TLB条目是否当前被高速缓存在各处理器核210 Any TLB entries may also be used to track the configuration associated with the interrupt handler 134 corresponding to the code or data is currently cached in the processor core 210

8处。 At 8. 该结构可以表示与中断处理程序134关联的各缓存行或者缓存页,或者可以通过表示集(representative set)来估计。 This structure can be represented interrupt handler 134 associated with each cache page or cache line, or may be represented by a set of estimates (representative set). 该结构可以存储在存储器中,由专用硬件来维护,或者可以是其任意组合。 The structure may be stored in a memory, it is maintained by dedicated hardware, or may be any combination thereof. 该结构可以通过高速缓存标签、虚拟地址、物理地址或者任何其他合理的高速缓存组织机制来组织。 This structure can be organized by the cache tag, the virtual address, physical address or any other reasonable cache organization mechanism.

[0031] 在一些实现中,中断控制器220可以被布置用于监视系统总线310上的交互来跟踪感兴趣的各行或者页的当前高速缓存状态。 [0031] In some implementations, the interrupt controller 220 may be arranged to interact with the monitoring system on the bus 310 to keep track of the current status of each cache line or page of interest. 在其中例如L2高速缓存325在核之间被共享的情况中,中断控制器220可以监视Ll高速缓存320和L2高速缓存325的状态。 In the case where, for example, L2 cache 325 is shared between the core, the interrupt controller 220 may monitor the Ll cache 320 and L2 cache state 325. 这种具体的高速缓存监视可以涉及监视高速缓存总线340以及监视系统总线310。 This particular cache monitor monitoring may involve monitoring a cache bus 340 and a system bus 310. 每个高速缓存可以被独立地跟踪。 Each cache can be tracked independently. 在一些例子中,可以使用评分系统,其中存在于Ll高速缓存320中比存在于L2高速缓存325中具有更大的权重。 In some examples, scoring system may be used, which is present in the Ll cache 320 than is present in the L2 cache 325 has a larger weight.

[0032] 中断控制器220可以被配置用于为各处理器核210计算局部性分数,其中局部性分数指示与中断处理程序134关联的多少代码和数据被各核高速缓存。 [0032] The interrupt controller 220 may be configured to calculate the score for the local processor core 210, wherein the local score indicates interrupt handler 134 associated with the number of code and data caches for each core. 在一些例子中,局部性分数可以是与各处理器核210关联的Ll高速缓存320中有效的、被跟踪的代码和数据缓存行的百分比。 In some instances, an effective local score may be associated with each processor core 210 of the Ll cache 320, percentages tracking code and data cache line. 评分功能的另一例子可以涉及在Ll高速缓存320、L2高速缓存325、TLB 条目中的有效缓存行的百分比的加权和或者其任意组合。 Another example may involve scoring function in the Ll cache 320, L2 cache 325, or any combination of the weighted sum of the percentage of valid cache line in the TLB entry thereof. 获得高的局部性分数的处理器核210可以被中断控制器220选择用于为等待处理的中断服务。 Get high scores local processor core 210 may be used to select the interrupt controller 220 to interrupt pending. 例如,消息可以由中断控制器220通过中断总线215发送给与指派的核关联的本地中断控制器330。 For example, the message may be interrupted by the interrupt controller 220 via local bus 215 associated core assignment sent to a controller 330 of the interrupt. 该示例性的消息可以指示中断并且请求处理器核210为中断服务。 The exemplary interrupt message may indicate that the processor core 210 and requests the interrupt service.

[0033] 可替选地,最低优先级和最高局部性分数这两种方式可以被一同使用来将中断指派给处理器核。 [0033] Alternatively, the lowest and the highest priority locality scores two methods may be used together to interrupt assigned to the processor core. 可以使用数学函数来将最低优先级与最高局部性分数结合。 You can use mathematical functions to be combined with the lowest priority with the highest local score. 例如,针对各处理器核的局部性分数可以被标准化到与可能的优先级水平的范围相同的范围,并且随后当前任务优先级水平可以被从该分数减去。 For example, the score for each local processor core may be normalized to the same range of possible priority level range, and then the current task priority level can be subtracted from the score. 这会产生组合分数,其可以用于选择哪个处理器核210为中断服务。 This will produce a combined score, which can be used to select which processor core 210 to interrupt service. 对于已经阅读了本公开内容的本领域普通技术人员而言,其他用于将所述两种因素结合的关系是清楚的。 For reading this disclosure has those of ordinary skill in the art, other relations for bonding the two factors is apparent.

[0034] 在一些实现中,中断控制器220和各种本地中断控制器330可以被实施为在支持处理器核210的相同集成电路中的模块或者电路。 [0034] In some implementations, the interrupt controller 220, and various local interrupt controller 330 may be implemented as to support the same integrated circuit as processor core 210 or the circuit module. 这种集成电路可以称为多处理器110。 Such a multi-processor integrated circuit 110 may be referred to. 在另外一些实现中,中断控制器220和各种本地中断控制器330可以被实施为与处理器核210分离的集成电路中的模块或者电路。 In other implementations, the interrupt controller 220, and various local interrupt controller 330 may be implemented as a processor core 210 are separate integrated circuits or circuit modules. 处理器核210也可以实施为分离的单独的处理器, 或者在另外一些例子中处理器核210可以被实施为集成电路。 The processor core 210 may also be implemented as a single separate processor or processor core 210 may be implemented as an integrated circuit in other cases.

[0035] 这里讨论的集成电路可以是专用的可编程集成电路(ASIC)如现场可编程门阵列(FPGA)、片上系统(SOC)、衬底上系统(system onsubstrate)、封装上系统(system on package)或者以任何其他用于集成电路或者封装电路的方式实施。 [0035] integrated circuits discussed herein may be a dedicated programmable integrated circuit (ASIC), such as field programmable gate arrays (the FPGA), the system (SOC) on a chip, on a substrate system (system onsubstrate), the encapsulation system (system on package) or implemented in any other way for the integrated circuit or circuit package. 虽然作为分离的模块或者电路来示出和讨论,然而中断控制器220、中断请求判定器310和各种本地中断控制器330可以在功能上以任何组合来结合或者不同地划分,而并未离开这里所公开的技术的精神和范围。 While shown and discussed as separate circuits or modules, however, the interrupt controller 220, the interrupt request determiner 310 and the various local interrupt controller 330 may be incorporated in any combination or differently functionally divided, and not leave the spirit and scope of the technology disclosed herein. 总之,任意组合的中断控制器220、中断总线215、各种本地中断控制器330或者其任意子集可以被称为中断分配系统。 In short, any combination of the interrupt controller 220, the interrupt bus 215, various local interrupt controller 330, or any subset of the dispensing system may be referred interrupted.

[0036] 现在参照图4,数据结构图400示出了根据这里提出的实施例的中断控制器使用的核处理器状态信息。 [0036] Referring now to FIG. 4, FIG 400 shows the data structure of a core processor state information presented herein interrupt controller used in the embodiment. 中断控制器220可以被配置用于为与各核处理器210相关的信息维护数据结构、相似的存储器结构或者电路。 Interrupt controller 220 may be configured with the information related to core processor 210 to maintain a data structure, or a structure similar to the memory circuit. 这些结构可以被布置用于维护与处理器核210相关的状态信息如优先级水平或者高速缓存存储器状态。 These structures may be arranged associated with the processor core 210 to maintain state information such as the priority level or the state cache memory. 这些结构可以被存储在存储器中、被专用硬件维护,或者使用任何其他合理的方式来存储信息。 These structures may be stored in the memory, it is maintained in dedicated hardware, or using any other reasonable way to store information.

[0037] 在中断控制器220处跟踪与处理器核210相关的状态信息可以支持由中断控制器220快速地将到达的中断分配给处理器核210。 [0037] Tracking the interrupt controller 220 associated with the processor core 210 to support the state information may be allocated to reach interrupt the processor core 210 by the interrupt controller 220 rapidly. 如果状态信息或者其估计已经被维护于中断控制器220处,则在中断时间可以充分地避免中断控制器220和处理器核210之间的交互来确定哪个处理器核可以最佳地为到达的中断服务。 If the status information, or estimated to have been maintained in the interrupt controller 220, the interruption time can be sufficiently avoid interruption of the interaction between the controller 220 and processor core 210 may determine which processor core to reach the best interrupt service.

[0038] 当前任务优先级水平结构410可以用于记录在各处理器核210处执行的当前任务305的优先级水平。 [0038] the current task priority level structure 410 may be used for recording execution priority level of each processor core 210 at 305 the current task. 对于图4所示的例子,优先级水平6、5、3和7可以分别指派给核0至3。 For the example shown in FIG. 4, priority levels 6,5,3 and 7 may be assigned to each core 0-3. 中断控制器220可以通过参照图3所讨论的各种监视技术或者报告技术来收集该信息。 Interrupt controller 220 may report a variety of monitoring techniques or techniques discussed 3 by referring to the collected information. 指示最低可能优先级的缺省优先级水平值可以用于指示处理器核210当前空闲。 Indicates the lowest possible priority level default priority value may be used to indicate the processor core 210 is currently idle.

[0039] 高速缓存有效性结构420可以被中断控制器220维护来跟踪处理器核210处的高速缓存状态信息,因为其与中断处理程序134有关。 [0039] The cache 420 may be structural validity of the interrupt controller 220 to maintain cache status information to track the processor core 210, 134 as it related to the interrupt handler. 高速缓存有效性结构420可以用于跟踪与特定的中断处理程序134关联的任何代码、数据或者有关的TLB条目是否当前在各处理器核210处被高速缓存。 Cache validity structure 420 may be used to track any code specific interrupt handler 134 associated with, or related to the data TLB entry is currently at each processor core 210 is cached. 针对与代码或者数据(其可能与中断处理程序134相关)关联的存储器120中的位置,高速缓存有效性结构420可以由高速缓存单元如缓存行或缓存页来组织。 And for the code or data (which may be associated with the interrupt handler 134) associated with a memory location 120, the effectiveness of the cache, such as cache line structure 420 may be organized by cache page or cache unit. 高速缓存有效性结构420可以由高速缓存标签、虚拟地址、物理地址或者本领域已知的任意其他的高速缓存组织机制来组织。 Cache validity structure 420 may be formed of cache tag virtual address, physical address or any other known in the art caching mechanisms organized tissue. 在高速缓存有效性结构420中的条目也可以跟踪与用于中断处理程序134的代码或者数据相关的地址的TLB条目。 Entries in the cache validity structure 420 may also be used for tracking and the interrupt handler code 134 or data address TLB entries associated.

[0040] 对于高速缓存有效性结构420中的各跟踪的高速缓存条目,可以为各核处理器210维护标识符,使得高速缓存条目有效时该标识符可以被设置,其中有效性可以意味着相应的代码、数据或者TLB当前在那个处理器核210处被高速缓存。 [0040] cache entry for the cache validity structure of each track 420, 210 may maintain identifiers for the core processor, such that the cache entry is valid identifier may be provided, which may mean the corresponding validity code, or data TLB currently at that processor core 210 is cached. 类似地,如果相应的代码、 数据或者TLB在那个处理器核210处未被高速缓存,则有效性标识符可以被清除。 Similarly, if the appropriate code or data processor core 210 that is not cached in the TLB, the validity identifier may be cleared. 对于图4中所示的例子,对于核0和1可以清除与高速缓存标签0x200FFFX关联的有效性标识符, 而对于核2和3可以设置该有效性标识符。 For the example shown in FIG. 4, for the core 0 and 1 can clear the validity identifier associated 0x200FFFX cache tags, and for the core 2 and 3 may be provided that the validity of the identifier. 对于核0可以清除与高速缓存标签0x200AFFX 关联的有效性标识符,而对于核2、3和4可以设置该有效性标识符。 For nuclear 0 clear identifier associated with the effectiveness of the cache tag 0x200AFFX, 2, 3 and 4 and for the core of the validity of the identifier may be provided. 对于核0至3可以清除与高速缓存标签0x4401FFFX关联的有效性标识符。 For nuclear 0-3 to clear the effectiveness of the identifier associated with the cache tag 0x4401FFFX.

[0041] 使用高速缓存有效性结构420来跟踪的高速缓存有效性信息可以被中断控制器220收集。 [0041] Using the cache structure 420 to track the effectiveness of the cache validity information may be collected by the interrupt controller 220. 中断控制器220可以监视在系统总线310上的交互来跟踪感兴趣的各缓存行或者缓存页的当前高速缓存状态。 Interrupt controller 220 may monitor their interaction on the system bus 310 to track the current state of each cache line of the cache or cache page of interest. 高速缓存监视可以涉及监视高速缓存总线340以及监视系统总线310。 Monitoring may involve cache monitor cache bus 340 and a monitoring system bus 310.

[0042] 高速缓存有效性信息、例如使用高速缓存有效性结构420来跟踪的高速缓存有效性信息可以用于确定哪个处理器核210已经具有被高速缓存在处理器核210处的、与给定的中断处理程序134关联的代码、数据或者TLB条目。 [0042] Cache validity information, for example using a cache structure 420 to track the effectiveness of the cache validity information may be used to determine which processor core 210 having been already cached at the processor core 210, with a given 134 associated interrupt handler code, or data TLB entry. 具有超过中断处理程序134所需资源的本地高速缓存的处理器核210可以意味着该处理器核210可以以对于系统性能降低的消耗来执行中断处理程序134。 With more than 134 resources required interrupt handler local cache of the processor core 210 may mean that the processor core 210 can reduce the consumption of system performance to execute the interrupt handler 134.

[0043] 当出现中断时,中断控制器220可以计算与高速缓存局部性分数结构430关联的值。 [0043] When an interrupt occurs, the interrupt controller 220 may calculate the score 430 associated with a cache local structure value. 局部性分数可以基于在中断控制器220维护的高速缓存有效性结构420的各个实例中设置的标识符。 Locality score may be based on an identifier provided in the respective examples cache validity structure of the interrupt controller 220 maintains 420. 各处理器核210的局部性分数可以指示与中断处理程序134关联的多少代码和数据被各核高速缓存。 Locality fraction of each processor core 210 may indicate the interrupt handler 134 associated with the number of the cores are code and data caches. 在一些例子中,局部性分数可以是在与各处理器核210关联的Ll高速缓存320中有效的被跟踪的代码和数据缓存行的百分比。 In some instances, the score may be a percentage local code and data cache line in Ll cache 320 is associated with each processor core 210 effectively tracked. 在另外一些例子中,评分功能可以包括TLB条目、Ll高速缓存320、L2高速缓存325中的有效缓存行的百分比加权和,或者其任意组合。 In other instances, the scoring function may include TLB entries, Ll cache 320, the effective percentage weighting of cache lines of the L2 cache 325 and, or any combination thereof. 具有高的局部性分数的处理器核210可以优选用于为待处理的中断服务,因为高速缓存局部性可以意味着处理器核210可以以降低的开销来执行关联的中断处理程序134。 Fraction having a high local processor core 210 may be preferably used to service a pending interrupt, because the cache locality may mean that the processor core 210 may be performed to reduce the overhead associated with the interrupt handler 134.

[0044] 对于图4中所示的例子,与高速缓存标签0x200FFFX关联的高速缓存局部性分数针对核0和1具有值0,针对核2具有值1,而针对核3具有值3。 [0044] For the example shown in FIG. 4, the cache associated with the local score 0x200FFFX cache tag for the core 0 and 1 has a value of 0, has a value of 1 for the core 2, and has a value of 3 for the core 3. 与高速缓存标签0X200AFFX 关联的高速缓存局部性分数针对核0和1具有值0,针对核2和3具有值1。 Local cache associated with the score cache tag for 0X200AFFX core 1 has a value of 0 and 0, has a value of 1 for the core 2 and 3. 与高速缓存标签0x4401FFFX关联的高速缓存局部性分数针对核0和1可以具有值1,而针对核2和3具 Local cache associated with the score cache tag 0x4401FFFX for the core 0 and 1 may have a value of 1, the core 2 and 3 for

有值0。 The value 0.

[0045] 现在参照图5,提供了关于这里描述的用于在多处理器内分配中断的实施例的附加细节。 [0045] Referring now to Figure 5, provides additional details for distributing multiprocessor interrupt on the described embodiments herein described. 特别地,图5是示出了根据这里提出的实施例的方面的、用于将中断指派给当前空闲或者为最低优先级任务服务的处理器核的过程500的方面的流程图。 In particular, FIG. 5 is a diagram illustrating an embodiment in accordance with aspects of the embodiments set forth herein for the flowchart of the interrupt currently idle or aspects of the lowest service priority task of the processor core 500 is assigned to process.

[0046] 应当理解,这里所描述的逻辑操作:(1)实现为在计算系统上运行的、计算机实施的动作或者程序模块的序列;和/或(2)实现为计算系统内的互联的机器逻辑电路或者电路模块。 [0046] It should be appreciated that the logical operations described herein: (1) implemented to run on a computing system, the sequence of acts or program modules computer-implemented; and / or (2) is implemented as interconnected within the computing system of the machine logic circuits or circuit modules. 该实施是取决于计算系统的性能和其他要求的选择的问题。 This embodiment is a matter of choice dependent on the performance and other requirements of the computing system. 相应地,这里所描述的逻辑操作被不同地称为状态操作、结构装置、动作或者模块。 Accordingly, the logical operations described herein are referred to variously as states operations, structural devices, acts or modules. 这些操作、结构装置、动作和模块可以用软件、固件、专用数字逻辑及其任意组合来实施。 These operations, structural devices, acts and modules may be implemented in software, firmware, special purpose digital logic, and any combination thereof. 还应当理解的是,可以执行比附图中和这里所描述的更多或者更少的操作。 It should also be appreciated that it is possible to perform more or fewer operations than in the drawings and described herein. 这些操作也可以顺序地、并行地或者不同于这里所描述的顺序地执行。 These operations may be performed sequentially, in parallel or in different order than the described herein.

[0047] 该过程500可以在操作510开始,其中可以基于在各处理器核210处执行的当前任务305的优先级水平来维护各处理器核210的优先级水平。 [0047] The process 500 may begin at operation 510, which may be based on the current task execution of the processor core 210 at each priority level 305 to maintain each of the processor core 210 priority level. 这种优先级水平信息可以在中断控制器220处在当前任务优先级水平结构410中维护。 This priority level information 220 in the current task priority level structure in the interrupt controller 410 to maintain. 指示最低可能优先级的缺省优先级水平值可以用于指示处理器核210当前空闲。 Indicates the lowest possible priority level default priority value may be used to indicate the processor core 210 is currently idle.

[0048] 接下来在操作520中,接收与特定中断处理程序134关联的中断。 [0048] Next, at operation 520, receives 134 a particular interrupt handler associated with the interrupt. 所接收的中断可以在中断线225上到达中断控制器220。 The received interrupt can break 225 on the landing 220 in the interrupt controller. 在操作530中,中断控制器220可以选择处理器核210用于执行与待处理的中断关联的中断服务处理程序134。 In operation 530, the interrupt controller 220 may choose to interrupt the processor core 210 associated with the pending interrupt execution of the service handler 134. 可以基于由操作510在当前任务优先级水平结构410中跟踪的优先级水平信息来选择处理器核210。 In operation 510 may be based on the priority level information 410 to track the current task priority level structure selection processor core 210. 例如,具有较低优先级水平的处理器核210可以被指派通过执行中断处理程序134来为待处理的中断服务的任务。 For example, with a lower priority level of the processor core 210 may be assigned the task 134 to interrupt service to be processed by executing the interrupt handler. 处理器核210可能具有较低的优先级水平,因为该处理器核具有缺省的优先级水平值指示该处理器核210当前空闲。 The processor core 210 may have a lower priority level as the processor core has a default priority level indicating that the processor core 210 is currently idle. 根据实施例,该缺省优先级水平可以是用于处理器核210的最低可能优先级。 According to an embodiment, the default priority level may be the lowest possible priority to the processor core 210. 不是抢占或者中断在另外的处理器核210上的较高优先级的当前任务305,而是在空闲的或者执行具有低优先级的当前任务305的处理器核210处为中断服务,可以对系统性能具有降低的负面影响。 Not to seize or to interrupt the current higher priority task 305 on a separate processor core 210, but with a core 210 processor, a low-priority task of the current 305 to interrupt service at idle or execution, the system can performance has a negative impact reduced.

[0049] 在操作540中,(在操作530中确定的)被选择的处理器核210或者目标核可以被用信号通知来执行中断处理程序134为待处理的中断服务。 [0049] In operation 540, (determined in operation 530) the selected target processor core 210 or the core may be performed to signal the interrupt handler 134 to service the pending interrupt. 信号通知可以通过总线线路来进行,其通过使用专用的信号线、作为中断总线215上的消息、或者通过本领域普通技术人员会理解的任何其他信号通知机制来进行。 Signaling may be performed by a bus line, any other signaling mechanisms by using a dedicated signal line, as a message on the interrupt bus 215, or by those of ordinary skill in the art will appreciate that to perform. 一旦完成了中断处理程序134的执行,被选择的处理器核210可以恢复其当前任务305的执行。 Once complete interrupt handler executes 134, 210 selected processor core can resume the implementation of its current task 305. 过程500可以在操作540之后终止。 Process 500 may terminate after operation 540. [0050] 现在参照图6,提供了关于这里所提出的用于在多处理器内指派中断的实施例的附加的细节。 [0050] Referring now to Figure 6, it provides additional details regarding an embodiment of assigning interrupts in a multiprocessor herein the proposed. 特别地,图6是示出了根据这里所提出的实施例的方面的、用于基于高速缓存状态信息将中断指派给处理器核的过程600的方面的流程图。 In particular, FIG. 6 is a flowchart illustrating aspects of the cache status information based on the processor core assigned to the interrupt process 600 in accordance with aspects of the embodiments set forth herein of the embodiment for.

[0051] 该过程600可以在操作610开始,其中可以维护各处理器核210的高速缓存状态信息。 [0051] The process 600 may begin at operation 610, which can maintain the status information of each cache of the processor core 210. 高速缓存有效性结构420或者指示器可以由中断控制器220维护来跟踪处理器核210处的高速缓存状态信息,因为其与中断处理程序134相关。 Cache validity indicator may structure 420 or 220 to maintain cache status information to track the processor core 210 by the interrupt controller, because it is associated with the interrupt handler 134. 高速缓存有效性结构420可以用于跟踪与特定中断处理程序134关联的任何代码、数据或者相关的TLB条目是否当前在各处理器核210处被高速缓存。 Any code cache structure 420 may be used to track the effectiveness of a particular interrupt handler 134 associated, TLB entries associated data is currently or at each processor core 210 is cached.

[0052] 接下来,在操作620中,接收到与特定中断处理程序134关联的中断。 [0052] Next, in operation 620, receives a particular interrupt handler 134 associated with interrupt. 被接收到的中断可以在中断线225上到达中断控制器220。 Interrupt is received can reach 220 in the interrupt controller interrupt line 225. 在操作630中,中断控制器220可以确定与高速缓存局部性分数结构420关联的值。 In operation 630, the interrupt controller 220 to determine the value associated with the cache of the local structure 420 fraction. 局部性分数可以基于在中断控制器220维护的高速缓存有效性结构420的各个实例中设置的标识符。 Locality score may be based on an identifier provided in the respective examples cache validity structure of the interrupt controller 220 maintains 420. 各处理器核210的局部性分数可以指示与中断处理程序134关联的多少代码和数据被各核高速缓存。 Locality fraction of each processor core 210 may indicate the interrupt handler 134 associated with the number of the cores are code and data caches.

[0053] 在操作640中,中断控制器220可以确定要为待处理的中断服务的、用于执行中断服务处理程序134的处理器核210 (目标核)。 [0053] In operation 640, the controller 220 may determine the interrupt to be processed interrupt service for the interrupt service handler 134, the processor core 210 (target core). 该确定可以基于高速缓存有效性或者高速缓存局部性来进行。 This determination can be made based on the effectiveness of the cache or cache locality. 例如,可以检查高速缓存有效性结构420或者高速缓存局部性分数结构420来确定哪个处理器核210在其高速缓存中已经有与中断处理程序134关联的最多资源。 For example, you can check the validity of the cache structure 420 or cache locality fraction structure 420 to determine which processor core 210 in its cache has the most resources and associated interrupt handler 134. 与中断处理程序134关联的资源可以包括代码、数据和相关的TLB条目。 Resources associated with the interrupt handler 134 may include code, data and associated TLB entry. 不是使用其中执行从存储器获取未被高速缓存的代码或者数据的另外的处理器核210,而是在具有增大的量的被高速缓存的资源的处理器核210处为中断服务,可以对系统性能具有降低的负面影响。 Wherein instead of using the implementation of access code or uncached data from the memory of another processor core 210, but at the resource cache processor core 210 has an increased amount of the interrupt service, the system can performance has a negative impact reduced.

[0054] 在操作650中,在操作640中确定的、被选择的处理器核210或者目标核可以被用信号通知执行中断处理程序134来为待处理的中断服务。 [0054] In operation 650, it is determined at operation 640, the selected processor core 210 or the core may be the target interrupt handler 134 to signal the execution of pending interrupt. 信号通知可以通过总线线路来进行,其通过使用专用的信号线、作为中断总线215上的消息、或者通过本领域普通技术人员会理解的任何其他信号通知机制来进行。 Signaling may be performed by a bus line, any other signaling mechanisms by using a dedicated signal line, as a message on the interrupt bus 215, or by those of ordinary skill in the art will appreciate that to perform. 一旦完成了中断处理程序134的执行,被选择的处理器核210可以恢复其当前任务305的执行。 Once complete interrupt handler executes 134, 210 selected processor core can resume the implementation of its current task 305. 过程600可以在操作650之后终止。 Process 600 may terminate after operation 650.

[0055] 现在参照图7,提供了关于这里所提出的用于在多处理器内分配中断的实施例的附加的细节。 [0055] Referring now to Figure 7, provides additional details regarding proposed here for allocating interrupts in a multiprocessor embodiment. 特别地,图7是示出了根据这里所提出的实施例的方面的、用于基于组合的高速缓存状态信息和优先级将中断指派给处理器核的过程700的方面的流程图。 In particular, FIG. 7 is a flowchart illustrating aspects set forth herein in accordance with aspects of the embodiments of, based on the combined cache status information and the priority assigned to the processor core interrupt process 700. 该过程700 在操作710开始,其中可以基于在各处理器核210执行的当前任务305的优先级水平来维护各处理器核210的优先级水平。 The process 700 begins at operation 710, which may be based on the respective current task 210 executed by the processor core 305 priority level of each processor core 210 to maintain the priority level. 这种优先级信息可以在中断控制器220处在当前任务优先级水平结构410中维护。 This priority information 220 may be in the current task priority level structure in the interrupt controller 410 to maintain. 可以使用指示最低可能优先级的缺省优先级水平值来指示处理器核210当前空闲。 You can use the lowest possible priority indicating the priority level of the default values ​​to indicate the processor core 210 is currently idle.

[0056] 在操作720中,可以维护针对各处理器核210的高速缓存状态信息的指示器。 [0056] In operation 720, the pointer information may be maintained for each cache status of the processor core 210. 高速缓存有效性结构420可以被中断控制器220维护来跟踪处理器核210处的高速缓存状态信息,因为其与中断处理程序134相关。 Cache validity structure 420 may be interrupt controller 220 to maintain cache status information to track the processor core 210, 134 because it is associated with the interrupt handler. 高速缓存有效性结构420可以用于跟踪与特定中断处理程序134关联的任何代码、数据或者相关的TLB条目是否当前在各处理器核210处被高速缓存。 Any code cache structure 420 may be used to track the effectiveness of a particular interrupt handler 134 associated, TLB entries associated data is currently or at each processor core 210 is cached.

[0057] 在操作730中,接收与特定中断处理程序134关联的中断。 [0057] In operation 730, the particular interrupt handler receives the interrupt 134 is associated. 所接收的中断可以在 The interruption can be received

12中断线225上到达中断控制器220。 Break 225 on the landing 12, the interrupt controller 220.

[0058] 在操作740中,中断控制器220可以基于各处理器核210的高速缓存局部性和优先级水平来确定组合分数。 [0058] In operation 740, the interrupt controller 220 may be based cache locality and priority levels of the processor core 210 to determine the combined score. 可以在中断控制器220处在当前任务优先级水平结构410中维护优先级水平信息。 220 may be in the current task priority level structure in the interrupt controller 410 to maintain the priority level information. 高速缓存局部性可以从高速缓存局部性分数结构420中获得。 Cache locality can be obtained from the local cache structure 420 scores. 局部性分数可以基于在中断控制器220维护的高速缓存有效性结构420的各个实例中设置的标识符。 Locality score may be based on an identifier provided in the respective examples cache validity structure of the interrupt controller 220 maintains 420. 可以使用数学函数来将最低优先级与最高局部性分数组合。 You can use a mathematical function to the lowest priority with the highest combined scores locality. 例如,针对各处理器核的局部性分数可以被标准化到与可能的优先级水平的范围相同的范围,并且随后当前任务优先级水平可以被从该分数减去。 For example, the score for each local processor core may be normalized to the same range of possible priority level range, and then the current task priority level can be subtracted from the score. 对于本领域普通技术人员而言,其他用于将所述两种因素结合的关系是清楚的。 For those of ordinary skill in the art, other relations for bonding the two factors is apparent.

[0059] 在操作750中,中断控制器220可以选择要为待处理的中断服务的、用于执行中断处理程序134的处理器核210或者目标核。 [0059] In operation 750, the interrupt controller 220 may be selected to service the pending interrupt for the processor core execute the interrupt handler 210 or 134 target core. 该确定可以基于操作740中确定的组合分数来进行。 The determination may be performed based on the operation determined in 740 combined score. 组合分数可以在将中断指派给执行低优先级任务的处理器核210与将中断指派给在其本地高速缓存中已经具有更多的用于中断处理程序134的资源的处理器核210之间进行权衡。 Combined score can be assigned to execute the low priority task will be interrupted and the processor core 210 between the already assigned to the processor core 210 has more resources for the interrupt handler 134 in its local cache in the interrupt trade off. 在对这些标准进行了权衡的处理器核210处对中断进行服务可具有对系统性能降低的负面影响。 To interrupt at the processor core 210 of these standards have been weighed against the service may have a negative impact on system performance degradation. 其他用于确定中断服务处理器核210的标准可以被使用或者与这些标准结合,而并没有背离本公开的精神或者范围。 Other criteria for determining the interrupt service processor core 210 or may be used in combination with these standards, and without departing from the spirit or scope of the disclosure. 可以对这些标准进行选择来降低为了服务中断的多处理器系统的有效开销。 These criteria can be selected to reduce the effective cost of multiprocessor systems for service interruptions.

[0060] 在操作760中,在操作750中确定的、被选择的处理器核210或者目标核可以被用信号通知执行中断处理程序134来为待处理的中断服务。 [0060] In operation 760, in operation 750 is determined, the selected processor core 210 or the core may be the target to be processed 134 to interrupt service signaled interrupt handler execution. 信号通知可以通过总线线路来进行,其通过使用专用的信号线、作为中断总线215上的消息、或者通过本领域普通技术人员会理解的任何其他信号通知机制来进行。 Signaling may be performed by a bus line, any other signaling mechanisms by using a dedicated signal line, as a message on the interrupt bus 215, or by those of ordinary skill in the art will appreciate that to perform. 一旦完成了中断处理程序134的执行,被选择的处理器核210可以恢复其当前任务305的执行。 Once complete interrupt handler executes 134, 210 selected processor core can resume the implementation of its current task 305. 过程700可以在操作760之后终止。 The process 700 may terminate after operation 760.

[0061] 参照图8,其中示出了示例性的计算系统用于实施各实施例。 [0061] Referring to FIG 8, there is shown an exemplary computing system for implementing various embodiments. 该计算系统包括计算机10。 The computing system includes a computer 10. 计算机10可以包括处理器11、存储器12以及一个或多个驱动器13。 The computer 10 may include a processor 11, a memory 12 and a driver 13 or more. 驱动器13 及其关联的计算机存储介质可以提供计算机可读指令的存储、数据结构的存储、程序模块23的存储和其他用于计算机10的数据的存储。 The computer storage medium drive 13 may be provided and its associated computer-readable instructions stored, storing the data in data structures, program modules and other 23 for the computer 10. 计算机10可以实施为传统计算机系统、嵌入式控制计算机、膝上电脑或者服务器计算机、移动设备、机顶盒、公用电话亭、车辆信息系统、移动电话、定制的机器或者其他硬件平台。 The computer 10 may be implemented as a conventional computer systems, embedded control computer, laptop or server computers, mobile devices, set-top boxes, kiosks, vehicle information systems, mobile phones, customized machines or other hardware platforms. 处理器11可以是通用处理器、处理器核、多处理器、多核处理器、图形处理器、数字信号处理(DSP)处理器、在专用集成电路(ASIC)中实现的定制的计算设备、在现场可编程门阵列(FPGA)中实现的定制的计算设备、在任何类型的可编程逻辑中实现的定制的计算设备、状态机、可重新配置的处理器、任何其他处理单元或者其任何组合或者重复。 The processor 11 may be a general purpose processor, a processor core, multi-processor, multi-core processor, a graphics processor, a digital signal processing (DSP) processor, a custom computing devices implemented in application specific integrated circuit (ASIC), the a field programmable gate array (FPGA) customized computing device implemented customized computing device implemented in any type of programmable logic, state machines, reconfigurable processor may be any other processing units, or any combination thereof, or repeat.

[0062] 驱动器13、其他存储设备或者它们关联的计算机可读存储介质可以存储操作系统21、应用程序22、程序模块23和数据库24。 [0062] The driver 13, other storage devices or their associated computer-readable storage medium may store an operating system 21, application 22, database 24 and program module 23. 计算机10可以包括用户输入设备15,用户可以通过该用户输入设备来输入命令和数据。 The computer 10 may include a user input device 15, the user may enter commands and data via the user input device. 输入设备可以包括电子数字转换器、麦克风、键盘、指示设备或者其任意组合。 The input device may include an electronic digitizer, a microphone, a keyboard, a pointing device, or any combination thereof. 指示设备的例子可以包括鼠标、跟踪球、光笔、触摸屏或者触摸板。 Examples of the pointing device may include a mouse, trackball, light pen, a touch screen or a touch pad. 其他至计算机10的输入设备可以包括操纵杆、游戏手柄、卫星天线、扫描仪等等。 Other input devices to the computer 10 may include a joystick, game pad, satellite dish, scanner or the like. 输入设备可以通过用户输入接口连接到处理器11,该用户输入界面耦合到系统总线。 The input device may be connected to the processor 11 via the interface user input, the user input interface coupled to the system bus. 输入设备也可以通过其他接口和总线结构如并行端口、游戏端口或者通用串行总线(USB)来连接。 The input device such as a parallel port may be connected by other interface and bus structures, game port or a universal serial bus (USB) to connect to. 计算机如计算机10也可以包括其他外围输出设备例如扬声器,其可以通过输出外围设备接口19或者类似接口来连接。 Computer The computer 10 may also include other peripheral output devices such as speakers, which may be through an output peripheral interface 19 is connected to the interface or the like.

[0063] 计算机10可以在联网环境中工作,该联网环境使用了至一个或多个计算机的逻辑连接,例如远程计算机连接到网络接口16。 [0063] The computer 10 may operate in a networked environment, the networked environment using logical connections to one or more computers, such as remote computer connected to a network interface 16. 远程计算机可以是个人计算机、服务器、路由器、网络PC、对等设备或者其他普通的网络节点。 The remote computer may be a personal computer, a server, a router, a network PC, a peer device or other common network node. 远程计算机可以包括这里关于计算机10 所描述的元件中的多个或者全部元件。 The remote computer may comprise elements herein described relative to the computer 10 in a plurality or all of the elements. 联网环境可以包括网络(WAN)、局域网(LAN)、内联网、英特网或者它们的组合。 Networked environment may include network (WAN), a local area network (LAN), an intranet, the Internet, or a combination thereof.

[0064] 当使用在LAN或者无线LAN(WLAN)联网环境中时,计算机10可以通过网络接口16或者网络适配器连接到LAN。 [0064] When used in a LAN or a wireless LAN (WLAN) networking environment, the computer 10 may be connected to the LAN 16 through a network interface or a network adapter. 当使用在WAN联网环境中时,计算机10可以包括调制解调器或者其他机制用于建立通过WAN的通信。 When used in a WAN networking environment, the computer 10 may include a modem or other mechanisms for establishing communication over the WAN. WAN可以包括英特网、所阐述的网络18、各种其他网络或者它们的任意组合。 WAN may include the Internet 18, various other network, or any combination thereof are set forth in the network. 应当理解,可以使用在计算机之间建立通信链接、环、格网、总线、云、或者网络的其他机制。 It should be understood that establishing a communications link between the computers, a ring, a grid, a bus, cloud, network, or other mechanisms may be used.

[0065] 根据一个或多个实施例,计算机10可以被配置为使得处理器11和/或程序模块23可以与基于多处理器110的计算机一同运行或者作为基于多处理器110的计算机来运行,或者作为执行根据这里提出的实施例的多处理器110的虚拟化的计算机来运行。 [0065] According to one or more embodiments, the computer 10 may be configured such that processor 11 and / or program modules 23 may be a multiprocessor 110-based computer running with or as to run on the multiprocessor computer 110, or as performed according to the embodiment set forth herein multiprocessor virtualized computer 110 to run. 多处理器110或者多处理器110的虚拟表示可以支持动态中断调度。 Virtual multi-processor or multi-processor 110 110 expressed support dynamic interrupt scheduling. 计算机10可以包括与驱动器13或者其他存储设备关联的物理的计算机可读存储介质的一个或多个实例。 The computer 10 may comprise 13 or other physical device drivers associated with the memory a computer readable storage medium or a plurality of instances. 系统总线可以使得处理器11能够将代码和/或数据从计算机可读存储介质中读取或者写入其中。 The system bus 11 may be such that the processor is able to code and / or data read from a computer-readable storage medium, or written to. 该介质可以代表使用任何合适的技术来实现的存储元件形式的装置,包括但不局限于半导体、磁性材料、光学介质、电存储装置、电化学存储装置或者任何其他的这种存储技术。 The medium may represent any suitable technique used to implement the storage element in the form of means, including but not limited to semiconductors, magnetic materials, optical media, electrical storage means, an electrochemical storage device, or any other such storage techniques. 该介质可以代表与存储器12关联的部件,无论特征是否为RAM、ROM、闪存或者其他类型的易失性或者非易失性存储器技术。 The medium may represent a memory associated with the member 12, regardless of whether the features of RAM, ROM, flash memory, or other type of volatile or non-volatile memory technology. 该介质也可以代表辅助存储装置,无论是否实施为存储驱动器13。 The medium may also represent an auxiliary storage apparatus, whether implemented as a storage drive 13. 硬驱动实现的特征可以在于固态,或者可以包括存储磁性编码信息的旋转介质。 Characterized in that the hard drive may be implemented solid, or may include a rotating magnetic medium for storing encoded information.

[0066] 存储介质可以包括一个或多个程序模块23。 [0066] The storage medium may comprise one or more program modules 23. 程序模块23可以包括软件指令,当被加载到处理器11中并且执行时,这些软件指令将通用计算系统转换为根据本发明来定制的专用计算系统。 Program module 23 may include software instructions that, when loaded into the processor 11 and executed, the software instructions for the general purpose computing system according to the present invention is converted customized special purpose computing system. 如本说明书中详细描述的那样,程序模块23可以提供各种工具或者技术,计算机10可以通过该工具或者技术来参与到使用这里所讨论的部件、逻辑流和/或数据结构的全部的系统或者操作环境中。 As described in detail in this specification, the program module 23 may provide various tools or techniques, the computer 10 may be used to participate discussed herein member by the tool or technique, all of the logic flow of the system and / or data structures, or operating environment.

[0067] 处理器11可以由任意数量的晶体管或者其他电路元件来构建,它们可以单独地或者共同地具有任意数量的状态。 [0067] The processor 11 may be constructed from any number of transistors or other circuit elements, which may either collectively have any number of states separately. 更确切地说,处理器11可以作为状态机或者有限状态机来工作。 More specifically, the processor 11 may operate as a state machine or a finite state machine. 这种机构可以通过加载程序模块23中包含的可执行指令来转换到第二机构或者特定的机构中。 Such means may be switched to the second specific mechanism or mechanisms by loader modules 23 executable instructions contained. 这些计算机可执行的指令可以通过指定处理器12如何在状态之间转变来转换处理器11,由此将构成处理器11的晶体管或者其他电路元件从第一机构转换到第二机构,其中第二机构可以被具体地配置用于支持动态中断调度。 These computer-executable instructions may be converted by the processor 11 to specify how the processor 12 transitions between states, thereby constituting a transistor or other circuit elements of the processor 11 from the first means to the second conversion means, wherein the second institutions can be specifically configured to support dynamic interrupt scheduling. 各机构的状态也可以通过接收来自一个或多个用户输入设备15、网络接口16、其他外围设备、其他接口、一个或多个用户或者其他行为者的输入来被转换。 The state of each mechanism may be by receiving from one or more user input devices 15, network interface 16, other peripherals, other interfaces, one or more user input or other actors to be converted. 各机构也可以转换各种输出设备如打印机、扬声器、 视频显示器等等的状态或者各种物理特征。 Each mechanism may also convert various output devices such as a printer, a speaker, a video display state or the like of various physical characteristics.

[0068] 将程序模块23编码也可以转换存储介质的物理结构。 [0068] The coding program modules 23 can also convert the physical structure of the storage medium. 在本说明书的不同实施方式中,物理结构的特定转换可以取决于各种因素。 In various embodiments of the present description, the particular physical configuration of the conversion may depend on various factors. 这种因素的例子可以包括(但不局限于):用于实现存储介质的技术,无论该存储介质特征是否为初级或者次级存储装置等等。 Examples of such factors may include (but are not limited to): technology for the storage medium, wherein the storage medium regardless of whether the primary or secondary storage device and the like. 例如,如果存储介质实现为基于半导体的存储器,当软件被编码在其中时,程序模块23可以转换半导体存储器12的物理状态。 For example, if the storage medium is implemented as semiconductor-based memory, when the software is encoded therein, the program module 23 may transform the physical state of the semiconductor memory 12. 例如,软件可以转换构成半导体存储器12的晶体管、 电容器或者其他分立电路元件的状态。 For example, software may transform the semiconductor memory transistor 12, a capacitor or other discrete circuit elements.

[0069] 作为另一个例子,存储介质可以使用磁性或者光学技术如驱动器13来实现。 [0069] As another example, the storage medium may be used as a magnetic or optical technology driver 13 is achieved. 在这种实现中,当软件被编码在其中时,程序模块23可以转换磁性介质或者光学介质的物理状态。 In such an implementation, when the software is encoded therein, the program module 23 may transform the physical state of the magnetic medium or an optical medium. 这些转换可以包括改变给定的磁性介质中的特定位置的磁性特征。 These transformations may include altering the magnetic characteristics of the magnetic medium is given a particular location. 这些转换也可以包括改变给定的光学介质中的特定位置的物理特征或者特点,以改变那些位置的光学特征。 These transformations may also include altering the physical characteristics of the specific location or characteristics given optical medium, to change the optical characteristics of those locations. 应当理解,物理介质的各种其他转换也是可能的,而并未脱离本说明书的范围和精神。 It should be understood that various other transformations of physical media are possible, without departing from the scope and spirit of the present specification.

[0070] 本公开并未根据本申请中所描述的特定实施例而受到限制,这些实施例旨在对各种方面进行说明。 [0070] The present disclosure is not limited by the present embodiment in accordance with certain embodiments described herein, these embodiments are intended to illustrate various aspects. 如对于本领域技术人员来说将会是明显的那样,可以进行许多修改和变化而并不脱离其精神和范围。 As will be apparent, as the skilled person, many modifications and variations may be made without departing from the spirit and scope thereof. 本公开的范围内的功能上等同的方法和装置以及本申请中所列举的那些,根据以上的描述对于本领域技术人员将会是明显的。 A method and apparatus are functionally equivalent within the scope of the present disclosure and those recited herein, the above description to those skilled in the art will be apparent. 这种修改和变化旨在落入所附权利要求的范围内。 Such modifications and variations are intended to fall within the scope of the appended claims. 本公开仅由所附权利要求的术语连同这种权利要求被冠以的等同物的全部范围来进行限制。 The present disclosure is limited only by the terms of the appended claims along with the full scope of equivalents to be known as such claims to be limiting. 要理解的是,本公开不限于特定的方法、组件、试剂、化合物成分或者生物系统,其当然可以变化。 It is to be understood that the present disclosure is not limited to particular methods, components, agents, compounds or constituents of biological systems, which can, of course vary. 还要理解的是,本申请中所使用的技术术语仅用于对特定的实施例进行描述的目的,并非旨在进行限制。 It is also understood that the technical term used herein is for the purpose of described particular embodiments is not intended to be limiting. [0071] 针对本申请中所使用的任何基本上为复数的和/或单数的术语,本领域技术人员可以适合于情况和/或应用进行从复数到单数和/或从单数到复数的诠释。 [0071] Any substantially and / terminology plural or singular, one skilled in the art may be adapted to the case and / or applications and / or interpretation from the plural to the singular from the singular to the plural for the present application are used. 在本申请中为了清楚起见而明确地阐述了各种单/复数变化。 In the present application, for clarity expressly set forth various singular / plural permutations.

[0072] 本领域技术人员将会理解的是,通常,本申请中、特别是所附权利要求(例如所附权利要求的主体)中所使用的术语通常旨在作为“开放式的”术语(例如,术语“包括”应当被解释成“包括但不限于”、术语“具有”应当被解释成“至少具有”、术语“包含”应当被解释成“包含但不限于”、等等)。 [0072] Those skilled in the art will appreciate that, in general, in this application, especially in the appended claim "open" terms (requirements (e.g., the body of the appended claims) the term used generally intended as For example, the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," the term "comprising" should be interpreted as "including but not limited to," etc.). 本领域技术人员将会进一步理解的是,如果旨在引入具体数量的权利要求重述,这种意图将会被明确地表述在权利要求中,而在没有这种表述的情况下, 则不存在这种意图。 Those skilled in the art will further appreciate that, if the intended specific number of an introduced claim restatement of such intent will be explicitly recited in the claim, and in the absence of such recitation case, then there is no that intention. 例如,作为对理解的辅助,随后的所附权利要求可以包含使用引导性的用语“至少一个”和“一个或多个”,以引入权利要求的重述。 For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrase "at least one" and "one or more" to introduce claim restatement. 然而,使用这些用语不应当被解释成隐含通过不定冠词“一”或“一个”来引入权利要求的重述而将任何包含这种引入权利要求重述的特定权利要求限制于仅包含一个这种重述的实施例,即使是当同样的权利要求包括引导性的用语“一个或多个”或“至少一个”和诸如“一”、“一个”的不定冠词的时候(例如,“一”和/或“一个” 一般应当被阐释成意思是“至少一个”或“一个或更多个”);同样的内容对于被用来引入权利要求重述的定冠词的使用同样适用。 However, the use of these terms should not be interpreted as implicit to introduce claim restatement by the indefinite article "a" or "an" and any particular claim containing such introduced claim restate a requirement limited to comprising only this embodiment restatement embodiment, even when the same claim includes the term "one or more" or "at least one" and as "a", "an" indefinite articles introductory time (e.g., " a "and / or" an "should typically be interpreted to mean" at least one "or" one or more "); the same content to be definite articles used to introduce claim restated using the same applies. 另外,即使具体数量的引入的权利要求重述被明确地表述,本领域技术人员将会认识到的是,这种重述应当被解释成意思是至少为所表述的数量(例如,仅有“两个重述”的表述在没有其它修改内容的情况下意思是至少两个重述、或者两个或更多个重述)。 Further, even repeat a specific number of an introduced claim requirement is explicitly recited, those skilled in the art will recognize that such restatement should be interpreted to mean at least the number expressed (e.g., only " two repeat "expression means at least two repeat without further modify the contents of the case, or two or more repeat). 此外,在使用类似于“A、B以及C等等中的至少一个”的习惯用法的那些情形中,这种习惯用法通常旨在从本领域技术人员将会理解该习惯用法的角度出发(例如,“具有A、B以及C中的至少一个的系统”将会包括但不限于只具有A、只具有B、只具有C、同时具有A和B、同时具有A和C、同时具有B和C、和/或同时具有A、B和C等等的系统)。 Further, in those cases analogous to "A, B, and C, etc. in at least one" idioms in the idiom is intended from the skilled in the art will appreciate that the idiom perspective (e.g. "a, B, and C in the system at least one" would include but not be limited to systems that have a, B has only, having only C, having both a and B, while a and C, while B and C , and / or simultaneously with a, B and C together, etc.). 在使用类似于“A、B或者C等等中的至少一个”的习惯用法的那些情形中,这种习惯用法通常旨在从本领域技术人员将会理解该习惯用法的角度出发(例如,“具有A、B或者C中的至少一个的系统”将会包括但不限于只具有A、只具有B、只具有C、同时具有A和B、同时具有A和C、同时具有B和C、和/或同时具有A、B和C等等的系统)。 In those cases analogous to "A, B or C, etc. at least one of" idioms in the idiom is generally intended to those skilled in the art will appreciate that the idiom perspective (e.g., " a, B, or at least a system "C will be in but not limited to having only a, only B has, has only C, with a with a and B, having both a and C, and B having both are C, and / or simultaneously with a, B and C together, etc.). 本领域技术人员将会进一步理解的是,任何出现了两个或更多个可替选的术语的分开的词语和/或用语(无论在说明书、权利要求还是附图中)实质上均应当被理解成预见了包括这些术语中的一个、术语中的任一个、或者两个术语的这些可能性。 Those skilled in the art will further appreciate that the emergence of any two or more separable alternative terminology words and / or terms (whether in the description, the drawings or claimed) shall be substantially these possibilities foreseen understood to include one of these terms, either of the terms, or both terms. 例如,用语"A或B”将会被理解成包括“A”或者“B”或者“A和B”的可能性。 For example, the phrase "A or B" will be understood to include the possibility of "A" or "B" or "A and B" is.

[0073] 另外,在本公开的特征或方面以马库什组的形式被描述之处,本领域技术人员将会认识到的是,本公开也因而以马库什组的成分中的任意的各个成分或子组的形式被描述。 [0073] Further, in the present disclosure features or aspects in terms of Markush groups, being described, the skilled artisan will recognize that the present disclosure therefore also to the component in any Markush groups of in the form of individual components or sub-group are described.

[0074] 如本领域技术人员将会理解的,为了任何的以及所有的目的,例如在提供书面说明书的方面,本申请中所公开的所有范围也涵盖任何的以及所有的可能的子范围以及其子范围的组合。 [0074] As will be understood by those skilled in the art, for any and all purposes, such as in terms of providing a written description, all ranges disclosed in the present application also encompasses any and all possible subranges as well as combinations of subranges thereof. 任何所列出的范围均能够被容易地识别成充分的描述以及使同样的范围能够至少被分解成同等的两部分、三部分、四部分、五部分、十部分,等等。 Any listed range can be easily recognized both as fully described and causing at least the same range can be decomposed into two equal parts, three parts, quarters, fifths, tenths, and the like. 作为非限制性的例子, 本申请中所讨论的每个范围均能够被容易地分解成下三分之一、中三分之一以及上三分之一等等。 As a non-limiting example, each range discussed in the present application are capable of being readily broken down into a lower third, middle third and upper third and the like. 如本领域技术人员还将会理解的,诸如“直到”、“至少”、“大于”、“小于”等的所有语言均包括所表述的数量并且是指能够随之被分解成如以上所讨论的子范围的范围。 As those skilled in the art will further appreciate, terms such as "up to," "at least," "greater than," "less than," and the like include the number of all languages ​​is expressed and subsequently be decomposed into it refers to as discussed above range of sub-ranges. 最后, 如本领域技术人员将会理解的,范围包括各个单独的成分。 Finally, as will be understood by those skilled in the art, a range includes each individual component. 所以,例如,具有1-3个单元的组是指具有1、2或者3个单元的组。 Thus, for example, a group having 1-3 cells refers to groups having 1, 2, or 3 cells. 类似地,具有1-5个单元的组是指具有1、2、3、4或者5个单元的组,等等。 Similarly, a group having 1-5 cells refers to groups having 3, 4, or 5 cells, and so on.

Claims (20)

  1. 一种用于在多处理器计算系统中处理中断的方法,包括:在多处理器计算系统中维护与各处理器关联的状态信息;接收至多处理器计算系统的中断;基于状态信息来选择为中断服务的处理器;以及用信号通知所选择的处理器为中断服务。 A method in a multiprocessor computing system for handling interrupts, comprising: maintaining in a multiprocessor computing system associated with each processor status information; receiving computing system to multiprocessor interrupt; selected based on the state information is processor interrupt service; and a processor to signal the selected interrupt service.
  2. 2.根据权利要求1所述的方法,其中维护状态信息包括维护与各处理器的当前任务关联的优先级水平,并且确定处理器包括选择执行具有低优先级水平的当前任务的处理器。 2. The method according to claim 1, wherein maintaining comprises maintaining state information associated with the current priority level for each task of the processor, and the processor determining comprises selecting the current task execution processor having a low priority level.
  3. 3.根据权利要求2所述的方法,其中维护优先级水平包括从与多处理器计算系统关联的操作系统接收优先级水平。 3. The method according to claim 2, wherein the priority level comprises receiving a maintenance priority level from a multi-processor computing system associated with the operating system.
  4. 4.根据权利要求2所述的方法,其中维护优先级水平包括从与多处理器计算系统关联的用于任务切换的模块接收优先级水平。 4. The method according to claim 2, wherein the priority level comprises receiving a maintenance priority level for the module from the task switching and multiprocessor computing systems associated.
  5. 5.根据权利要求1所述的方法,其中维护状态信息包括维护与各处理器关联的高速缓存状态信息,并且确定处理器包括选择对于与服务中断关联的资源具有高的高速缓存局部性分数的处理器。 5. The method according to claim 1, wherein maintaining comprises maintaining cache status information associated with each processor state information, and resource determination processor includes selecting the service disruption associated with a high score cache locality processor.
  6. 6.根据权利要求5所述的方法,其中维护高速缓存状态信息包括维护高速缓存有效性结构。 6. The method according to claim 5, wherein maintaining comprises maintaining cache status information cache validity structure.
  7. 7.根据权利要求5所述的方法,其中选择具有高的高速缓存局部性分数的处理器包括计算与高速缓存局部性分数结构关联的值。 The processor 7. The method according to claim 5, wherein selecting the cache locality has a high score comprises a value associated with a locality calculate the score cache structure.
  8. 8.根据权利要求1所述的方法,其中确定处理器包括针对各处理器将与当前任务关联的优先级水平同对于与服务中断关联的资源的高速缓存局部性分数相组合。 8. The method according to claim 1, wherein the processor comprises determining, for each processor associated with the current task priority level with respect to the interrupt service resources associated cache locality combined score.
  9. 9. 一种用于在多处理器计算系统中处理中断的系统,包括:多个处理器核;用于从多处理器请求中断服务的中断线;以及中断控制器模块,其能够操作用于维护与多个处理器核的各处理器核关联的状态信息,接收中断,以及基于维护的状态信息标识用于为中断服务的所述多个处理器核之一。 A multiprocessor computing system for processing interrupt system, comprising: a plurality of processor cores; for interrupt request from the interrupt service multiple processors; and an interrupt controller module, which is operable with to maintain state information associated with each processor core of the plurality of processor cores, the receive interrupt, based on state information maintained for identifying one of said plurality of interrupt service processor cores.
  10. 10.根据权利要求9所述的系统,其中能够操作的中断控制器模块进一步能够操作用于用信号通知确定的处理器核为中断服务。 10. The system according to claim 9, wherein the controller is capable of interrupting operation of the processor core module is further operable for determining signaled interrupt service.
  11. 11.根据权利要求9所述的系统,其中维护状态信息包括维护与各处理器核的当前任务关联的优先级水平,并且确定多个处理器核之一包括选择执行具有低优先级水平的当前任务的处理器核。 Current 11. The system according to claim 9, wherein maintaining comprises maintaining state information associated with the current priority level for each task of the processor core, and determining comprises selecting one of a plurality of processor cores performing a low priority level the task processor cores.
  12. 12.根据权利要求11所述的系统,其中维护优先级水平包括从与多处理器计算系统关联的操作系统接收优先级水平。 12. The system according to claim 11, wherein the priority level comprises receiving a maintenance priority level from a multi-processor computing system associated with the operating system.
  13. 13.根据权利要求11所述的系统,其中维护优先级水平包括从与多处理器计算系统关联的用于任务切换的模块接收优先级水平。 13. The system according to claim 11, wherein the priority level comprises receiving a maintenance priority level for the module from the task switching and multiprocessor computing systems associated.
  14. 14.根据权利要求9所述的系统,其中维护状态信息包括维护与各处理器核关联的高速缓存状态信息,并且确定多个处理器核之一包括选择对于与服务中断关联的资源具有高的高速缓存局部性的处理器核。 14. The system according to claim 9, wherein maintaining the state information includes maintaining cache status information associated with each processor core, and determining one of the plurality of processor cores includes selecting resources and services associated with the interrupt have high cache locality of processor cores.
  15. 15.根据权利要求14所述的系统,其中维护高速缓存状态信息包括维护高速缓存有效性结构。 15. The system according to claim 14, wherein maintaining comprises maintaining cache status information cache validity structure.
  16. 16.根据权利要求14所述的系统,其中选择具有高的高速缓存局部性的处理器核包括计算与高速缓存局部性分数结构关联的值。 Processor core 16. The system according to claim 14, wherein selecting a cache having a high value calculation comprises locality associated with a fractional local cache structure.
  17. 17.根据权利要求9所述的系统,其中维护状态信息包括维护与各处理器核的当前任务关联的优先级水平,以及维护与各处理器核关联的高速缓存状态信息。 17. The system according to claim 9, wherein maintaining comprises maintaining state information associated with the current priority level for each task of the processor core, and maintaining cache status information associated with each processor core.
  18. 18.根据权利要求9所述的系统,其中确定多个处理器核之一包括针对各处理器核将与当前任务关联的优先级水平与高速缓存局部性分数组合。 18. The system according to claim 9, wherein determining one of the plurality of processor cores comprising a combination of scores for each local processor core associated with the current task priority level cache.
  19. 19. 一种计算机存储介质,具有存储于其上的计算机可执行指令,当所述指令被计算机系统执行时使得计算机系统:维护与多处理器计算系统的各处理器的当前任务关联的优先级水平; 维护与各处理器关联的高速缓存状态信息; 接收至多处理器计算系统的中断;基于高速缓存状态信息确定各处理器的高速缓存局部性分数; 计算针对各处理器平衡优先级水平和高速缓存局部性分数的值; 基于所计算的值来确定用于为中断服务的处理器;以及用信号通知所确定的处理器为中断服务。 19. A computer storage medium having computer-executable instructions stored thereon, the instructions when executed by a computer system cause the computer system: the maintenance associated with each processor, multi-processor computing system of the priority of the current task level; maintenance associated with each processor's cache status information; receiving an interrupt to multiprocessor computing system; determining for each processor's cache locality cache status information based on the score; balance calculated for each priority level processor and high-speed cache locality score value; based on the calculated value for the processor to determine the interrupt; and a processor signaling the determined interrupt service.
  20. 20.根据权利要求19所述的计算机存储介质,其中维护高速缓存状态信息包括维护高速缓存有效性结构。 20. The computer storage medium according to claim 19, wherein maintaining comprises maintaining cache status information cache validity structure.
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