RU194084U1 - Board for building digital systems - Google Patents

Abstract

The utility model relates to the field of microelectronics, namely to the development of electronic computing tools, and can be used to build digital computing and logical data processing systems that operate under the control of real-time operating systems based on the domestic high-performance universal 64-bit microprocessor with low energy consumption of 1890 VM108. The boards based on the domestic microprocessor have a wide range of supported peripheral devices and interfaces, and the possibility of installing a wide range of software. Boards based on the domestic 1890 BM108 microprocessor can be used to build standardized workstations and workstations. Practical results obtained as a result of developing a utility model and implemented during the development of the board based on the domestic 1890 VM108 microprocessor can be used in the development of new products and systems based on the microprocessor 1890 VM108. This utility model is also aimed at solving the problems of import substitution and expanding the product range based on Russian microprocessors. The technical result of using the utility model is the development of processor boards or processor modules with increased functionality. This technical result is achieved by the board for building digital systems, including a microprocessor that provides the operation of external interfaces, which differs from the prototype in that in As a microprocessor, it includes an 1890 BM108 microprocessor, which has inputs and outputs that ensure the operation of the following external interfaces: one channel of RAM; two PCI Express lanes; two channels of the USB 2.0 interface; two channels of the ULPI interface; four channels of the I2C interface; two channels of the Gigabit Ethernet interface; two channels of the SATA 3.0 interface; one channel of the LVDS interface with a resolution of up to 2048 × 1536; four channels of the UART interface with a speed of up to 115200 baud; two channels of Fast UART interface with a speed of up to 12.5 Mbps; two channels of CAN 2.0 interface; 32 GPIO input-output lines (general-purpose input / output); two multiplexed channels of information exchange (MKIO) with redundancy; JTAG in-circuit debugging interface, with support for EJTAG debugging mode; four channels of the SPI interface; Local Device Bus. 26 ill.

Description

The utility model relates to the field of microelectronics, namely to the development of electronic computing tools, and can be used to build digital systems of computational and logical data processing, operating under the control of real-time operating systems.

As part of the implementation of import substitution programs, it is necessary to increase the number of electronic computing tools developed using the domestic component base. This goal can be achieved by increasing the use of domestic electronic components in the development and modernization of electronic computing tools. For this, the nomenclature of the developed and used domestic components, including microprocessors having the necessary set of external and internal interfaces, for the implementation of the functions required from computing equipment, should be increased.

Currently, most electronic computing tools are built on processor boards or processor modules with a similar set of functional units and interfaces, but these products are mainly implemented on microprocessors of foreign manufacture.

Analogs are imported boards for domestic and industrial use, used to build personal workstations (personal computers) of various types, including monoblocks, as well as to build industrial automation systems. An example is motherboards:

- ASRock IMB-142;

- ASRock Q1900B-ITX;

- ASRock J3355B-ITX + Celeron J3355 onboard;

- ASRock J3455-ITX + Celeron J3455 onboard;

- Advantech AIMB-212N-S6A1E;

- Advantech AIMB-203G2-00A1E

- Intel D2500CC / D2500CCE.

As a prototype, the IMB-142 series board (www.asrockind.com/overview.ru.asp?Model=IMB-142%20Series) from ASRock Inc. can be used This board relates to motherboards in the industrial market segment. The motherboard IMB-142 is made in mini-ITX format. The Intel Dual-Core Atom CedarView Processor D2550 / N2600 / N2800 can be installed on the IMB-142 motherboard as a central processor. The IMB-142 motherboard provides the connection of two memory channels of the DDR3 SO-DIMM type, one PCI channel and one PCI Express channel.

The IMB-142 motherboard provides up to eight USB 2.0 channels, two SATA 2.0 channels and two Gigabit Ethernet channels based on two Intel WG82574L controllers.

The IMB-142 motherboard provides connection of one HDMI channel with a resolution of up to 1920 × 1200, one DVI-D channel with a resolution of up to 1920 × 1200, and one 18-bit LVDS channel with a resolution of up to 1440 × 900 based on the Intel PowerVR SGX545 video controller.

The disadvantage of this prototype is the use of imported microcircuitry as the central processor, which contradicts the policy of implementing import substitution programs, and, moreover, does not ensure the fulfillment of many functions that are in demand on the market, such as:

- the ability to work in difficult climatic conditions for a long period of time due to the reliability and technological support of domestic components;

- increase the safety factor of computer systems - the degree of power of attorney of the system.

The technical result of the application of the utility model is the development of processor boards or processor modules with increased functionality.

The specified technical result is achieved by the circuit board for building digital systems, including a microprocessor, which ensures the functioning of external interfaces, which differs from the prototype in that it includes a microprocessor 1890 VM108, which has inputs and outputs that provide the following external interfaces:

one channel of random access memory;

two PCI Express lanes;

two channels of the USB 2.0 interface;

two channels of the ULPI interface;

four channels of the I2C interface;

two channels of the Gigabit Ethernet interface;

two channels of the SATA 3.0 interface;

one channel of the LVDS interface with a resolution of up to 2048 × 1536;

four channels of the UART interface with a speed of up to 115200 baud;

two channels of Fast UART interface with a speed of up to 12.5 Mbps;

two channels of CAN 2.0 interface;

32 GPIO input-output lines (general-purpose input / output);

two multiplexed channels of information exchange (MKIO) with redundancy;

JTAG in-circuit debugging interface, with support for EJTAG debugging mode;

four channels of the SPI interface;

Local Device Bus.

The microprocessor 1890 BM108 is a domestic high-performance universal 64-bit microprocessor with low energy consumption (registration certificate RU 2018630007 from 01/11/2018).

The circuitry solutions that can be applied in the development of processor modules using a patented board based on the domestic 1890 BM108 microprocessor are shown in the figures - FIG. 1 - FIG. 26 where

FIG. 1 - An example of the use of a patented circuit board based on the 1890 VM108 microprocessor with the greatest functionality;

FIG. 2 - An example of connecting a memory channel of the DDR3 type;

FIG. 3 - List of elements for connecting the DDR3 interface;

FIG. 4 - An example of connecting a PCI Express channel;

FIG. 5 - Supplement to the example of FIG. 4 PCI Express channel connections;

FIG. 6 - List of elements for connecting the PCI Express interface;

FIG. 7 - An example of connecting USB 2.0;

FIG. 8 - List of elements for connecting the USB 2.0 interface;

FIG. 9 - An example of connecting I2C;

FIG. 10 - List of elements for connecting the I2C interface;

FIG. 11 - An example of a Gigabit Ethernet connection;

FIG. 12 - List of elements for connecting the Gigabit Ethernet interface;

FIG. 13 - An example of connecting SATA 3.0;

FIG. 14 - The list of elements for connecting the SATA 3.0 interface;

FIG. 15 - An example of connecting LVDS;

FIG. 16 - List of elements for connecting the LVDS interface;

FIG. 17 - An example of connecting memory chips;

FIG. 18 - List of elements for connecting memory chips;

FIG. 19 - An example of connecting UART and Fast UART interfaces;

FIG. 20 - List of elements for connecting UART and Fast UART interfaces;

FIG. 21 - Connection example CAN 2.0;

FIG. 22 - List of elements for connecting the CAN 2.0 interface;

FIG. 23 - An example of connecting a multiplex information exchange channel (MKIO);

FIG. 24 - A list of elements for connecting a multiplexed information exchange channel (ICIE);

FIG. 25 - An example of connecting the JTAG interface;

FIG. 26 - List of elements for connecting the JTAG interface.

The processor modules implemented using a patented motherboard based on a domestic microprocessor are modules designed to develop and debug software for the 1890 BM108 microprocessor, which is a high-performance universal 64-bit microprocessor with low power consumption, as well as to build digital systems for computing and logical data processing operating under the control of real-time operating systems.

Using a patented card, one memory channel of the DDR3 SO-DIMM type can be implemented, for which there are corresponding inputs / outputs, according to the figure of FIG. 2 and the table of FIG. 3. The RAM controller of the 1890 VM108 microprocessor supports up to 8 GB of synchronous dynamic memory of the DDR3 / DDR3L SDRAM type, while the logical model of the memory controller is the same for DDR3 and DDR3L. In this case, it is possible to use memory chips of the DDR2 type with the corresponding voltage. The memory controller supports two channels with monitoring and error correction according to the Hamming code. The width of the data bus is 64 bits, the buses of the correction codes are 8 bits. On the board, DDR3 SO-DIMM memory modules can be installed which are not buffered, without ECC support, (204 pins, 1.5 V) with a capacity of 1 GB, 2 GB, 4 GB or 8 GB The interface is implemented in accordance with the technical description for the 1890 BM108 microprocessor and JEDEC Standard No. 79-3-1, No. 79-3-2, No. 79-ST, No. 79-3D (https://www.jedec.org/standards-documents/docs/jesd-79-3d).

Using a patented card, up to two PCI Express lanes can be implemented, as shown in the figure of FIG. 4, FIG. 5 and the table of FIG. 6. The PCI Express controller of the 1890 BM108 microprocessor is a programmable interface of the local (internal) AXI bus and an external PCI Express bus. PCI Express expansion cards can be installed on the board with the number of lines × 4 (degradation to × 1 is possible), the nominal line speed is at least 2.5 Gbit / s, and the Root complex / End point operating modes. Clocking is implemented using the 871S1022EKLF clock synthesizer (IDT, Integrated Device Technology Inc). The implementation of the interface is carried out according to the technical descriptions for the 1890 BM108 microprocessor, synthesizer and PCI ExpressBase Specification, Revision 2.0 (https://members.pcisig.com/wg/PCI-SIG/document/download/8246).

Using a patented board, up to two channels of the USB 2.0 and USB 1.1 interface based on the USB controller of the 1890 BM108 microprocessor can be implemented and up to two USB 2.0 and USB 1.1 channels based on two channels of the ULPI microprocessor of 1890 BM108. The total number of ports on the board can be increased through the use of USB hubs. Up to eight USB 2.0 channels can be implemented on the board based on two ULPI channels of the 1890 BM108 microprocessor, according to the figure of FIG. 7 and the table of FIG. 8. The physical layer of USB 2.0 channels is based on a ULPI FUSB2805MLX (ON Semiconductor) transceiver. The USB 2.0 ports on the board are based on the USB2514B-I / M2-ND USB hub (Microchip Technology). Nominal USB 2.0 port speeds are 480 Mbps (high-speed), 12 Mbps (full-speed), 1.5 Mbps (low-speed). The implementation of the interface is performed according to the technical descriptions for the 1890 BM108 microprocessor, ULPI transceiver, USB hub and Universal Serial Bus Specification Revision 2.0 specifications (http://sdphca.ucsd.edu/Lab_Equip_Manuals/usb_20.pdf).

Using the patented board, up to four I ² C channels can be implemented based on the I ² C controller of the 1890 BM108 microprocessor and the I ² C PCA9545APW multiplexer (Texas Instruments), according to the figure in FIG. 9 and the table of FIG. 10. The interface is implemented in accordance with the technical descriptions for the 1890 BM108 microprocessor, I ² C-multiplexer and UM10204 I2C-bus specification and user manual Rev. 6 (https://www.nxp.com/docs/en/user-guide/UM10204.pdf).

Using the patented board, up to two Ethernet 10/100/1000 channels can be implemented on the basis of two Gigabit Ethernet controllers of the 1890 BM108 microprocessor, according to the figure of FIG. 11 and the table of FIG. 12. AXI is used as the system bus. The RGMII interface is used to communicate with Ethernet transceivers. The physical layer of Ethernet 10/100/1000 channels is based on Ethernet 10/100/1000 RTL8211E-VB-CG Ethernet transceivers (Realtek Semiconductor). The implementation of the interface is performed according to the technical descriptions for the 1890 BM108 microprocessor, Ethernet transceiver 10/100/1000 and the IEEE 802.3 Specification (https://standards.ieee.org/standard/802_3-2015.html).

Using a patented board, up to two SATA interface channels can be implemented on the basis of two SATA 3.0 controllers of the 1890 BM108 microprocessor with a nominal speed of up to 6 Gbit / s, according to the figure of FIG. 13 and the table of FIG. 14. The SATA controller is a host controller for the ATA serial disk interface. The software model is Native ATA with extended SATA registers. The system bus uses the AXI interface. Two channels of the SATA interface are connected to external connectors 47155-4001 (Molex) or similar. A SATA15PDP-HH (AUK CONTRACTORS) connector is installed on the board to connect power to SATA devices supporting PDC (Power Disable Control) and DSS (Disable Staggered Spinup) functions. The implementation of the interface is performed according to the technical description for the 1890 BM108 microprocessor and the Serial ATA Specification Rev. 3.1 (https://sata-io.org/developers/purchase-specification).

Using a patented board, one channel of Open LDI (LVDS display interface) with a resolution of up to 2048x1536 based on the LVDS video controller of microprocessor 1890 BM108 can be implemented, according to the figure of FIG. 15 and the table of FIG. 16. The channel of the Open LDI interface is connected to the connector 107K40-000001-G2 (Starconn). The implementation of the interface is performed according to the technical description for the 1890 BM108 microprocessor and the ANSI / TIA / EIA-644 standard (https://www.ti.com/lit/an/slla038b/slla038b.pdf).

Using a patented board, it is possible to connect a NAND EEPROM TH58NVG5S0FTA20 memory chip (Toshiba Memory) based on the Device Bus local bus controller and connect a S25FL127SABMFI101 Flash memory chip (Cypress Semiconductor) via the SPI interface based on the microprocessor SPI controller, according to the figure of FIG. 17 and the table of FIG. 18. The Device Bus controller of the 1890 BM108 microprocessor consists of three units: a software-controlled NAND flash controller that allows simple single memory operations, a NFI ONFI controller with direct memory access and an asynchronous and synchronous static memory controller SRAM, SB-SRAM and flash memory NOR. The 1890 BM108 microprocessor SPI controller provides access to the serial SPI (Serial Peripheral Bus) interface in master mode. A DMA controller is implemented, which allows for batch transfers from / to memory (data stream is formed in memory). A memory-mapped read channel from the SPI slave with hardware implementation of the SPI protocol is available. The implementation of the interface is performed according to the technical descriptions for the 1890 BM108 microprocessor and memory chips.

Using a patented card, up to four channels of the UART interface and up to two channels of the Fast UART interface can be implemented, according to the figure of FIG. 19 and the table of FIG. 20. The channel of the UART interface is implemented on the basis of the RS-232 standard transceiver with the UART interface MAX3245EEAI (MAXIM integrated). The Fast UART interface channel is routed to an external connector.

Using a patented board, up to two CAN 2.0 interface channels can be implemented (GOST R ISO 11898-1), according to the figure of FIG. 21 and the table of FIG. 22, implemented on the basis of the built-in communication controllers of the microprocessor 1890 BM108, supporting the CAN 2.0A / B protocol, described in the technical specification of BOSCH, and the OCP protocol.

Using a patented board, connection to up to two redundant multiplexed data exchange channels (MKIO) can be realized, implemented on the built-in MKIO controller of microprocessor 1890 BM108, according to the figure of FIG. 23 and the table of FIG. 24. The built-in controller MKIO microprocessor 1890 BM108 can perform the functions of a controller, terminal device or monitor MKIO. When working in any mode, the controller performs the hardware protocol of exchange on the multiplex channel without the participation of the central processor.

Using a patented board, the JTAG interface (IEEE Std. 1149.1, http://grouper.ieee.org/groups/1149/1/) can be implemented, according to the drawing of FIG. 25 and the table of FIG. 26. The JTAG interface provides the processor with the ability to check memory blocks without starting the microcircuit in the module, and to verify the microprocessor core on five signal lines. The JTAG interface allows you to manage all the signals at the edge of the chip, thereby helping to facilitate debugging of work in the module. The interface supports EJTAG debugging mode.

Claims (13)

A circuit board for building digital systems, including a microprocessor that provides the operation of external interfaces, characterized in that as a microprocessor it includes an 1890 BM108 microprocessor, which has inputs and outputs that enable the following external interfaces to function: one channel of random access memory; two PCI Express lanes; two channels of the USB 2.0 interface; two channels of the ULPI interface; four channels of the I ² C interface; two channels of the Gigabit Ethernet interface; two channels of the SATA 3.0 interface; one channel of the LVDS interface with a resolution of up to 2048 × 1536; four channels of the UART interface with a speed of up to 115200 baud; two channels of Fast UART interface with a speed of up to 12.5 Mbps; two channels of CAN 2.0 interface; 32 GPIO input-output lines (general-purpose input / output); two multiplexed channels of information exchange (MKIO) with redundancy; JTAG in-circuit debugging interface, with support for EJTAG debugging mode; four channels of the SPI interface; Local Device Bus.

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