CN107942899A - A kind of multi-channel Grating signal processing circuit based on CPLD - Google Patents
A kind of multi-channel Grating signal processing circuit based on CPLD Download PDFInfo
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- CN107942899A CN107942899A CN201711086992.4A CN201711086992A CN107942899A CN 107942899 A CN107942899 A CN 107942899A CN 201711086992 A CN201711086992 A CN 201711086992A CN 107942899 A CN107942899 A CN 107942899A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor
Abstract
The invention belongs to electronic measuring technology field, more particularly to a kind of multi-channel Grating signal processing circuit based on CPLD.Phase module is distinguished in the input interface connection subdivision of the output signal of grating sensor output two-way difference pi/2 of the present invention；Subdivision distinguishes that phase module connects reversible counting module, and reversible counting module 3 connects triple gate module；The input line of address decoding module be the grating signal process circuit input line address wire A0, A1, chip select line CS, read data line RD；The output line of address decoding module is G1, G2, G3 inside circuit, and for controlling 3 groups of tri-state gate circuit outputs, output module is connected with CPU.The present invention can effectively improve integrated level, and make measuring system working stability, reliable.Have the advantages that measure data precision is high, measurement range is big, the output of digit pulse amount, can be widely used for numerically controlled processing equipment, lithographic equipment and other need to do displacement the industrial automatic control occasion detected in high precision.
Description
Technical field
The invention belongs to electronic measuring technology field, more particularly to a kind of multi-channel Grating signal processing electricity based on CPLD
Road, particularly directed to the process circuit of the moire frange signal of grating displacement sensor output, is suitable for one or more gratings
With pretreatment of one piece of special chip to grating signal during displacement sensor access computer system.
Background technology
The development of mechanical processing and measurement technology, the measurement to length and displacement does not require nothing more than raising precision, and requires
Objectively length and displacement measurement can be exported with digital signal form rapidly, to carry out data processing and program
Control.Grating sensor signal process circuit mainly completes the functions such as subdivision, sensing, counting, interface.At present, grating is handled to pass
The hardware circuit of sensor output signal can use application-specific integrated circuit, can also use programmable logic device (FPGA/CPLD)
Realize.At present, using dedicated electronic fine-grained, sensing and the discrete element group such as reversible counting chip into circuit, its autgmentability
Difference, stability are poor.Using the grating displacement sensor signal processing circuit of CPLD device developments, system reliability is improved, is pressed
Contracted circuit structure, enhances programing function, is conducive to the miniaturization of product.Complete electrically subdivision, sensing, counting, interface etc.
Function has the circuit of diversified forms, and the present invention selects a kind of circuit structure of suitable hardware programming, and utilizes hardware program language
It is solidificated in programmable logic device（CPLD）In.In addition, the circuit has, measure data precision is high, measurement range is big, number
Word (pulse) amount output the advantages of, can be widely used for numerically controlled processing equipment, lithographic equipment and it is other need to do displacement it is high-precision
Spend the industrial automatic control occasion of detection.
The content of the invention
Outside above-mentioned the deficiencies in the prior art, the present invention provides a kind of multi-channel Grating signal based on CPLD
Process circuit, its purpose is to reach raising integrated level, and makes measuring system working stability, reliable.
In order to realize foregoing invention purpose, the present invention is achieved by the following technical solutions：
A kind of multi-channel Grating signal processing circuit based on CPLD, the output signal of grating sensor output two-way difference pi/2
Phase module is distinguished in input interface connection subdivision；Subdivision distinguishes that phase module connects reversible counting module, and reversible counting module 3 connects triple gate
Module；The input line of address decoding module is input line address wire A0, A1 of the grating signal process circuit, and chip select line CS, reads
Data cable RD；The output line of address decoding module is G1, G2, G3 inside circuit, for controlling 3 groups of tri-state gate circuit outputs,
Output module is connected with CPU.
The triple gate module includes tri-state gate circuit interface A1, tri-state gate circuit interface A2 and tri-state gate circuit interface
A3。
The output terminal Q0-Q7 connection tri-state gate circuit interface A1 of the reversible counting module, the output of reversible counting module 3
Hold Q8-Q15 connection tri-state gate circuit interface A2, the output terminal Q16-Q23 connection tri-state gate circuit interface A3 of counting module 3, root
The quantity of connection triple gate is determined according to grating sensor measurement length.
The grating sensor, when output multi-channel differs the input interface of output signal of pi/2, with one piece of special chip pair
Multi-channel Grating Signal Pretreatment, by taking two grating displacement sensors as an example：Including first via grating input interface, the second road grating
Input interface and address decoding module, in a core on chip designs two-way grating signal process circuit, the processing of two-way grating signal
Circuit shares an address decoding module, selects the different triple gate of two-way to export stop position by cpu address line bus
Information；And so on, one piece of special chip can design multi-channel Grating signal processing circuit.
The grating sensor, export for single channel grating signal process circuit when, selector EPM7064；When for two-way
During grating signal process circuit, selector EPM7128；The grating sensor, its moire frange signal exported, using can
Programmed logic device CPLD is developed distinguishes light that phase module, 24 reversible counting modules and bus interface module form by subdivision
Gate signal Processing Interface chip；The interface chip input interface can access multiple grating displacement sensor and multiple signals processing；
Output interface uses three bus designs, can be interconnected with various microcontrollers, ARM, DSP and CPU.
The subdivision distinguishes that phase module employs state analysis method and is finely divided and sensing, generation meter during AB two paths of signals state changes
Rapid pulse rushes, and determines that it is to add counting pulse or subtract counting arteries and veins to be currently generated pulse according to current AB states and previous AB states
Punching.
The state analysis method：The order of state change when differing different, when the signal A and signal B of 90 ° of phase difference are in a week
In phase, the level combinations state of two signals has 4 groups；When 90 ° of advanced B phases of A phases, the level state of two phase signals of A, B is opposite
Change turns to 00 → 10 → 11 → 01, both S1 → S2 → S3 → S4；When A phases fall behind 90 ° of B phases, the level of two phase signals of A, B
Opposite become of state turns to 00 → 01 → 11 → 10, both S4 → S3 → S2 → S1；During 90 ° of phase difference, occur without state 00 → 11,
State Transferring between 11 → 00,10 → 01,01 → 10；When state 00 → 10 → 11 → 01 is changed, one-shot change, P often occurs
There is corresponding pulses output, in a cycle, P there are 4 pulses outputs, and direction D is 1；When state 00 → 01 → 11 → 10 is changed, often
Generation one-shot change, P have corresponding pulses output, and in a cycle, P has 4 pulses outputs, and direction D is 0；This just constitutes four
Subdivision and sensing；According to State Transferring, the level change of output P, D.
The reversible counting module is forward-backward counter module 24, Q0-Q23, parallel three bytes ternary output；It is strobed
Byte is exported by tri-state interface module；Exterior three bus interface have A0, A1 address wire, and three byte of counter is corresponded to after decoding；RD
Read and write line；CS chip select lines；D0-D7 data cables；Internal signal wire, which has, counts pulse P, add-subtract control D；G1, G2, G3 are three words
Save Q0-Q7, Q8-Q15, Q16-Q23 select lines；The VHDL language of 24 forward-backward counter modules is described as follows：P counts pulse；D
Add-subtract control；24 parallel-by-bit of Q counters exports.
The interface module includes address decoding module 4 and three 8 one-way bus buffers, 8 one-way bus
Buffer：Q inputs for 8 parallel-by-bits；G is enabled；D is 8 parallel-by-bit ternary outputs.
In described address decoding module, A0, A1 are address；RD is reading；CS selects for piece；G1, G2, G3 export for decoding, make
For the gating signal of triple gate；When two grating displacement sensors of system access, piece address wire A2 of interface chip multiple access,
A2 accesses decoder, as A2=0, selects the first grating sensor, G1, G2, G3 are effective；As A2=0, the second grating is selected to pass
Sensor, G4, G5, G6 are effective；When more grating displacement sensors of system access, the address decoding module of interface chip continues to increase
Add address wire.
Advantages of the present invention and beneficial effect are：
The present invention can effectively improve integrated level, and make measuring system working stability, reliable.The present invention relates to special chip to set
Meter, the structure of circuit.The circuit can make grating displacement sensor signal processing integrated level obtain height, can also make work efficiency
It is greatly improved.The present invention selects a kind of circuit structure of suitable hardware programming, and is consolidated using hardware program language
Change in programmable logic device（CPLD）In.It is big, the output of digit pulse amount excellent with measure data precision height, measurement range
Point, can be widely used for numerically controlled processing equipment, lithographic equipment and other needs to do displacement the industrial automation detected in high precision
Control occasion.
Brief description of the drawings
Circuit structure block diagram when Fig. 1 is single grating displacement sensor access；
The structure diagram of circuit when Fig. 2 is more grating displacement sensor accesses；
Fig. 3 is interface mode structure diagram of the present invention；
Fig. 4 is a-signal phase 90 degree of schematic diagrames of advanced B signal；
Fig. 5 is that a-signal phase falls behind 90 degree of schematic diagrames of B signal；
Fig. 6 is the change that P, D are exported according to State Transferring；
Multi-channel Grating signal processing circuit shown in Fig. 7 and CPU connection figures.
In figure：Input interface 1, segments and distinguishes phase module 2, reversible counting module 3, address decoding module 4, triple gate module 5,
Output module 6, first via grating input interface 7, the second road grating input interface 8.
Embodiment
The present invention is a kind of multi-channel Grating signal processing circuit based on CPLD, that is, one kind is based on programmable logic
The CPLD of device is adapted to the process circuit of multi-channel Grating signal.Including input interface 1, phase module 2, reversible counting module are distinguished in subdivision
3, address decoding module 4, triple gate module 5 and output module 6.Realize said units functions of modules description circuit arrangement compared with
More, the circuit arrangement that the present invention uses is shown in the circuit design of VHDL descriptions.By the Integrated Development Environment of computer to preliminary
Function description integrated, emulated, being tested, downloads after i.e. completion chip design.
The present invention is one piece of integrated circuit that is complete, having processing grating signal, as shown in Figure 1, Fig. 1 is single grating
Circuit structure block diagram when displacement sensor accesses, the design structure of the circuit are as follows：
The input interface 1 of the output signal of grating sensor output two-way difference pi/2 connects subdivision and distinguishes phase module 2；Phase is distinguished in subdivision
Module 2 connects reversible counting module 3.Reversible counting module 3 connects triple gate module 5, and triple gate module 5 includes tri-state gate circuit
Interface A1, tri-state gate circuit interface A2 and tri-state gate circuit interface A3.The output terminal Q0-Q7 connection tri-states of reversible counting module 3
Gate circuit interface A1, the output terminal Q8-Q15 connection tri-state gate circuit interface A2 of reversible counting module 3, reversible counting module 3
Output terminal Q16-Q23 connection tri-state gate circuit interface A3, measure length according to grating sensor and determine to connect the quantity of triple gate.
The special circuit has three bus interface of standard computer, there is address wire, control line and data cable, and phase is selected with address decoder
Three output end interfaces of the tri-state gate circuit answered can be directly connected with CPU.
The input line of address decoding module 4 be the grating signal process circuit input line address wire A0, A1, chip select line
CS, read data line RD；The output line of address decoding module 4 is G1, G2, G3 inside circuit, for controlling 3 groups of tri-state gate circuits
Output, output module 6 are connected with CPU.
Include the address wire and control line for the output that A0, A1, CS, RD are CPU with cpu i/f, A0-A7 is 8 of CPU
Data cable.As shown in fig. 7, multi-channel Grating signal processing circuit and CPU connection figures.
1,24 three groups, 8 one group of triple gates point as shown in the figure；24 digit counters export Q0-Q23, also divide 3 groups, as
Input is respectively connected to 3 groups of triple gates, and Q0-Q7 accesses first group, and Q8-Q15 accesses second group, and Q16-Q23 accesses the 3rd group.Often
Group triple gate output meets the data output D0-D7 of grating signal process circuit respectively.G1, G2, G3 export for decoder, are also three
The control of group triple gate, triple gate output is high resistant when not selected（Without output）, D0-D7 without（Without output）.
A0, A1, CS, RD line of CPU reads the data of D0-D7 by decoder：
CS is effective（Logical zero）, grating signal process circuit is selected；
CS is effective（Logic 1）, grating signal process circuit output high resistant（Without output）；
A0、A1（00）, after choosing G1, RD effective, D0-D7 outputs are Q0-Q7；
A0、A1（01）, after choosing G2, RD effective, D0-D7 outputs are Q8-Q15；
A0、A1（10）, after choosing G3, RD effective, D0-D7 outputs are Q16-Q23.
CPU reads in three groups of 8 data respectively, is 24 outputs of counter.
As shown in Fig. 2, when Fig. 2 is the access of more grating displacement sensors circuit structure diagram.When measurement length uses
During more grating displacement sensor access computer systems, with one piece of special chip to multi-channel Grating Signal Pretreatment, with two
Exemplified by grating displacement sensor.Including first via grating input interface 7, the second road grating input interface 8 and address decoding module
4.In a core on chip designs two-way grating signal process circuit, two-way grating signal process circuit shares an address decoding mould
Block, selects the different triple gate of two-way to export raster position information by cpu address line bus.And so on, one piece is special
Chip can design multi-channel Grating signal processing circuit.
Circuit design method of the present invention is the Integrated Development Environment by computer, and circuit design uses hardware description language
VHDL or verilog carries out function description to each unit module in special chip, then connects corresponding module, passes through collection
Development environment synthesis, which is downloaded, completes chip design.The function description of unit module can select different signal processing electricity
Road, the method that the present invention uses further illustrate in the description.
The selection of programmable logic device：Single channel grating signal process circuit selector EPM7064, two-way grating signal
Process circuit selector EPM7064.
The operation principle of the present invention is as follows：
The present invention for grating displacement sensor output moire frange signal, using programmable logic device (CPLD) develop by
The grating signal processing Special Interface Chip that phase module, 24 reversible counting modules and bus interface module are formed is distinguished in subdivision.
The interface chip input interface can be designed as accessing multiple grating displacement sensor and multiple signals processing.Output interface uses
Three bus designs, can interconnect with various microcontrollers, ARM, DSP and CPU.Exemplified by accessing two grating displacement sensors, to light
Gate signal interface chip operation principle, design method are explained.
Each module is introduced separately below：
The subdivision distinguishes that the function of phase module 2 is：
1. segmenting, the purpose of subdivision is to improve the spatial resolution of grating displacement measuring system, and grating sensor output is two-way
The square-wave signal of 90 ° of difference.There are four lower edges within a square-wave signal cycle of output, using four edges, then lead to
Cross logic circuit and generate four burst pulses for counting, equivalent to the resolution ratio for improving measuring system.
2. sensing（Phase）It is the moving direction for distinguishing grating sensor.Grating sensor output differs 90 ° of side for two-way
Ripple signal, when direction is different, two-way difference is different, i.e. 90 ° of the advanced B signal of a-signal or a-signal hysteresis 90 ° of utilizations of B signal is patrolled
Collect the current AB signal conditions of circuit judges and a subsequent state, so that it may judge the direction of grating sensor relative displacement.Can
Determine that counter is addend or subtrahend.
State analysis method is exactly to determine current forward-backward counter according to current input AB states and upper input AB states
It is plus counts or subtract counting, count value is displacement.
Application state analytic approach：The order of state change when differing different, when the signal A and signal B of 90 ° of phase difference are one
In a cycle, the level combinations state of two signals has 4 groups.When 90 ° of advanced B phases of A phases, as shown in figure 4, Fig. 4 is a-signal phase
Position 90 degree of schematic diagrames of advanced B signal.A, opposite become of the level state of two phase signals of B turns to 00 → 10 → 11 → 01, both S1 → S2
→S3→S4；When A phases fall behind 90 ° of B phases, as shown in figure 5, Fig. 5, which is a-signal phase, falls behind 90 degree of schematic diagrames of B signal.A, B two
Opposite become of the level state of phase signals turns to 00 → 01 → 11 → 10, both S4 → S3 → S2 → S1.During 90 ° of phase difference, occur without
State Transferring between state 00 → 11,11 → 00,10 → 01,01 → 10.When state 00 → 10 → 11 → 01 is changed, often occur
One-shot change, P have corresponding pulses output, and in a cycle, P has 4 pulses outputs, and direction D is 1；State 00 → 01 → 11 →
During 10 conversion, often occur one-shot change, P has corresponding pulses output, and in a cycle, P there are 4 pulses outputs, and direction D is 0.This
Just constitute four subdivisions and sensing.According to State Transferring, the level change of output P, D, as shown in fig. 6, Fig. 6 is turned according to state
Change the variation diagram of output P, D.
Reversible counting module 3：The forward-backward counter module of Special Interface Chip 24, Q0-Q23, parallel three bytes tri-state
Output.Byte is strobed to be exported by tri-state interface module.As shown in Fig. 2, exterior three bus interface have A0, A1 address wire, decode
Three byte of counter is corresponded to afterwards；RD reads and writes line；CS chip select lines；D0-D7 data cables.Internal signal wire, which has, counts pulse P, plus-minus control
D processed；G1, G2, G3 are three byte Q0-Q7, Q8-Q15, Q16-Q23 select lines.The VHDL language of 24 forward-backward counter modules
It is described as follows：P counts pulse；D add-subtract controls；24 parallel-by-bit of Q counters exports.
Interface module includes address decoding module 4 and three 8 one-way bus buffers, and 8 one-way bus delay
Rush device：Q inputs for 8 parallel-by-bits；G is enabled；D is 8 parallel-by-bit ternary outputs.In described address decoding module 4, A0, A1 are ground
Location；RD is reading；CS selects for piece；G1, G2, G3 export for decoding, the gating signal as triple gate.
When two grating displacement sensors of system access, as shown in figure 3, Fig. 3 is interface mode structural representation of the present invention
Figure.Piece address wire A2 of interface chip multiple access.A2 accesses decoder, as A2=0, selects the first grating sensor, G1, G2,
G3 is effective；As A2=0, the second grating sensor is selected, G4, G5, G6 are effective.
When more grating displacement sensors of system access, the address decoding module of interface chip continues to increase address wire.
Claims (10)
1. a kind of multi-channel Grating signal processing circuit based on CPLD, it is characterized in that：Grating sensor output two-way difference pi/2
Phase module is distinguished in the input interface connection subdivision of output signal；Subdivision distinguishes that phase module connects reversible counting module, reversible counting module 3
Connect triple gate module；The input line of address decoding module be the grating signal process circuit input line address wire A0, A1, piece
Route selection CS, read data line RD；The output line of address decoding module is G1, G2, G3 inside circuit, for controlling 3 groups of triple gates
Circuit output, output module are connected with CPU.
2. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：The tri-state
Door module includes tri-state gate circuit interface A1, tri-state gate circuit interface A2 and tri-state gate circuit interface A3.
3. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：It is described reversible
The output terminal Q0-Q7 connection tri-state gate circuit interface A1 of counting module, the output terminal Q8-Q15 connection tri-states of reversible counting module 3
Gate circuit interface A2, the output terminal Q16-Q23 connection tri-state gate circuit interface A3 of counting module 3, measures according to grating sensor
Length determines the quantity of connection triple gate.
4. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：The grating
Sensor, when output multi-channel differs the input interface of output signal of pi/2, locates multi-channel Grating signal with one piece of special chip in advance
Reason, by taking two grating displacement sensors as an example：Including first via grating input interface, the second road grating input interface and address are translated
Code module, in a core on chip designs two-way grating signal process circuit, two-way grating signal process circuit shares an address
Decoding module, selects the different triple gate of two-way to export raster position information by cpu address line bus；And so on, one
Block special chip can design multi-channel Grating signal processing circuit.
5. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：The grating
Sensor, export for single channel grating signal process circuit when, selector EPM7064；When for two-way grating signal process circuit
When, selector EPM7128；The grating sensor, its moire frange signal exported, using programmable logic device (CPLD)
Develop and grating signal Processing Interface core that phase module, 24 reversible counting modules and bus interface module form is distinguished by subdivision
Piece；The interface chip input interface can access multiple grating displacement sensor and multiple signals processing；Output interface is total using three
Line designs, and can be interconnected with various microcontrollers, ARM, DSP and CPU.
6. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：The subdivision
Distinguish that phase module employs state analysis method and is finely divided and sensing, during AB two paths of signals state changes generation count pulse, according to
Current AB states and previous AB states determine that being currently generated pulse is plus counts pulse or subtract counting pulse.
7. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 6, it is characterized in that：The state
Analytic approach：The order of state change when differing different, when 90 ° of phase difference signal A and signal B in one cycle, two signals
Level combinations state have 4 groups；When 90 ° of advanced B phases of A phases, opposite become of the level state of two phase signals of A, B turns to 00 → 10
→ 11 → 01, both S1 → S2 → S3 → S4；When A phases fall behind 90 ° of B phases, opposite become of the level state of two phase signals of A, B turns to
00 → 01 → 11 → 10, both S4 → S3 → S2 → S1；During 90 ° of phase difference, state 00 → 11,11 → 00,10 → 01,01 is occurred without
State Transferring between → 10；When state 00 → 10 → 11 → 01 is changed, often occurring one-shot change, P has corresponding pulses output, and one
In a cycle, P has 4 pulse outputs, and direction D is 1；When state 00 → 01 → 11 → 10 is changed, one-shot change often occurs, P has
Corresponding pulses export, and in a cycle, P has 4 pulse outputs, and direction D is 0；This just constitutes four subdivisions and sensing；According to shape
State is changed, and exports the level change of P, D.
8. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：It is described reversible
Counting module is forward-backward counter module 24, Q0-Q23, parallel three bytes ternary output；Byte is strobed by tri-state interface mould
Block exports；Exterior three bus interface have A0, A1 address wire, and three byte of counter is corresponded to after decoding；RD reads and writes line；CS chip select lines；
D0-D7 data cables；Internal signal wire, which has, counts pulse P, add-subtract control D；G1, G2, G3 for three byte Q0-Q7, Q8-Q15,
Q16-Q23 select lines；The VHDL language of 24 forward-backward counter modules is described as follows：P counts pulse；D add-subtract controls；Q is counted
24 parallel-by-bit of device exports.
9. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 8, it is characterized in that：The interface
Module includes address decoding module 4 and three 8 one-way bus buffers, 8 one-way bus buffers：Q is 8 parallel-by-bits
Input；G is enabled；D is 8 parallel-by-bit ternary outputs.
10. a kind of multi-channel Grating signal processing circuit based on CPLD according to claim 1, it is characterized in that：Describedly
In the decoding module of location, A0, A1 are address；RD is reading；CS selects for piece；G1, G2, G3 export for decoding, the gating as triple gate
Signal；When two grating displacement sensors of system access, piece address wire A2, A2 access decoder of interface chip multiple access,
As A2=0, the first grating sensor is selected, G1, G2, G3 are effective；As A2=0, the second grating sensor, G4, G5, G6 are selected
Effectively；When more grating displacement sensors of system access, the address decoding module of interface chip continues to increase address wire.
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| CN109634212A (en) * | 2018-12-13 | 2019-04-16 | 中国航空工业集团公司北京长城计量测试技术研究所 | A kind of grating digital display device with Remote triggering function |
| CN114253206A (en) * | 2021-11-18 | 2022-03-29 | 加弘科技咨询(上海)有限公司 | Transparent transmission structure of programmable logic device and programmable logic device |
| CN114253206B (en) * | 2021-11-18 | 2024-02-23 | 加弘科技咨询(上海)有限公司 | Transparent transmission structure of programmable logic device and programmable logic device |
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Application publication date: 20180420 |