CN114253206A - Transparent transmission structure of programmable logic device and programmable logic device - Google Patents
Transparent transmission structure of programmable logic device and programmable logic device Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
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- G05B2219/15—Plc structure of the system
- G05B2219/15034—Serial transmission using one line for data and one line for clock
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention provides a transparent transmission structure of a programmable logic device and the programmable logic device, wherein the transparent transmission structure comprises: the device comprises an upstream tri-state gate circuit module, a downstream tri-state gate circuit module, a bus direction analysis module and a multi-input logic and operation module; the bus direction analysis module realizes the switching of the signal transmission directions of the upstream and downstream three-state gates; the upstream tri-state gate circuit module switches logic signals according to the direction of the tri-state gate to control enable control bits so as to realize signal input of an upstream signal bus and signal output of a multi-path input logic and operation module; the downstream tri-state gate circuit module switches the logic signal control enabling control bit according to the direction of the downstream tri-state gate so as to realize the transmission of the input signal of the upstream signal bus to downstream slave equipment and the transmission of the downstream input signal to the multi-input logic and operation module. The transparent transmission structure can realize the purpose of expanding the communication channel of the programmable logic device.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to the technical field of programmable logic devices.
Background
Programmable Logic Devices (PLDs) have the advantages of low cost, high integration, and easy work expansion, and PLDs have become the preferred solution for more and more complex systems.
Generally, a link architecture of a programmable logic device is implemented by a certain channel selection expansion device (for example, a channel selection expander in PCA95 series), but because the circuit board area of the programmable logic device is limited and the layout is tense, it is difficult to implement effective expansion of a channel of the programmable logic device when the channel selection expansion device cannot be laid.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a transparent transmission structure of a programmable logic device and a programmable logic device, which are used to solve the technical problems that the programmable logic device in the prior art is not sufficiently introduced and an output channel is difficult to expand.
To achieve the above and other related objects, an embodiment of the present invention provides a transparent transmission structure of a programmable logic device, including: the device comprises an upstream tri-state gate circuit module, a downstream tri-state gate circuit module, a bus direction analysis module and a multi-input logic and operation module; the bus direction analysis module is connected with an upstream signal bus and the upstream tri-state gate circuit module and is connected to an enabling control port of the downstream tri-state gate circuit module through an inverter, and the bus direction analysis module is used for analyzing the transmission direction of a bus signal on the upstream signal bus and generating a tri-state gate direction switching logic signal based on the transmission direction of the bus signal so as to perform enabling control on the upstream tri-state gate circuit module and the downstream tri-state gate circuit module and realize switching of the transmission directions of the upstream tri-state gate signal and the downstream tri-state gate signal; the multi-path input logic and operation module is respectively connected with the upstream tri-state gate circuit module and the downstream tri-state gate circuit module, and inputs a downstream input signal of the downstream tri-state gate circuit module into the upstream tri-state gate circuit module after performing logic and operation on the downstream input signal of the downstream tri-state gate circuit module; the upstream tri-state gate circuit module is connected with the upstream signal bus, the bus direction analysis module and the multi-input logic and operation module, and switches logic signal control enabling control bits according to the tri-state gate direction so as to realize signal input of the upstream signal bus and signal output of the multi-input logic and operation module; the downstream tri-state gate circuit module is connected with downstream slave equipment, and the logic signal is switched according to the direction of the downstream tri-state gate to control the enabling control bit so as to realize the transmission of the input signal of the upstream signal bus to the downstream slave equipment and the transmission of the downstream input signal to the multi-input logic and operation module.
In one embodiment of the present application, the signal buses include an upstream clock signal bus and an upstream data signal bus.
In an embodiment of the present application, the upstream tri-state gate circuit module includes: a first upstream tri-state gate circuit connected to the upstream clock signal bus; a second upstream tri-state gate circuit connected to the upstream data signal bus; the downstream tri-state gate module comprises: the first downstream tri-state gate circuit comprises a plurality of tri-state gates, is connected with a plurality of downstream slave devices, and respectively controls the clock signal to be transmitted to the corresponding downstream slave devices through the tri-state gates; and the second downstream tri-state gate circuit comprises a plurality of tri-state gates, is connected with a plurality of downstream slave devices, and respectively controls the data signal to be transmitted to the corresponding downstream slave devices through the tri-state gates.
In an embodiment of the present application, the bus direction analyzing module includes: an upstream clock signal bus direction analyzing module, connected to the upstream clock signal bus, the upstream data signal bus, and the first downstream tri-state gate circuit, respectively, for analyzing a transmission direction of a signal on the upstream clock signal bus, and generating a first upstream tri-state gate direction switching logic signal for controlling an enable control bit of the first upstream tri-state gate circuit and a first downstream tri-state gate direction switching logic signal for controlling an enable control bit of the first downstream tri-state gate circuit based on the transmission direction of the signal on the upstream clock signal bus; and the upstream data signal bus direction analyzing module is respectively connected with the upstream clock signal bus, the upstream data signal bus and the second downstream tri-state gate circuit, and is used for analyzing the transmission direction of the signal on the upstream data signal bus, and generating a second upstream tri-state gate direction switching logic signal for controlling the enable control bit of the second upstream tri-state gate circuit and a second downstream tri-state gate direction switching logic signal for controlling the enable control bit of the second downstream tri-state gate circuit based on the transmission direction of the signal on the upstream data signal bus.
In an embodiment of the present application, the logic and operation module with multiple inputs includes: a first multi-input logic and operation module, which is respectively connected to the first upstream tri-state gate circuit and the first downstream tri-state gate circuit, and outputs a first downstream input signal of the first downstream tri-state gate circuit to the first upstream tri-state gate circuit after performing logic and operation; and the second multi-input logic and operation module is respectively connected with the second upstream tri-state gate circuit and the second downstream tri-state gate circuit, and outputs a second downstream input signal of the second downstream tri-state gate circuit to the second upstream tri-state gate circuit after performing logic and operation on the second downstream input signal.
In an embodiment of the present application, the first upstream tri-state gate circuit controls an enable control bit according to the first upstream tri-state gate direction switching logic signal, so as to implement signal input of an upstream clock signal bus and signal output of the first multi-input logical and operation module; and the second upstream tri-state gate circuit switches logic signals according to the direction of the second upstream tri-state gate to control an enable control bit so as to realize signal input of an upstream data signal bus and signal output of the second multi-path input logic AND operation module.
In an embodiment of the present application, the first downstream tri-state gate circuit switches the logic signal control enable control bit according to the direction of the first downstream tri-state gate, so as to implement transmission of the input signal of the upstream clock signal bus to the first downstream slave device, and transmission of the first downstream input signal to the first multi-input logical and operation module; and the second downstream tri-state gate circuit switches logic signals according to the direction of the second downstream tri-state gate to control an enable control bit so as to realize the transmission of the input signals of the upstream data signal bus to the second downstream slave device and the transmission of the second downstream input signals to the second multi-input logic AND operation module.
In an embodiment of the present application, the method further includes: and the first inverter is connected between the first downstream tri-state gate circuit and the upstream clock signal bus direction analysis module, and the transmission directions of the clock signals of the first upstream tri-state gate circuit and the first downstream tri-state gate circuit are mutually the logical inverse.
In an embodiment of the present application, the second inverter is connected between the second downstream tri-state gate circuit and the upstream data signal bus direction analyzing module, and transmission directions of clock signals of the second upstream tri-state gate circuit and the second downstream tri-state gate circuit are logical inverses of each other.
The embodiment of the invention also provides a programmable logic device which comprises the transparent transmission structure of the programmable logic device.
As described above, the transparent transmission structure of the programmable logic device and the programmable logic device of the present invention have the following advantages:
the transparent transmission structure can realize the purpose of expanding the communication channel of the programmable logic device, not only can improve the resource utilization rate of the programmable logic device, but also can carry out targeted expansion of the transparent transmission structure according to the number of plug-in downstream equipment, thereby saving the cost of products and the layout space of circuit boards.
Drawings
Fig. 1 is a schematic diagram illustrating an overall schematic structure of a transparent transmission structure of a programmable logic device according to the present invention.
Fig. 2 is a schematic diagram showing a specific structure of a transparent transmission structure of a programmable logic device according to the present invention.
Description of the element reference numerals
Transparent transmission structure of 100 programmable logic device
110 upstream tri-state gate module
111 first upstream tri-state gate
112 second upstream tri-state gate
120 bus direction analysis module
121 upstream clock signal bus direction analysis module
122 upstream data signal bus direction analysis module
130 multi-input logic and operation module
131 first multi-channel input logic and operation module
132 second multiple input logic and operation module
140 downstream tri-state gate module
141 first downstream tri-state gate
142 second downstream tri-state gate
151 first inverter
152 second inverter
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
The purpose of this embodiment is to provide a transparent transmission structure 100 of a programmable logic device and a programmable logic device, which are used to solve the technical problem in the prior art that a control node cannot normally work when mixed insertion occurs in a control cabinet.
The following will explain the principle and implementation of the transparent transmission structure 100 of the programmable logic device and the programmable logic device in this embodiment in detail, so that those skilled in the art can understand the transparent transmission structure 100 of the programmable logic device and the programmable logic device of the present invention without creative labor.
As shown in fig. 1, this embodiment provides a transparent transmission structure 100 of a programmable logic device, where the transparent transmission structure 100 of the programmable logic device includes: an upstream tri-state gate module 110, a downstream tri-state gate module 140, a bus direction resolution module 120, and a multi-input logical and operation module 130.
In the transparent transmission structure 100 of the programmable logic device in this embodiment, an upstream signal bus is directly transmitted to a downstream multi-path signal bus, and the downstream multi-path signal bus is respectively connected to a plurality of downstream slave devices, so that a purpose of expanding a communication channel of the programmable logic device is achieved, a purpose of controlling the plurality of downstream slave devices through the upstream signal bus is achieved, and transparent transmission is achieved.
As shown in fig. 2, in the present embodiment, the upstream tri-state gate circuit module 110 includes: a first upstream tri-state gate 111 and a second upstream tri-state gate 112.
Specifically, in this embodiment, the signal buses include an upstream clock signal bus and an upstream data signal bus, the first upstream tri-state gate circuit 111 is connected to the upstream clock signal bus, and the second upstream tri-state gate circuit 112 is connected to the upstream data signal bus.
In this embodiment, the downstream tri-state gate module 140 includes: a first downstream tri-state gate circuit 141, including a plurality of tri-state gates (e.g. 8 tri-state gates shown in fig. 2), connected to a plurality of downstream slave devices, and configured to control, through each of the tri-state gates, transmission of a clock signal to the corresponding downstream slave device; a second downstream tri-state gate circuit 142, comprising a plurality of tri-state gates (e.g., 8 tri-state gates shown in fig. 2), is connected to a plurality of the downstream slave devices, and controls the transmission of data signals to the corresponding downstream slave devices through each of the tri-state gates.
In this embodiment, the principle of the analysis by the bus direction analysis module 120 is to analyze the transmission directions of the upstream clock signal and the upstream data signal according to the bus protocol format according to the upstream clock signal and the upstream data signal, and the analyzed data transmission direction control signal is used as the enable control bit of the data port tri-state gate.
Specifically, in this embodiment, the bus direction analyzing module 120 is connected to an upstream signal bus and the upstream tri-state gate circuit module 110, and is connected to the enable control port of the downstream tri-state gate circuit module 140 through an inverter, and the bus direction analyzing module 120 is configured to analyze a transmission direction of a bus signal on the upstream signal bus, and generate a tri-state gate direction switching logic signal based on the transmission direction of the bus signal, so as to perform enable control on the upstream tri-state gate circuit module 110 and the downstream tri-state gate circuit module 140, and implement switching of transmission directions of upstream and downstream tri-state gate signals.
Wherein the inverters include a first inverter 151 and a second inverter 152.
The first inverter 151 is connected between the first downstream tri-state gate circuit 141 and the upstream clock signal bus direction analyzing module 121, and the transmission directions of the clock signals of the first upstream tri-state gate circuit 111 and the first downstream tri-state gate circuit 141 are logical inverses of each other; the second inverter 152 is connected between the second downstream tri-state gate circuit 142 and the upstream data signal bus direction analyzing module 122, and the transmission directions of the clock signals of the second upstream tri-state gate circuit 112 and the second downstream tri-state gate circuit 142 are logical inverses of each other.
Specifically, in this embodiment, the bus direction analyzing module 120 includes: an upstream clock signal bus direction analyzing module 121 and an upstream data signal bus direction analyzing module 122.
The upstream clock signal bus direction analyzing module 121 is connected to the upstream clock signal bus, the upstream data signal bus, and the first downstream tri-state gate circuit 141, and configured to analyze a transmission direction of a signal on the upstream clock signal bus, and generate a first upstream tri-state gate direction switching logic signal for controlling an enable control bit of the first upstream tri-state gate circuit 111 and a first downstream tri-state gate direction switching logic signal for controlling an enable control bit of the first downstream tri-state gate circuit 141 based on the transmission direction of the signal on the upstream clock signal bus.
The upstream data signal bus direction analyzing module 122 is respectively connected to the upstream clock signal bus, the upstream data signal bus, and the second downstream tri-state gate circuit 142, and is configured to analyze a transmission direction of a signal on the upstream data signal bus, and generate a second upstream tri-state gate direction switching logic signal for controlling an enable control bit of the second upstream tri-state gate circuit 112 and a second downstream tri-state gate direction switching logic signal for controlling an enable control bit of the second downstream tri-state gate circuit 142 based on the transmission direction of the signal on the upstream data signal bus.
In this embodiment, the multi-input logical and operation module 130 is respectively connected to the upstream tri-state gate circuit module 110 and the downstream tri-state gate circuit module 140, and inputs the downstream input signal of the downstream tri-state gate circuit module 140 to the upstream tri-state gate circuit module 110 after performing logical and operation; the upstream tri-state gate circuit module 110 is connected to the upstream signal bus, the bus direction analyzing module 120 and the multi-input logical and operation module 130, and controls an enable control bit according to the tri-state gate direction switching logic signal, so as to implement signal input of the upstream signal bus and signal output of the multi-input logical and operation module 130; the downstream tri-state gate circuit module 140 is connected to the downstream slave device, and controls the enable control bit according to the direction of the downstream tri-state gate, so as to implement the transmission of the input signal of the upstream signal bus to the downstream slave device, and the transmission of the downstream input signal to the multi-input logical and operation module 130.
Specifically, in the present embodiment, the multi-input logic and operation module 130 includes: a first multi-input logical and operation block 131 and a second multi-input logical and operation block 132.
The first multi-input logical and operation module 131 is respectively connected to the first upstream tri-state gate circuit 111 and the first downstream tri-state gate circuit 141, and outputs a first downstream input signal of the first downstream tri-state gate circuit 141 to the first upstream tri-state gate circuit 111 after performing logical and operation; and a second multi-input logical and operation module 132, which is respectively connected to the second upstream tri-state gate circuit 112 and the second downstream tri-state gate circuit 142, and outputs the second downstream input signal of the second downstream tri-state gate circuit 142 to the second upstream tri-state gate circuit 112 after performing logical and operation.
The operation principle of the transparent transmission structure 100 of the programmable logic device of the embodiment is as follows:
1) the first upstream tri-state gate circuit 111 switches the logic signal control enabling control bit according to the direction of the first upstream tri-state gate, so as to realize the signal input of the upstream clock signal bus and the signal output of the first multi-input logic and operation module 131; the second upstream tri-state gate circuit 112 switches the logic signal control enable control bit according to the direction of the second upstream tri-state gate, so as to realize the signal input of the upstream data signal bus and the signal output of the second multi-input logical and operation module 132.
2) The first downstream tri-state gate circuit 141 switches the logic signal control enabling control bit according to the direction of the first downstream tri-state gate to realize the transmission of the input signal of the upstream clock signal bus to the first downstream slave device, and the transmission of the first downstream input signal to the first multi-input logical and operation module 131; the second downstream tri-state gate circuit 142 switches the logic signal control enabling control bit according to the direction of the second downstream tri-state gate, so as to realize the transmission of the input signal of the upstream data signal bus to the second downstream slave device, and the transmission of the second downstream input signal to the second multi-input logical and operation module 132.
In addition, an embodiment of the present invention further provides a programmable logic device, which includes the transparent transmission structure 100 of the programmable logic device. The transparent transmission structure 100 of the programmable logic device has been described in detail above, and will not be described in detail here.
In summary, the transparent transmission structure in the invention can achieve the purpose of expanding the communication channel of the programmable logic device, and the invention can not only improve the resource utilization rate of the programmable logic device, but also carry out the targeted expansion of the transparent transmission structure according to the number of the plug-in downstream equipment, thereby saving the cost of the product and the layout space of the circuit board. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A transparent transmission structure of a programmable logic device is characterized in that: the method comprises the following steps: the device comprises an upstream tri-state gate circuit module, a downstream tri-state gate circuit module, a bus direction analysis module and a multi-input logic and operation module;
the bus direction analysis module is connected with an upstream signal bus and the upstream tri-state gate circuit module and is connected to an enabling control port of the downstream tri-state gate circuit module through an inverter, and the bus direction analysis module is used for analyzing the transmission direction of a bus signal on the upstream signal bus and generating a tri-state gate direction switching logic signal based on the transmission direction of the bus signal so as to perform enabling control on the upstream tri-state gate circuit module and the downstream tri-state gate circuit module and realize switching of the transmission directions of the upstream tri-state gate signal and the downstream tri-state gate signal;
the multi-path input logic and operation module is respectively connected with the upstream tri-state gate circuit module and the downstream tri-state gate circuit module, and inputs a downstream input signal of the downstream tri-state gate circuit module into the upstream tri-state gate circuit module after performing logic and operation on the downstream input signal of the downstream tri-state gate circuit module;
the upstream tri-state gate circuit module is connected with the upstream signal bus, the bus direction analysis module and the multi-input logic and operation module, and switches logic signal control enabling control bits according to the tri-state gate direction so as to realize signal input of the upstream signal bus and signal output of the multi-input logic and operation module;
the downstream tri-state gate circuit module is connected with downstream slave equipment, and the logic signal is switched according to the direction of the downstream tri-state gate to control the enabling control bit so as to realize the transmission of the input signal of the upstream signal bus to the downstream slave equipment and the transmission of the downstream input signal to the multi-input logic and operation module.
2. The transparent transmission structure of a programmable logic device according to claim 1, characterized in that: the signal buses include an upstream clock signal bus and an upstream data signal bus.
3. The transparent transmission structure of a programmable logic device according to claim 2, characterized in that: the upstream tri-state gate module comprises:
a first upstream tri-state gate circuit connected to the upstream clock signal bus;
a second upstream tri-state gate circuit connected to the upstream data signal bus;
the downstream tri-state gate module comprises:
the first downstream tri-state gate circuit comprises a plurality of tri-state gates, is connected with a plurality of downstream slave devices, and respectively controls the clock signal to be transmitted to the corresponding downstream slave devices through the tri-state gates;
and the second downstream tri-state gate circuit comprises a plurality of tri-state gates, is connected with a plurality of downstream slave devices, and respectively controls the data signal to be transmitted to the corresponding downstream slave devices through the tri-state gates.
4. The transparent transmission structure of a programmable logic device according to claim 3, characterized in that: the bus direction analysis module comprises:
an upstream clock signal bus direction analyzing module, connected to the upstream clock signal bus, the upstream data signal bus, and the first downstream tri-state gate circuit, respectively, for analyzing a transmission direction of a signal on the upstream clock signal bus, and generating a first upstream tri-state gate direction switching logic signal for controlling an enable control bit of the first upstream tri-state gate circuit and a first downstream tri-state gate direction switching logic signal for controlling an enable control bit of the first downstream tri-state gate circuit based on the transmission direction of the signal on the upstream clock signal bus;
and the upstream data signal bus direction analyzing module is respectively connected with the upstream clock signal bus, the upstream data signal bus and the second downstream tri-state gate circuit, and is used for analyzing the transmission direction of the signal on the upstream data signal bus, and generating a second upstream tri-state gate direction switching logic signal for controlling the enable control bit of the second upstream tri-state gate circuit and a second downstream tri-state gate direction switching logic signal for controlling the enable control bit of the second downstream tri-state gate circuit based on the transmission direction of the signal on the upstream data signal bus.
5. The transparent transmission structure of a programmable logic device according to claim 3, characterized in that: the logic and operation module with multiple inputs comprises:
a first multi-input logic and operation module, which is respectively connected to the first upstream tri-state gate circuit and the first downstream tri-state gate circuit, and outputs a first downstream input signal of the first downstream tri-state gate circuit to the first upstream tri-state gate circuit after performing logic and operation;
and the second multi-input logic and operation module is respectively connected with the second upstream tri-state gate circuit and the second downstream tri-state gate circuit, and outputs a second downstream input signal of the second downstream tri-state gate circuit to the second upstream tri-state gate circuit after performing logic and operation on the second downstream input signal.
6. The transparent transmission structure of a programmable logic device according to claim 5, characterized in that: the first upstream tri-state gate circuit switches logic signals according to the direction of the first upstream tri-state gate to control enabling control bits so as to realize signal input of an upstream clock signal bus and signal output of a logic and operation module of the first multi-path input; and the second upstream tri-state gate circuit switches logic signals according to the direction of the second upstream tri-state gate to control an enable control bit so as to realize signal input of an upstream data signal bus and signal output of the second multi-path input logic AND operation module.
7. The transparent transmission structure of a programmable logic device according to claim 5, characterized in that: the first downstream tri-state gate circuit switches logic signals according to the direction of the first downstream tri-state gate to control an enabling control bit so as to realize the transmission of an input signal of an upstream clock signal bus to the first downstream slave device and the transmission of the first downstream input signal to the first multi-input logic and operation module; and the second downstream tri-state gate circuit switches logic signals according to the direction of the second downstream tri-state gate to control an enable control bit so as to realize the transmission of the input signals of the upstream data signal bus to the second downstream slave device and the transmission of the second downstream input signals to the second multi-input logic AND operation module.
8. The transparent transmission structure of a programmable logic device according to claim 4, characterized in that: further comprising:
and the first inverter is connected between the first downstream tri-state gate circuit and the upstream clock signal bus direction analysis module, and the transmission directions of the clock signals of the first upstream tri-state gate circuit and the first downstream tri-state gate circuit are mutually the logical inverse.
9. The transparent transmission structure of a programmable logic device according to claim 4 or 8, characterized in that: further comprising:
and the second inverter is connected between the second downstream tri-state gate circuit and the upstream data signal bus direction analysis module, and the transmission directions of the clock signals of the second upstream tri-state gate circuit and the second downstream tri-state gate circuit are mutually the logical inverse.
10. A programmable logic device, characterized by: a transparent structure comprising the programmable logic device of any of claims 1 to 9.
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0954752A (en) * | 1995-08-16 | 1997-02-25 | Nec Eng Ltd | Control system for bidirectional bus |
| US6249149B1 (en) * | 1997-01-23 | 2001-06-19 | Altera Corporation | Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device |
| US7062589B1 (en) * | 2003-06-19 | 2006-06-13 | Altera Corporation | Bus communication apparatus for programmable logic devices and associated methods |
| CN107942899A (en) * | 2017-11-07 | 2018-04-20 | 国网辽宁省电力有限公司电力科学研究院 | A kind of multi-channel Grating signal processing circuit based on CPLD |
| CN110209107A (en) * | 2019-05-10 | 2019-09-06 | 宁波安信数控技术有限公司 | A kind of method and system by DTU remote debugging PLC device |
| CN110880998A (en) * | 2019-12-03 | 2020-03-13 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN111078614A (en) * | 2019-12-19 | 2020-04-28 | 成都理工大学工程技术学院 | Function module based on FPGA |
| CN211015473U (en) * | 2019-12-28 | 2020-07-14 | 深圳开立生物医疗科技股份有限公司 | Upgrade configuration logic circuit, programmable logic device and upgrade configuration system |
| CN113642278A (en) * | 2021-07-15 | 2021-11-12 | 加弘科技咨询(上海)有限公司 | Power consumption generation system and method of programmable logic device |
-
2021
- 2021-11-18 CN CN202111371759.7A patent/CN114253206B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0954752A (en) * | 1995-08-16 | 1997-02-25 | Nec Eng Ltd | Control system for bidirectional bus |
| US6249149B1 (en) * | 1997-01-23 | 2001-06-19 | Altera Corporation | Apparatus and method for centralized generation of an enabled clock signal for a logic array block of a programmable logic device |
| US7062589B1 (en) * | 2003-06-19 | 2006-06-13 | Altera Corporation | Bus communication apparatus for programmable logic devices and associated methods |
| CN107942899A (en) * | 2017-11-07 | 2018-04-20 | 国网辽宁省电力有限公司电力科学研究院 | A kind of multi-channel Grating signal processing circuit based on CPLD |
| CN110209107A (en) * | 2019-05-10 | 2019-09-06 | 宁波安信数控技术有限公司 | A kind of method and system by DTU remote debugging PLC device |
| CN110880998A (en) * | 2019-12-03 | 2020-03-13 | 锐捷网络股份有限公司 | Message transmission method and device based on programmable device |
| CN111078614A (en) * | 2019-12-19 | 2020-04-28 | 成都理工大学工程技术学院 | Function module based on FPGA |
| CN211015473U (en) * | 2019-12-28 | 2020-07-14 | 深圳开立生物医疗科技股份有限公司 | Upgrade configuration logic circuit, programmable logic device and upgrade configuration system |
| CN113642278A (en) * | 2021-07-15 | 2021-11-12 | 加弘科技咨询(上海)有限公司 | Power consumption generation system and method of programmable logic device |
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