CN113642278A - Power consumption generation system and method of programmable logic device - Google Patents
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- G06F30/30—Circuit design
- G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
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Abstract
The invention provides a power consumption generating system and method of a programmable logic device, wherein the system comprises a clock manager, a clock selection module, a logic resource module and a signal control module; the clock manager multiplies the frequency of an input clock signal into a plurality of paths of working clock signals; the clock selection module selects a corresponding working clock signal from the multi-path working clock signals and inputs the selected working clock signal to the logic resource module; the signal control module generates a clock selection control signal and an enabling control signal; the logic resource module divides logic resources in the programmable logic device into at least one resource group, controls the enabling of the corresponding resource group based on the enabling control signal, and controls the enabled resource group to generate power consumption under the action of the working clock signal based on the working clock signal. The invention can evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption under the condition of no formal release version of the programmable logic device.
Description
Technical Field
The invention belongs to the technical field of electronic circuits, and particularly relates to the technical field of programmable logic devices.
Background
PLD (programmable Logic device) is a generic term for programmable Logic devices, which basically performs the functions of most word devices, ranging from high-performance CPUs to simple integrated circuits. The technology of PLD has developed rapidly after the 90 s, and has now developed into CPLD, FPGA and SOC-based PLD. Currently, field programmable logic devices (FPGAs) and Complex Programmable Logic Devices (CPLDs) are two main types of programmable logic devices. FPGAs offer the highest logic density, the most abundant features, and the highest performance. These advanced devices also provide features such as built-in hardwired processors, mass storage, clock management systems, etc., and support a variety of recent ultra-fast device-to-device (device-to-device) signal technologies. FPGAs are used in a wide range of applications, from data processing and storage, to instrumentation, telecommunications, and digital signal processing, to name a few.
At present, after the programmable logic device is designed and released, the power consumption of the programmable logic device can be evaluated, the heat dissipation effect of the device can be evaluated, and the like.
Disclosure of Invention
In view of the above drawbacks of the prior art, an object of the present invention is to provide a power consumption generation system and method for a programmable logic device, which are used to solve the technical problem of inflexible and convenient power consumption evaluation of the programmable logic device in the prior art.
In order to achieve the above and other related objects, an embodiment of the present invention provides a power consumption generation system for a programmable logic device, including a clock manager, a clock selection module, a logic resource module, and a signal control module; the clock manager receives an input clock signal and multiplies the frequency of the input clock signal into a plurality of paths of working clock signals; the clock selection module is respectively connected with the clock manager and the logic resource module, selects corresponding working clock signals from the multi-path working clock signals based on the input clock selection control signals, and inputs the selected working clock signals to the logic resource module; the signal control module is respectively connected with the clock selection module and the logic resource module, generates the clock selection control signal for inputting to the clock selection module based on a clock control option combination instruction input by a user, and generates the enable control signal for inputting to the logic resource module based on an enable control instruction input by the user; the logic resource module comprises at least one resource group divided by logic resources in the programmable logic device, and the logic resource module controls the enabling of the corresponding resource group based on the enabling control signal and controls the enabled resource group based on the clock signal to generate power consumption under the action of the working clock signal.
In an embodiment of the present application, the logic resources inside the programmable logic device include a plurality of look-up tables and a plurality of flip-flops.
In an embodiment of the present application, the resource group includes at least one resource unit, and each of the resource units is composed of at least one lookup table and at least one trigger.
In an embodiment of the present application, the logic resource module controls the lookup table and the output level of the flip-flop in the enabled resource group to perform high-speed flipping based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
In an embodiment of the present application, the signal control module includes: and the virtual interface module comprises a human-computer interface with a plurality of virtual interfaces, and the virtual interface module receives a clock control option combination command and an enabling control command input by a user through the plurality of virtual interfaces.
The invention also provides a power consumption generation method of the programmable logic device, which comprises the following steps: receiving an input clock signal, and multiplying the frequency of the input clock signal into a plurality of paths of working clock signals; dividing logic resources in the programmable logic device into at least one resource group; selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to enable based on an enable control instruction input by the user; and the resource group which is enabled by control generates power consumption under the action of the selected working clock signal.
In an embodiment of the present application, the logic resources inside the programmable logic device include a plurality of look-up tables and a plurality of flip-flops.
In an embodiment of the present application, the resource group includes at least one resource unit, and each of the resource units is composed of at least one lookup table and at least one trigger.
In an embodiment of the present application, the manner of generating power consumption by the control-enabled resource group under the action of the selected operating clock signal includes: and controlling the output levels of the lookup tables and the triggers in the enabled resource group to perform high-speed turnover based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
In an embodiment of the present application, the selecting a corresponding working clock signal from the multiple working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group enablement based on an enable control instruction input by the user includes: providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces; and selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the enabling of the corresponding resource group based on an enabling control instruction received from the corresponding virtual interface.
As described above, the power consumption generation system and method of the programmable logic device of the present invention have the following advantages:
1. the invention can dynamically control the working clock in the programmable logic device and control the internal resources of the editable logic device to generate power consumption under the corresponding clock, and can flexibly and conveniently evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption under the condition of no formal release version of the programmable logic device.
2. According to the invention, the internal resources of the programmable logic device are divided into a plurality of resource groups, so that the corresponding power consumption generated by the programmable logic device can be flexibly controlled, and meanwhile, the power consumption of different gears can be dynamically configured for the programmable logic device.
3. The invention has simple and flexible realization mode and higher practicability.
Drawings
Fig. 1 is a schematic diagram showing an overall schematic structure of a power consumption generation system of a programmable logic device according to the present invention.
Fig. 2 is a schematic diagram showing logic resource division inside a programmable logic device in the power consumption generation system of the programmable logic device according to the present invention.
Fig. 3 is a schematic diagram of a signal control module in a power consumption generation system of a programmable logic device according to the present invention.
Fig. 4 is a schematic diagram showing an overall implementation principle of a power consumption generation system of a programmable logic device according to the present invention.
Fig. 5 is a flow chart illustrating a power consumption generating method of a programmable logic device according to the present invention.
Description of the element reference numerals
Power consumption generation system for 100 programmable logic device
110 clock manager
120 clock selection module
130 logical resource module
140 signal control module
141 virtual interface module
S100 to S400
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention. It is to be noted that the features in the following embodiments and examples may be combined with each other without conflict.
The present embodiment aims to provide a power consumption generation system and method for a programmable logic device, which are used to solve the technical problem in the prior art that power consumption evaluation for a programmable logic device is not flexible and convenient.
The principles and embodiments of the power consumption generation system and method of the programmable logic device of the present invention will be described in detail below, so that those skilled in the art can understand the power consumption generation system and method of the programmable logic device without creative work.
Example 1
As shown in fig. 1, the present embodiment provides a power consumption generating system 100 of a programmable logic device, where the power consumption generating system 100 of the programmable logic device includes a clock manager 110, a clock selection module 120, a logic resource module 130, and a signal control module 140.
In this embodiment, the dynamically tunable clock frequency module multiplies the frequency of the input clock signal by the mode clock manager 110 inside the programmable logic device, and the clock selection module 120 can select the working clock of the logic resource module 130, and in this embodiment, the internal resources in the logic resource module 130 are blocked, and the signal control module 140 enables or disables the internal resources of different blocks to achieve the purpose of flexibly enabling the programmable logic device to generate different power consumptions.
The clock manager 110, the clock selection module 120, the logic resource module 130, and the signal control module 140 in the power consumption generation system 100 of the programmable logic device according to the present embodiment will be described in detail below.
In this embodiment, the clock manager 110 receives an input clock signal and multiplies the input clock signal into multiple working clock signals. The frequencies of the multiple paths of frequency-doubled working clock signals are preferably different, and the frequencies of at least two paths of working clock signals can be the same.
For example, the clock manager 110 receives an input clock signal of 100Mhz, then multiplies the input clock signal of 100Mhz to multiple working clock signals of 200Mhz, 300Mhz, 400Mhz, 500Mhz, 600Mhz, etc., and then inputs the multiple working clock signals to the clock selection module 120, and the working clock signals of the logic resource module 130 are selected by the clock selection module 120.
Specifically, in this embodiment, the clock selection module 120 is respectively connected to the clock manager 110 and the logic resource module 130, selects a corresponding working clock signal from the multiple working clock signals based on an input clock selection control signal, and inputs the selected working clock signal to the logic resource module 130, so as to implement a dynamically adjustable clock frequency.
The clock selection module 120 is further connected to the signal control module 140, and selects a corresponding working clock signal from the multiple working clock signals based on the clock selection control signal output by the signal control module 140, and inputs the selected working clock signal to the logic resource module 130.
Fig. 2 is a schematic diagram showing logic resource division inside the programmable logic device in the power consumption generation system 100 of the programmable logic device according to the embodiment. In this embodiment, as shown in fig. 2, the logic resource module 130 divides logic resources inside a programmable logic device into at least one resource group, controls enabling of the corresponding resource group based on the enable control signal received from the signal control module 140, and controls the enabled resource group based on the operating clock signal received from the clock selection module 120 to generate power consumption under the action of the operating clock signal.
In this embodiment, the logic resources inside the programmable logic device include a look-up table (LUT) and a flip-flop (FF).
Specifically, in this embodiment, the logic resources in the programmable logic device are divided into at least one resource group, for example, the resource group 1, … … shown in fig. 2, and the resource group K, where each of the resource groups includes at least one resource unit, for example, the resource group 1 includes the resource unit 1, … …, and the resource unit P, and the resource group K includes the resource unit 1, … …, and the resource unit J, and the resource units included in each of the resource groups may be the same or different. Each of the resource units is composed of at least one lookup table and at least one trigger, for example, the resource unit 1 includes lookup table 1, … …, lookup table a, trigger 1, … …, and trigger B, the resource unit P includes lookup table 1, … …, lookup table C, trigger 1, … …, and trigger D, wherein the number of the lookup tables and the number of the triggers included in each resource unit may be the same or different.
That is to say, a specific internal logic resource of the programmable logic device is determined, the look-up table (LUT) and the flip-flop (FF) are main parts forming the logic resource, the logic resource module 130 in this embodiment forms a resource unit by a certain number of look-up tables (LUT) and flip-flops (FF), and then forms a resource Group (Group) by at least one resource unit, where at least one resource Group (Group) forms the internal logic resource of the programmable logic device.
For example, a resource unit includes 4096 triggers, 2048 look-up tables, and then a resource Group (Group) is composed of at least one resource unit, for example, 32768 resource units. The above description only illustrates the composition of the resource units and the resource groups, and the embodiment does not limit the number of the middle triggers and the lookup tables of the resource units, nor the number of the resource units in the resource groups, and those skilled in the art can divide the number of the resource groups, the number of the resource units in the resource groups, and the number of the triggers and the lookup tables in the resource units according to actual requirements.
The logic resource module 130 in this embodiment implements dynamically adjustable control of logic resources by enabling or disabling different numbers of resource groups, so as to flexibly control the programmable logic device to generate corresponding power consumption, and also dynamically configure power consumption of different gears for the programmable logic device.
Specifically, in this embodiment, the logic resource module 130 controls the output levels of the lookup tables and the flip-flops in the enabled resource group to perform high-speed flipping based on the operating clock signal, so that the enabled resource group generates power consumption under the action of the operating clock signal. That is, the output level of the lookup table and the flip-flop in the programmable logic device is inverted at a high speed under the action of the input working clock signal, and then power consumption is generated.
In this embodiment, the signal control module 140 is respectively connected to the clock selection module 120 and the logic resource module 130, and generates the clock selection control signal for inputting to the clock selection module 120 based on a clock control option combination instruction input by a user, and generates the enable control signal for inputting to the logic resource module 130 based on an enable control instruction input by the user.
Specifically, in the present embodiment, as shown in fig. 3, the signal control module 140 includes: the virtual interface module 141 comprises a human-machine interface with a plurality of virtual interfaces, and the virtual interface module 141 receives a clock control option combination command and an enabling control command input by a user through the plurality of virtual interfaces.
After the clock control option combination command and the enable control command input by the user through the plurality of virtual interfaces, the clock selection control signals (clock selection control signal 1, clock selection control signal 2, … …, clock selection control signal I shown in fig. 3) input to the clock selection module 120 are generated by the signal control module 140 based on the clock control option combination command, and the enable control signals (enable control signal 1, enable control signal 2, … …, enable control signal L shown in fig. 3) input to the logic resource module 130 are generated by the signal control module 140 based on the enable control command.
In this embodiment, the virtual interface module 141 is configured to simulate a configurable control signal, and the virtual interface module 141 generates a clock selection control signal and inputs the clock selection control signal to the clock selection module 120, so that the clock selection module 120 selects a corresponding working clock signal from the multiple working clock signals based on the clock selection control signal and inputs the selected working clock signal to the logic resource module 130. The virtual interface module 141 generates an enable control signal for controlling enabling or disabling of each resource group in the logic resource module 130 based on an enable control instruction input by a user, so as to enable or disable the resource group, thereby achieving the purpose of enabling the programmable logic device to generate power consumption of different gears under a certain working clock signal.
In other words, in this embodiment, the virtual interface module 141 inside the programmable logic device is used to select the operating clock frequency of the programmable logic device and enable or disable the resource group, so as to achieve the purpose of generating power consumption of different gears by the programmable logic device.
The operation of the power consumption generation system 100 of the programmable logic device in this embodiment is specifically described below with reference to fig. 4.
The clock manager 110 receives an input clock signal and multiplies the input clock signal into multiple working clock signals. For example, the clock manager 110 receives an input clock signal of 100Mhz, multiplies the input clock signal of 100Mhz by multiple working clock signals of 200Mhz, 300Mhz, 400Mhz, 500Mhz, 600Mhz, and inputs the multiple working clock signals to the clock selection module 120.
After the clock control option combination command and the enable control command are input by the user through the plurality of virtual interfaces, the signal control module 140 generates the clock selection control signal input to the clock selection module 120 based on the clock control option combination command, inputs the clock selection control signal to the clock selection module 120 so that the clock selection module 120 selects a corresponding working clock signal from the plurality of working clock signals based on the clock selection control signal, and the virtual interface module 141 generates an enable control signal for controlling enabling or disabling of each resource group in the logic resource module 130 based on the enable control command input by the user, and inputs the enable control signal to the logic resource module 130. Then, the clock selection module 120 selects a corresponding working clock signal from the multiple working clock signals based on the input clock selection control signal, and inputs the selected working clock signal to the logic resource module 130, so as to implement a dynamically adjustable clock frequency.
Finally, the logic resource module 130 controls the lookup table and the output level of the flip-flop in the enabled resource group to perform high-speed flip based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal. That is, the output level of the lookup table and the flip-flop in the programmable logic device is inverted at a high speed under the action of the input working clock signal, and then power consumption is generated. Therefore, the power consumption generation of the programmable logic device of the embodiment can dynamically control the working clock in the programmable logic device and control the internal resources of the editable logic device to generate power consumption under the corresponding clock, and the target power consumption of the programmable logic device and the heat dissipation effect of the programmable logic device under the corresponding power consumption can be flexibly and conveniently evaluated in advance under the condition of no formal release version of the programmable logic device.
Example 2
As shown in fig. 5, this embodiment further provides a power consumption generating method of a programmable logic device, including:
step S100, receiving an input clock signal, and multiplying the frequency of the input clock signal into a plurality of paths of working clock signals.
The implementation principle of step S100 in this embodiment is the same as that of the clock manager 110 in embodiment 1, and similar or identical technical features between the principles are not described again.
Step S200, dividing logic resources in the programmable logic device into at least one resource group.
In this embodiment, the logic resources inside the programmable logic device include a plurality of look-up tables and a plurality of flip-flops.
In this embodiment, the resource group includes at least one resource unit, and each resource unit is composed of at least one lookup table and at least one trigger.
Step S300, selecting a corresponding working clock signal from the multiple working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to enable based on an enable control instruction input by the user.
Specifically, in this embodiment, the selecting a corresponding operating clock signal from the multiple operating clock signals based on the clock control option combination instruction input by the user, and controlling the enabling of the corresponding resource group based on the enable control instruction input by the user includes: providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces; and selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the enabling of the corresponding resource group based on an enabling control instruction received from the corresponding virtual interface.
The implementation principle of step S300 in this embodiment is the same as the implementation principle of the clock selection module 120 and the signal control module 140 in embodiment 1, and similar or identical technical features between the principles are not repeated.
And step S400, controlling the enabled resource group to generate power consumption under the action of the selected working clock signal.
Specifically, in this embodiment, the manner of generating power consumption by the control-enabled resource group under the action of the selected operating clock signal includes: and controlling the output levels of the lookup tables and the triggers in the enabled resource group to perform high-speed turnover based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
The implementation principle of step S200 and step S400 in this embodiment is the same as the implementation principle of the logic resource module 130 in embodiment 1, and similar or identical technical features between the principles are not repeated.
In summary, the present invention can dynamically control the working clock inside the programmable logic device, and control the internal resources of the editable logic device to generate power consumption under the corresponding clock, and can flexibly and conveniently evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption without formal release version of the programmable logic device; according to the invention, the internal resources of the programmable logic device are divided into a plurality of resource groups, so that the programmable logic device can be flexibly controlled to generate corresponding power consumption, and meanwhile, the power consumption of different gears can be dynamically configured for the programmable logic device; the invention has simple and flexible realization mode and higher practicability. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (10)
1. A power consumption generation system for a programmable logic device, characterized by: the system comprises a clock manager, a clock selection module, a logic resource module and a signal control module;
the clock manager receives an input clock signal and multiplies the frequency of the input clock signal into a plurality of paths of working clock signals;
the clock selection module is respectively connected with the clock manager and the logic resource module, selects corresponding working clock signals from the multi-path working clock signals based on the input clock selection control signals, and inputs the selected working clock signals to the logic resource module;
the signal control module is respectively connected with the clock selection module and the logic resource module, generates the clock selection control signal for inputting to the clock selection module based on a clock control option combination instruction input by a user, and generates the enable control signal for inputting to the logic resource module based on an enable control instruction input by the user;
the logic resource module comprises at least one resource group divided by logic resources in the programmable logic device, and the logic resource module controls the enabling of the corresponding resource group based on the enabling control signal and controls the enabled resource group based on the clock signal to generate power consumption under the action of the working clock signal.
2. The power consumption generation system of a programmable logic device of claim 1, wherein: the logic resources inside the programmable logic device comprise a plurality of lookup tables and a plurality of triggers.
3. The power consumption generation system of a programmable logic device of claim 2, wherein: the resource group comprises at least one resource unit, and each resource unit is composed of at least one lookup table and at least one trigger.
4. The power consumption generation system of a programmable logic device of claim 2, wherein: and the logic resource module controls the lookup table in the enabled resource group and the output level of the trigger to perform high-speed turnover based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
5. The power consumption generation system of a programmable logic device of claim 1, wherein: the signal control module includes:
and the virtual interface module comprises a human-computer interface with a plurality of virtual interfaces, and the virtual interface module receives a clock control option combination command and an enabling control command input by a user through the plurality of virtual interfaces.
6. A power consumption generation method of a programmable logic device is characterized in that: the method comprises the following steps:
receiving an input clock signal, and multiplying the frequency of the input clock signal into a plurality of paths of working clock signals;
dividing logic resources in the programmable logic device into at least one resource group;
selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to enable based on an enable control instruction input by the user;
and the resource group which is enabled by control generates power consumption under the action of the selected working clock signal.
7. The power consumption generation method of a programmable logic device according to claim 6, characterized in that: the logic resources inside the programmable logic device comprise a plurality of lookup tables and a plurality of triggers.
8. The power consumption generation method of a programmable logic device according to claim 7, characterized in that: the resource group comprises at least one resource unit, and each resource unit is composed of at least one lookup table and at least one trigger.
9. The power consumption generation method of a programmable logic device according to claim 7, characterized in that: the mode of generating power consumption by the control-enabled resource group under the action of the selected working clock signal comprises the following steps: and controlling the output levels of the lookup tables and the triggers in the enabled resource group to perform high-speed turnover based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
10. The power consumption generation method of a programmable logic device according to claim 6, characterized in that: the selecting a corresponding working clock signal from the multiple working clock signals based on the clock control option combination instruction input by the user, and controlling the corresponding resource group enabling based on the enabling control instruction input by the user comprises:
providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces;
and selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the enabling of the corresponding resource group based on an enabling control instruction received from the corresponding virtual interface.
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