CN113642278B - Power consumption generation system and method of programmable logic device - Google Patents
Power consumption generation system and method of programmable logic device Download PDFInfo
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Abstract
The application provides a power consumption generation system and a method of a programmable logic device, wherein the system comprises a clock manager, a clock selection module, a logic resource module and a signal control module; the clock manager multiplies the input clock signal into a plurality of working clock signals; the clock selection module selects a corresponding working clock signal from the multipath working clock signals and inputs the selected working clock signal to the logic resource module; the signal control module generates a clock selection control signal and an enabling control signal; the logic resource module divides logic resources in the programmable logic device into at least one resource group, controls the corresponding resource group to enable based on the enabling control signal, and controls the enabled resource group to generate power consumption under the action of the working clock signal based on the working clock signal. The application can evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption under the condition of no formal release version of the programmable logic device.
Description
Technical Field
The application belongs to the technical field of electronic circuits, and particularly relates to the technical field of programmable logic devices.
Background
PLD (Programmable Logic Device) is a generic term for programmable logic devices, and PLDs basically perform the functions of most digital devices, ranging from high performance CPUs to simple integrated circuits, which can be implemented using PLDs. PLD technology has evolved rapidly after the 90 s, and has now evolved to CPLD, FPGA and SOC-based PLDs. Currently field programmable logic devices (FPGAs) and Complex Programmable Logic Devices (CPLDs) are two major types of programmable logic devices. FPGAs offer the highest logic density, the most abundant features, and the highest performance. These advanced devices also provide features such as built-in hardwired processors, mass storage, clock management systems, etc., and support a variety of latest ultra-fast device-to-device (device-to-device) signaling techniques. FPGAs are used in a wide range of applications, from data processing and storage, to instrumentation, telecommunications, and digital signal processing, among others.
At present, after the design of the programmable logic device is released, the programmable logic device can be evaluated for device power consumption, the device heat dissipation effect can be evaluated, and the programmable logic device can not be effectively evaluated for power consumption when no formally released version exists in the design stage of the programmable logic device.
Disclosure of Invention
In view of the above-mentioned drawbacks of the prior art, an object of the present application is to provide a power consumption generating system and method for a programmable logic device, which are used for solving the technical problem that in the prior art, power consumption evaluation of the programmable logic device is not flexible and convenient.
To achieve the above and other related objects, an embodiment of the present application provides a power consumption generating system of a programmable logic device, including a clock manager, a clock selecting module, a logic resource module, and a signal control module; the clock manager receives an input clock signal and multiplies the input clock signal into a plurality of working clock signals; the clock selection module is respectively connected with the clock manager and the logic resource module, selects a corresponding working clock signal from the multiple paths of working clock signals based on an input clock selection control signal, and inputs the selected working clock signal to the logic resource module; the signal control module is respectively connected with the clock selection module and the logic resource module, generates the clock selection control signal for being input to the clock selection module based on a clock control option combination instruction input by a user, and generates an enabling control signal for being input to the logic resource module based on an enabling control instruction input by the user; the logic resource module comprises at least one resource group divided by logic resources in the programmable logic device, controls the corresponding resource group to enable based on the enabling control signal, and controls the enabled resource group to generate power consumption under the action of the working clock signal based on the clock signal.
In an embodiment of the present application, the logic resources inside the programmable logic device include a plurality of lookup tables and a plurality of flip-flops.
In an embodiment of the present application, the resource group includes at least one resource unit, and each of the resource units is composed of at least one lookup table and at least one trigger.
In an embodiment of the present application, the logic resource module controls the output levels of the lookup table and the flip-flop in the enabled resource group to perform high-speed flip-flop based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
In an embodiment of the application, the signal control module includes: the virtual interface module comprises a man-machine interface with a plurality of virtual interfaces, and the virtual interface module receives clock control option combination instructions and enabling control instructions input by a user through the plurality of virtual interfaces.
The application also provides a power consumption generation method of the programmable logic device, which comprises the following steps: receiving an input clock signal and multiplying the input clock signal into a plurality of working clock signals; dividing logic resources inside the programmable logic device into at least one resource group; selecting a corresponding working clock signal from the multiple paths of working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to be enabled based on an enabling control instruction input by the user; and controlling the enabled resource group to generate power consumption under the action of the selected working clock signal.
In an embodiment of the present application, the logic resources inside the programmable logic device include a plurality of lookup tables and a plurality of flip-flops.
In an embodiment of the present application, the resource group includes at least one resource unit, and each of the resource units is composed of at least one lookup table and at least one trigger.
In an embodiment of the present application, the manner in which the resource group enabled by the control generates power consumption under the action of the selected operation clock signal includes: and controlling the output levels of the lookup table and the trigger in the enabled resource group to be turned over at high speed based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
In an embodiment of the present application, the selecting, based on the clock control option combination instruction input by the user, a corresponding working clock signal from the multiple working clock signals, and controlling, based on the enabling control instruction input by the user, the enabling of the corresponding resource group includes: providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces; and selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the corresponding resource group to be enabled based on an enabling control instruction received from the corresponding virtual interface.
As described above, the power consumption generation system and method of the programmable logic device of the present application have the following beneficial effects:
1. the application can dynamically control the working clock in the programmable logic device, and control the internal resource of the programmable logic device to generate power consumption under the corresponding clock, and can flexibly and conveniently evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption under the condition of no formal release of the programmable logic device.
2. The application divides the internal resources of the programmable logic device into a plurality of resource groups, not only can flexibly control the programmable logic device to generate corresponding power consumption, but also can dynamically configure the power consumption of different gears for the programmable logic device.
3. The application has simple and flexible implementation mode and higher practicability.
Drawings
Fig. 1 is a schematic diagram of the overall principle of the power consumption generating system of the programmable logic device according to the present application.
Fig. 2 is a schematic diagram showing the division of logic resources inside a programmable logic device in the power consumption generating system of the programmable logic device according to the present application.
Fig. 3 is a schematic diagram of a signal control module in the power consumption generating system of the programmable logic device according to the present application.
Fig. 4 is a schematic diagram showing the overall implementation principle of the power consumption generating system of the programmable logic device of the present application.
Fig. 5 is a flow chart of a method for generating power consumption of the programmable logic device according to the present application.
Description of element reference numerals
100. Power consumption generation system of programmable logic device
110. Clock manager
120. Clock selection module
130. Logic resource module
140. Signal control module
141. Virtual interface module
S100 to S400 steps
Detailed Description
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
The embodiment aims to provide a power consumption generation system and method of a programmable logic device, which are used for solving the technical problem that the power consumption evaluation of the programmable logic device is inflexible and convenient in the prior art.
The principle and implementation of the power consumption generating system and method of the programmable logic device of the present embodiment will be described in detail below, so that those skilled in the art can understand the power consumption generating system and method of the programmable logic device of the present application without creative effort.
Example 1
As shown in fig. 1, the present embodiment provides a power consumption generating system 100 of a programmable logic device, where the power consumption generating system 100 of a programmable logic device includes a clock manager 110, a clock selecting module 120, a logic resource module 130, and a signal control module 140.
In this embodiment, the dynamically adjustable clock frequency module multiplies the frequency of the input clock signal by the mode clock manager 110 inside the programmable logic device, and the clock selection module 120 can select the working clock of the logic resource module 130, and in this embodiment, the internal resources in the logic resource module 130 are partitioned, and the signal control module 140 enables or disables the internal resources of different partitions to achieve the purpose of flexibly enabling the programmable logic device to generate different power consumption.
The clock manager 110, the clock selection module 120, the logic resource module 130 and the signal control module 140 in the power consumption generation system 100 of the programmable logic device according to the present embodiment are described in detail below.
In this embodiment, the clock manager 110 receives an input clock signal and multiplies the input clock signal into multiple working clock signals. The frequencies of the multiplied multiple working clock signals are preferably different, and the frequencies of at least two working clock signals can be the same.
For example, the clock manager 110 receives an input clock signal of 100Mhz, multiplies the input clock signal of 100Mhz into multiple working clock signals of 200Mhz,300Mhz,400Mhz,500Mhz,600Mhz, etc., and then inputs the multiple working clock signals to the clock selection module 120, and the working clock signals of the logic resource module 130 are selected by the clock selection module 120.
Specifically, in this embodiment, the clock selection module 120 is respectively connected to the clock manager 110 and the logic resource module 130, selects a corresponding working clock signal from the multiple working clock signals based on the input clock selection control signal, and inputs the selected working clock signal to the logic resource module 130, so as to realize dynamically adjustable clock frequency.
The clock selection module 120 is further connected to the signal control module 140, selects a corresponding working clock signal from the multiple working clock signals based on the clock selection control signal output by the signal control module 140, and inputs the selected working clock signal to the logic resource module 130.
Fig. 2 is a schematic diagram showing the logic resource division inside the programmable logic device in the power consumption generating system 100 of the programmable logic device according to the present embodiment. In this embodiment, as shown in fig. 2, the logic resource module 130 divides logic resources inside the programmable logic device into at least one resource group, controls the corresponding resource group to be enabled based on the enable control signal received from the signal control module 140, and generates power consumption under the action of the operation clock signal based on the operation clock signal received from the clock selection module 120.
In this embodiment, the logic resources inside the programmable logic device include a look-up table (LUT) and a flip-flop (FF).
Specifically, in this embodiment, the logic resources inside the programmable logic device are divided into at least one resource group, for example, resource groups 1 and … … shown in fig. 2, and resource group K, where each resource group includes at least one resource unit, for example, resource group 1 includes resource unit 1 including resource unit 1 and … …, resource unit P, resource group K includes resource unit 1 and … …, and resource unit J, where the resource units included in each resource group may be the same or different. Each of the resource units is composed of at least one lookup table and at least one trigger, for example, the resource unit 1 includes a lookup table 1, … …, a lookup table a, a trigger 1, … …, a trigger B, and the resource unit P includes a lookup table 1, … …, a lookup table C, a trigger 1, … …, and a trigger D, wherein the number of the lookup tables and the triggers included in each of the resource units may be the same or different.
That is, the logic resources inside a specific programmable logic device are determined, the look-up table (LUT) and the flip-flop (FF) are the main parts of the logic resources, the logic resource module 130 in this embodiment forms a resource unit through a certain number of look-up tables (LUTs) and flip-flops (FFs), and then forms a resource Group (Group) by at least one resource unit, and at least one resource Group (Group) forms the logic resources inside the programmable logic device.
For example, one resource unit includes 4096 triggers, 2048 look-up tables, and then at least one resource unit forms a resource Group (Group), for example 32768 resource units form a resource Group (Group). The above only exemplifies the composition of the resource units and the resource groups, and the present embodiment does not limit the number of the triggers and the lookup tables in the resource units, nor does the number of the resource units in the resource groups, and a person skilled in the art may divide the number of the resource groups, the number of the resource units in the resource groups, and the number of the triggers and the lookup tables in the resource units according to actual requirements.
The logic resource module 130 in this embodiment implements dynamically adjustable control logic resources by enabling or disabling different number of resource groups, so as to achieve the purpose of flexibly controlling the programmable logic device to generate corresponding power consumption, and simultaneously dynamically configuring power consumption of different gears for the programmable logic device.
Specifically, in this embodiment, the logic resource module 130 controls the output levels of the lookup table and the flip-flop in the enabled resource group to perform high-speed flip-flop based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal. That is, the output level of the lookup table and the flip-flop in the programmable logic device is turned over at high speed under the action of the input operation clock signal, thereby generating power consumption.
In this embodiment, the signal control module 140 is respectively connected to the clock selection module 120 and the logic resource module 130, and generates the clock selection control signal for inputting to the clock selection module 120 based on the clock control option combination instruction input by the user, and generates the enable control signal for inputting to the logic resource module 130 based on the enable control instruction input by the user.
Specifically, in this embodiment, as shown in fig. 3, the signal control module 140 includes: the virtual interface module 141 includes a man-machine interface having a plurality of virtual interfaces, and the virtual interface module 141 receives a clock control option combination instruction and an enable control instruction input by a user through the plurality of virtual interfaces.
After a clock control option combination instruction and an enable control instruction input by a user through a plurality of virtual interfaces, the clock selection control signal (clock selection control signal 1, clock selection control signal 2, … …, clock selection control signal I shown in fig. 3) input to the clock selection module 120 is generated by the signal control module 140 based on the clock control option combination instruction, and the signal control module 140 generates an enable control signal (enable control signal 1, enable control signal 2, … …, enable control signal L shown in fig. 3) input to the logic resource module 130 based on the enable control instruction.
In this embodiment, the virtual interface module 141 is configured to simulate a configurable control signal, the virtual interface module 141 generates a clock selection control signal, and inputs the clock selection control signal to the clock selection module 120, so that the clock selection module 120 selects a corresponding working clock signal from the multiple working clock signals based on the clock selection control signal, and inputs the selected working clock signal to the logic resource module 130. The virtual interface module 141 generates an enabling control signal for controlling the enabling or disabling of each resource group in the logic resource module 130 based on the enabling control instruction input by the user, so that the enabling or disabling of the resource group is achieved, and the purpose of enabling the programmable logic device to generate power consumption of different gears under a certain working clock signal is achieved.
That is, in this embodiment, the virtual interface module 141 inside the programmable logic device is used to select the working clock frequency of the programmable logic device and enable or disable the resource group, so as to achieve the purpose that the programmable logic device generates power consumption of different gears.
The operation of the power consumption generation system 100 of the programmable logic device in this embodiment will be described in detail with reference to fig. 4.
The clock manager 110 receives an input clock signal and multiplies the input clock signal into a multi-path working clock signal. For example, the clock manager 110 receives an input clock signal of 100Mhz, multiplies the input clock signal of 100Mhz into multiple operation clock signals of 200Mhz,300Mhz,400Mhz,500Mhz,600Mhz, etc., and then inputs the multiple operation clock signals to the clock selection module 120.
After the user inputs the clock control option combination instruction and the enable control instruction through the multiple virtual interfaces, the signal control module 140 generates the clock selection control signal input to the clock selection module 120 based on the clock control option combination instruction, and inputs the clock selection control signal to the clock selection module 120, so that the clock selection module 120 selects a corresponding working clock signal from the multiple working clock signals based on the clock selection control signal, and the virtual interface module 141 generates an enable control signal for controlling enabling or disabling of each resource group in the logic resource module 130 based on the enable control instruction input by the user and inputs the enable control signal to the logic resource module 130. The clock selection module 120 then selects a corresponding working clock signal from the multiple working clock signals based on the input clock selection control signal, and inputs the selected working clock signal to the logic resource module 130, so as to realize a dynamically adjustable clock frequency.
Finally, the logic resource module 130 controls the output levels of the lookup table and the flip-flop in the enabled resource group to perform high-speed flip-flop based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal. That is, the output level of the lookup table and the flip-flop in the programmable logic device is turned over at high speed under the action of the input operation clock signal, thereby generating power consumption. Therefore, the power consumption generation of the programmable logic device of the embodiment can dynamically control the working clock in the programmable logic device and control the internal resources of the editable logic device to generate power consumption under the corresponding clock, and the target power consumption of the programmable logic device and the heat dissipation effect of the programmable logic device under the corresponding power consumption can be flexibly and conveniently evaluated in advance under the condition of no formal release version of the programmable logic device.
Example 2
As shown in fig. 5, this embodiment further provides a power consumption generating method of a programmable logic device, including:
step S100, receiving an input clock signal and multiplying the input clock signal to a multi-path working clock signal.
The implementation principle of step S100 in this embodiment is the same as that of the clock manager 110 in embodiment 1, and similar or identical technical features are not described herein.
In step S200, the logic resources inside the programmable logic device are divided into at least one resource group.
In this embodiment, the logic resources inside the programmable logic device include a plurality of lookup tables and a plurality of flip-flops.
In this embodiment, the resource group includes at least one resource unit, and each of the resource units is composed of at least one lookup table and at least one trigger.
Step S300, selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to be enabled based on an enabling control instruction input by the user.
Specifically, in this embodiment, the selecting, based on the clock control option combination instruction input by the user, a corresponding working clock signal from the multiple working clock signals, and controlling, based on the enabling control instruction input by the user, the enabling of the corresponding resource group includes: providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces; and selecting a corresponding working clock signal from the multi-path working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the corresponding resource group to be enabled based on an enabling control instruction received from the corresponding virtual interface.
The implementation principle of step S300 in this embodiment is the same as the implementation principle of the clock selection module 120 and the signal control module 140 in embodiment 1, and similar or identical technical features are not described herein.
Step S400, controlling the enabled resource group to generate power consumption under the action of the selected working clock signal.
Specifically, in this embodiment, the manner in which the resource group enabled by the control generates power consumption under the action of the selected operation clock signal includes: and controlling the output levels of the lookup table and the trigger in the enabled resource group to be turned over at high speed based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
The implementation principle of step S200 and step S400 in this embodiment is the same as that of the logic resource module 130 in embodiment 1, and similar or identical technical features are not described herein.
In summary, the application can dynamically control the working clock in the programmable logic device and control the internal resource of the editable logic device to generate power consumption under the corresponding clock, and can flexibly and conveniently evaluate the target power consumption of the programmable logic device in advance and the heat dissipation effect of the programmable logic device under the corresponding power consumption under the condition of no formal release version of the programmable logic device; the application divides the internal resources of the programmable logic device into a plurality of resource groups, which not only can flexibly control the programmable logic device to generate corresponding power consumption, but also can dynamically configure the power consumption of different gears for the programmable logic device; the application has simple and flexible implementation mode and higher practicability. Therefore, the application effectively overcomes various defects in the prior art and has high industrial utilization value.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (9)
1. A power consumption generation system of a programmable logic device, characterized by: the system comprises a clock manager, a clock selection module, a logic resource module and a signal control module;
the clock manager receives an input clock signal and multiplies the input clock signal into a plurality of working clock signals;
the clock selection module is respectively connected with the clock manager and the logic resource module, selects a corresponding working clock signal from the multiple paths of working clock signals based on an input clock selection control signal, and inputs the selected working clock signal to the logic resource module;
the signal control module is respectively connected with the clock selection module and the logic resource module, generates the clock selection control signal for being input to the clock selection module based on the clock control option combination instruction input by a user,
and generating an enable control signal for input to the logic resource module based on an enable control instruction input by a user;
the logic resource module comprises at least one resource group divided by logic resources in the programmable logic device, controls the corresponding resource group to enable based on the enabling control signal, and controls the enabled resource group to generate power consumption under the action of the working clock signal based on the clock signal.
2. The power consumption generation system of a programmable logic device of claim 1, wherein: the logic resources inside the programmable logic device include a number of look-up tables and a number of flip-flops.
3. The power consumption generation system of a programmable logic device of claim 2, wherein: the resource group comprises at least one resource unit, each of which is composed of at least one lookup table and at least one trigger.
4. The power consumption generation system of a programmable logic device of claim 2, wherein: the logic resource module controls the output level of the lookup table and the trigger in the enabled resource group to turn over at high speed based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
5. The power consumption generation system of a programmable logic device of claim 1, wherein: the signal control module comprises:
the virtual interface module comprises a man-machine interface with a plurality of virtual interfaces, and the virtual interface module receives clock control option combination instructions and enabling control instructions input by a user through the plurality of virtual interfaces.
6. A power consumption generation method of a programmable logic device is characterized in that: comprising the following steps:
receiving an input clock signal and multiplying the input clock signal into a plurality of working clock signals;
dividing logic resources inside the programmable logic device into at least one resource group;
selecting a corresponding working clock signal from the multiple working clock signals based on a clock control option combination instruction input by a user, and controlling the corresponding resource group to enable based on an enabling control instruction input by the user:
providing a human-computer interface with a plurality of virtual interfaces, and receiving a clock control option combination instruction input by a user and an enabling control instruction input by the user through the plurality of virtual interfaces;
selecting a corresponding working clock signal from the multiple paths of working clock signals based on a clock control option combination instruction received from the corresponding virtual interface, and controlling the corresponding resource group to be enabled based on an enabling control instruction received from the corresponding virtual interface;
and controlling the enabled resource group to generate power consumption under the action of the selected working clock signal.
7. The power consumption generation method of a programmable logic device according to claim 6, wherein: the logic resources inside the programmable logic device include a number of look-up tables and a number of flip-flops.
8. The power consumption generation method of a programmable logic device according to claim 7, wherein: the resource group comprises at least one resource unit, each of which is composed of at least one lookup table and at least one trigger.
9. The power consumption generation method of a programmable logic device according to claim 7, wherein: the manner in which the resource group enabled by the control generates power consumption under the action of the selected working clock signal comprises the following steps: and controlling the output levels of the lookup table and the trigger in the enabled resource group to be turned over at high speed based on the working clock signal, so that the enabled resource group generates power consumption under the action of the working clock signal.
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