CN105740179A - Parallel data acquisition system - Google Patents
Parallel data acquisition system Download PDFInfo
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- CN105740179A CN105740179A CN201410734107.9A CN201410734107A CN105740179A CN 105740179 A CN105740179 A CN 105740179A CN 201410734107 A CN201410734107 A CN 201410734107A CN 105740179 A CN105740179 A CN 105740179A
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- cpld
- port ram
- data
- signal
- dual port
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Abstract
The invention provides a parallel data acquisition system. A CPLD controls A/D sampling and conversion, data is written in a double-port RAM, and can be sent to other hosts through a serial interface. The system is formed by an ADC0809, a double-port RAMI chip DT7005, a single-chip microcomputer, a CPLD chip MAX7000S, and a serial communication module. Specifically, a clock generates signals, simulation sampling is connected with eight simulation input quantities, and just one simulation input quantity is allowed to enter each time, and through A/D conversion, the simulation input quantity is converted to an eight-bit digital quantity. A method comprises: firstly, the clock generating a starting signal, the CPLD sending a gating signal to a sampling switch, selecting a simulation sampling switch, a zeroth path analog quantity entering, after A/D conversion, the analog quantity changing into an eight-bit digital quantity and being stored in the double-port RAM, A/D feedback notifying the CPLD that conversion is completed; the CPLD selecting a first path analog quantity to enter, repeating the above process; if after 0.1 ms, the clock generating a pulse enable signal again, the CPLD gating from the zeroth path analog quantity again; in the 0.1 ms of the clock pulse signal, 0-7 paths of analog switches passing through the CPLD in sequence, in each time of gating, determining whether the analog quantity is the seventh path analog quantity, if yes, the CPLD no longer respond to an A/D feedback signal, if not, waiting for arrival of the 0.1 ms clock pulse signal, getting back to work again. The single-chip microcomputer is used for communication with an external PC machine. The PC machine inquires whether new data exists in the double-port RAM, and can read data through an interface circuit.
Description
Technical field
The present invention relates to a kind of data collecting system, particularly to the data collecting system of a kind of dual port RAM adopting CPLD.
Background technology
Along with the arrival of digital Age, the application of digital technology has penetrated into the various aspects of human lives.The development of digital display circuit has benefited from the development of device and integrated technology to a great extent, the prophesy of famous Moore's Law (Moore'sLaw) is also confirmed in the evolution of integrated circuit, and the design concept of digital display circuit and method for designing there occurs deep change in this process.From Electronic CAD, electronics CAE to electric design automation (EDA), along with being continuously increased of design complexity, the automaticity of design is more and more higher.At present, EDA technology is as the general-purpose platform of Electronic Design, gradually to supporting system-level designs；The design of digital display circuit also develops from graphic designs scheme to hardware description language design.Programming device is used widely in Design of Digital System field, not only shorten system development cycle, and utilize the field-programmable characteristic of device, according to the requirement of application, device dynamically configuration or programming be can be carried out, interpolation and the amendment of function completed simplely.
In the development of modern industry, real-time is used widely, and high-speed digital video camera system is just had higher requirement by this.Because relating to substantial amounts of design, in order to improve arithmetic speed, apply a large amount of DSP device.Data collecting system is one of core of whole system, traditional method is application MCU or the DSP analog/digital conversion gathered by software control data, so will frequently interrupting the operation of system thus the data operation of attenuation systems, the speed of data acquisition is also limited.Therefore, the scheme of CPLD is considered as one of optimal case of digital information processing system, hardware controls analog/digital conversion and data store, thus improving the Signal sampling and processing ability of system to greatest extent.
Summary of the invention
It is an object of the invention to provide a kind of data collecting system system, control A/D sampling and conversion, data write dual port RAM, it is possible to send data to other main frames by serial line interface with CPLD.
The object of the present invention is achieved like this:
The present invention is made up of ADC0809, dual port RAM I chip DT7005, single-chip microcomputer, CPLD chip MAX7000S and serial communication module.Clock produces signal specifically, and analog sampling connects 8 simulation input quantities, is once only permitted a simulation input quantity and enters, is converted to 8 bit digital quantity through A/D.First, clock produces enabling signal, and CPLD sends gating signal to sampling switch, selected analog sampling switch, and the 0th tunnel analog quantity enters, and after A/D changes, analog quantity becomes 8 bit digital quantity and is stored in dual port RAM, and A/D feeds back CPLD and informs that conversion is complete.CPLD gating the 1st tunnel analog quantity again enters, and repeats said process.If through 0.1ms, clock produces again a pulse enabling signal, and CPLD is again from the 0th tunnel analog quantity gating.In this 0.1ms process of clock pulse signal, CPLD order is by 0 ~ 7 path analoging switch, must determine whether the 7th tunnel analog quantity when each gating, if then CPLD no longer responds A/D feedback signal, and the clock pulse signal being to wait for 0.1ms arrives and reworks.Single-chip microcomputer is used for and outer PC communication, and whether PC inquiry has new data in dual port RAM, and data can be read in through interface circuit.
Wherein dual port RAM chip has the data of two groups of independences, address and control line.Any one port can be carried out independent operation.Before not introducing dual port RAM, when CPLD takes interrupt mode that CPU is carried data, CPU will stop current work and go the request outside process, the place being originally terminated is returned after having processed external event, continue original work, thus leveraging the speed of CPU, the data that therefore introducing dual port RAM transmits CPLD store, then CPU reading from dual port RAM again.
First the program circuit of the present invention for carrying out scaling down processing by 20MHz, then A/D conversion is started, select analog switch nswitch, start conversion, convert afterwards and terminate, read A/D result, result is write in dual port RAM, amendment pointer nswitch+1, if the continuing of nswitch < 7 adds 1, until terminate programs equal to 6.
CPLD pin configuration in the present invention is:
1, input pipe
CLK_IN: clock input 87
EOC: EOC input 64
: single-chip microcomputer read command 93
DATA_IN7 ~ DATA_IN0:ADC0809 data read in mouth 52,53,54,55,
65,57,80,56
2, output pin
1) A/D pin
CLK_OUT: clock division exports ADC080979
ALE: the deposited signal 58 of channel address
: channel signal 76 ~ 78
START: start A/D signal 60
OE_ADC: output allows signal 68
2) dual port RAM pin
: chip selection signal 24
: dual port RAM write signal 22
: dual port RAM read signal 23
: CPLD8 bit data outfan 20,21,19,17,
14,9,13,7
: dual port RAM 13 bit address end 49,47,45,41,37,36,33,
32,31,30,29,28,27
: single-chip microcomputer reads in RAM100
Advantages of the present invention: the present invention introduces dual port RAM in data collecting system, the control to A/D conversion is realized with CPLD chip, data are stored in dual port RAM, main frame only need to realize dual port RAM is accessed, it is achieved with A/D and changes data, thus there being other affairs of more time-triggered protocol, substantially increase the utilization ratio of main frame.
Accompanying drawing explanation
Fig. 1 is the overall structure block diagram of the present invention；
Fig. 2 is the software flow pattern of the present invention.
Detailed description of the invention
Below in conjunction with accompanying drawing citing, the present invention is described in more detail:
In conjunction with the overall structure block diagram that Fig. 1, Fig. 1 are the present invention.The present invention is made up of ADC0809, dual port RAM I chip DT7005, single-chip microcomputer, CPLD chip MAX7000S and serial communication module.Clock produces signal specifically, and analog sampling connects 8 simulation input quantities, is once only permitted a simulation input quantity and enters, is converted to 8 bit digital quantity through A/D.First, clock produces enabling signal, and CPLD sends gating signal to sampling switch, selected analog sampling switch, and the 0th tunnel analog quantity enters, and after A/D changes, analog quantity becomes 8 bit digital quantity and is stored in dual port RAM, and A/D feeds back CPLD and informs that conversion is complete.CPLD gating the 1st tunnel analog quantity again enters, and repeats said process.If through 0.1ms, clock produces again a pulse enabling signal, and CPLD is again from the 0th tunnel analog quantity gating.In this 0.1ms process of clock pulse signal, CPLD order is by 0 ~ 7 path analoging switch, must determine whether the 7th tunnel analog quantity when each gating, if then CPLD no longer responds A/D feedback signal, and the clock pulse signal being to wait for 0.1ms arrives and reworks.Single-chip microcomputer is used for and outer PC communication, and whether PC inquiry has new data in dual port RAM, and data can be read in through interface circuit.
Wherein dual port RAM chip has the data of two groups of independences, address and control line.Any one port can be carried out independent operation.Before not introducing dual port RAM, when CPLD takes interrupt mode that CPU is carried data, CPU will stop current work and go the request outside process, the place being originally terminated is returned after having processed external event, continue original work, thus leveraging the speed of CPU, the data that therefore introducing dual port RAM transmits CPLD store, then CPU reading from dual port RAM again.
It is the software flow pattern of the present invention in conjunction with Fig. 2, Fig. 2.First the program circuit of the present invention for carrying out scaling down processing by 20MHz, then A/D conversion is started, select analog switch nswitch, start conversion, convert afterwards and terminate, read A/D result, result is write in dual port RAM, amendment pointer nswitch+1, if the continuing of nswitch < 7 adds 1, until terminate programs equal to 6.CPLD pin configuration in the present invention is:
1, input pipe
CLK_IN: clock input 87
EOC: EOC input 64
: single-chip microcomputer read command 93
DATA_IN7 ~ DATA_IN0:ADC0809 data read in mouth 52,53,54,55,
65,57,80,56
2, output pin
1) A/D pin
CLK_OUT: clock division exports ADC080979
ALE: the deposited signal 58 of channel address
: channel signal 76 ~ 78
START: start A/D signal 60
OE_ADC: output allows signal 68
2) dual port RAM pin
: chip selection signal 24
: dual port RAM write signal 22
: dual port RAM read signal 23
: CPLD8 bit data outfan 20,21,19,17,
14,9,13,7
: dual port RAM 13 bit address end 49,47,45,41,37,36,33,
32,31,30,29,28,27
: single-chip microcomputer reads in RAM100.
Claims (3)
1. a Parallel Port Data Sampling System, is characterized in that the present invention is made up of ADC0809, dual port RAM I chip DT7005, single-chip microcomputer, CPLD chip MAX7000S and serial communication module；Clock produces signal specifically, and analog sampling connects 8 simulation input quantities, is once only permitted a simulation input quantity and enters, is converted to 8 bit digital quantity through A/D；First, clock produces enabling signal, and CPLD sends gating signal to sampling switch, selected analog sampling switch, and the 0th tunnel analog quantity enters, and after A/D changes, analog quantity becomes 8 bit digital quantity and is stored in dual port RAM, and A/D feeds back CPLD and informs that conversion is complete；CPLD gating the 1st tunnel analog quantity again enters, and repeats said process；If through 0.1ms, clock produces again a pulse enabling signal, and CPLD is again from the 0th tunnel analog quantity gating；In this 0.1ms process of clock pulse signal, CPLD order is by 0 ~ 7 path analoging switch, must determine whether the 7th tunnel analog quantity when each gating, if then CPLD no longer responds A/D feedback signal, and the clock pulse signal being to wait for 0.1ms arrives and reworks；Single-chip microcomputer is used for and outer PC communication, and whether PC inquiry has new data in dual port RAM, and data can be read in through interface circuit.
2. a kind of Parallel Port Data Sampling System according to claim 1, is characterized in that wherein dual port RAM chip has the data of two groups of independences, address and control line；Any one port can be carried out independent operation；Before not introducing dual port RAM, when CPLD takes interrupt mode that CPU is carried data, CPU will stop current work and go the request outside process, the place being originally terminated is returned after having processed external event, continue original work, thus leveraging the speed of CPU, the data that therefore introducing dual port RAM transmits CPLD store, then CPU reading from dual port RAM again.
3. a kind of Parallel Port Data Sampling System according to claim 1, it is characterized in that first the program circuit of the present invention for carrying out scaling down processing by 20MHz, then A/D conversion is started, select analog switch nswitch, start conversion, convert afterwards and terminate, read A/D result, result is write in dual port RAM, amendment pointer nswitch+1, if nswitch < 7 continue add 1, until equal to 6 terminate programs.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410734107.9A CN105740179A (en) | 2014-12-08 | 2014-12-08 | Parallel data acquisition system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410734107.9A CN105740179A (en) | 2014-12-08 | 2014-12-08 | Parallel data acquisition system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105740179A true CN105740179A (en) | 2016-07-06 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410734107.9A Pending CN105740179A (en) | 2014-12-08 | 2014-12-08 | Parallel data acquisition system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105629831A (en) * | 2015-12-27 | 2016-06-01 | 哈尔滨米米米业科技有限公司 | Parallel data acquisition system |
| CN109445318A (en) * | 2018-09-24 | 2019-03-08 | 武汉研润科技发展有限公司 | A kind of internet-of-things terminal control method for petrochemical industry detection |
-
2014
- 2014-12-08 CN CN201410734107.9A patent/CN105740179A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105629831A (en) * | 2015-12-27 | 2016-06-01 | 哈尔滨米米米业科技有限公司 | Parallel data acquisition system |
| CN109445318A (en) * | 2018-09-24 | 2019-03-08 | 武汉研润科技发展有限公司 | A kind of internet-of-things terminal control method for petrochemical industry detection |
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| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20160706 |
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| WD01 | Invention patent application deemed withdrawn after publication |