CN104239232B - Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) - Google Patents
Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) Download PDFInfo
- Publication number
- CN104239232B CN104239232B CN201410459309.7A CN201410459309A CN104239232B CN 104239232 B CN104239232 B CN 104239232B CN 201410459309 A CN201410459309 A CN 201410459309A CN 104239232 B CN104239232 B CN 104239232B
- Authority
- CN
- China
- Prior art keywords
- address
- write
- signal
- read
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Memory System Of A Hierarchy Structure (AREA)
- Static Random-Access Memory (AREA)
Abstract
The invention relates to a Ping-Pong cache operation structure based on a DPRAM (Dual Port Random Access Memory) in an FPGA (Field Programmable Gate Array), which is used for receiving a frame of data and reading a frame of complete data to realize the cache of the frame of data. The Ping-Pong cache operation structure based on the DPRAM in the FPGA comprises a writing operation control module, a reading operation control module and a DPRAM module. By judging the highest bit of a writing address of the DPRAM, an address space of the DPRAM is divided into a low address space and a high address space, and Ping-Pong cache operation is completed in one DPRAM; under the situation that an externally input reading control signal exists, the highest bit of the writing address is used for generating a judgment signal of a reading address; under the situation that the externally input reading control signal does not exist, cache data is automatically read. The Ping-Pong cache operation structure based on the DPRAM in the FPGA avoids the disadvantages that the traditional Ping-Pong cache operation generates a principal DPRAM module and a standby DPRAM module, two groups of writing control logics and reading control logics of the DPRAM modules are generated and the consumed resources of the FPGA are greater.
Description
Technical field
The present invention relates to a kind of ping-pong buffer operation structure based on DPRAM in FPGA, belongs to signal processing technology field.
Background technology
FPGA is used for data processing, and wherein ping-pong buffer operation is most basic operation.BlockRAM is the basic of FPGA
Memory element, DPRAM modules are to increase control logic on the basis of BlockRAM to produce, and are produced by FPGA design instrument,
Manually can not intervene, ping-pong buffer operation is to increase to read control logic and write control logic generation on the basis of DPRAM modules
's.The operation of DPRAM ping-pong buffers is made up of BlockRAM units, BlockRAM control logics, DPRAM Read-write Catrol logics.
At present, as shown in Figure 5 and Figure 6, traditional ping-pong buffer operation based on DPRAM in FPGA commonly use main part and
Two DPRAM modules of backup, for active and standby ping-pong operation, do so exists clearly disadvantageous；
1st, because producing main part DPRAM modules, backup DPRAM modules, 2 groups of BlockRAM control logics can be produced,
BlockRAM control logic resources usage amount is caused to increase；
2nd, the address space of BlockRAM is generally 1024 (18bit*1K) in FPGA,
When a frame buffer data less (being less than 512), a frame data also will be using a BlockRAM units storage, this
The operation of sample ping-pong buffer produces main part DPRAM, backs up DPRAM, produces 2 BlockRAM units, causes BlockRAM units to make
Consumption increases by 1 times；
When a frame buffer data larger (being more than 2048), a frame data need the BlockRAM for using 2 and the above mono-
Unit's storage, such ping-pong buffer operation produces main part DPRAM, backs up DPRAM, produces the BlockRAM units of 4 and the above, no
Splice optimisation technique using BlockRAM blocks beneficial to FPGA design instrument.
3rd, ping-pong buffer operation includes write control logic, reading control logic, if producing main part write control logic, backup is write
Control logic, main part read control logic, backup and read control logic, and active and standby output data selection circuit, cause DPRAM to read and write
Control logic resource usage amount is significantly increased.Three kinds of DPRAM ping-pong buffers operate used fpga logic resource usage amount pair
Than figure as shown in fig. 7, in the case of FPGA timing performance identicals, the present invention is operated relative to traditional DPRAM ping-pong buffers
Logical resource is reduced up to 50%.
The content of the invention
Present invention solves the technical problem that being：Overcome the deficiencies in the prior art, there is provided a kind of based on DPRAM in FPGA
Ping-pong buffer operates structure, the present invention that ping-pong buffer operation is completed in a DPRAM, the use of BlockRAM units is reduced
Amount, the FPGA resource usage amount for reducing BlockRAM control logics, the FPGA resource of reduction DPRAM Read-write Catrol logics are used
Amount.
The present invention technical solution be：
A kind of ping-pong buffer operation structure based on DPRAM in FPGA, including：Write operation control module, read operation control
Module, DPRAM modules；The present invention is operated in the data bandwidth of effectively writing of ping-pong buffer operation and is less than or equal to valid reading according to bandwidth
In the case of.
Write operation control module includes write data register group, writes enable depositor, write address counter；
Write data register group is deposited a Ge Sui roads clock cycle to the cache data signals of outside input, and data are write in generation
Signal, and it is input to DPRAM modules；
The data cached effective marker position signal one Ge Sui roads clock cycle of deposit for enabling register pair outside input is write, is produced
Raw write enable signal, and it is input to write address counter, DPRAM modules；
In the case of the write control signal for having outside input：
When the write control signal of outside input is effective, write address counter highest order is negated, and write address counter is except most
Address bit assignment ' 0 ' beyond a high position, produces writing address signal, and is input to DPRAM modules, while write address highest order is believed
Number it is input to read address counter；
When the write control signal of outside input is invalid, write enable effectively and write address counter is in addition to highest order
When address bit is equal to threshold value, write address counter is constant, produces writing address signal, and is input to DPRAM modules, while will write ground
Location highest order signal input is to read address counter；
When the write control signal of outside input is invalid, write enable effectively and write address counter is in addition to highest order
When address bit is not equal to threshold value, write address counter adds 1, produces writing address signal, and is input to DPRAM modules, while will write
Address highest order signal input is to read address counter；
When the write control signal of outside input it is invalid, and write enable it is invalid when, write address counter is constant, produce write address
Signal, and DPRAM modules are input to, while by write address highest order signal input to read address counter；
When the write control signal of outside input is invalid, write enable effectively and write address counter is in addition to highest order
When address bit is equal to threshold value, the first frame buffer completes signal and is changed into effective, produces the first frame buffer and completes signal, and is input to reading
Address counter；
In the case of the write control signal without outside input：
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being equal to threshold value, write address
Enumerator highest order is negated, address bit assignment ' 0 ' of the write address counter in addition to highest order, produces writing address signal, and defeated
Enter to DPRAM modules, while by write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being not equal to threshold value, writes ground
Location enumerator adds 1, produces writing address signal, and is input to DPRAM modules, while by write address highest order signal input to reading ground
Location enumerator；
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM modules,
Simultaneously by write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being equal to threshold value, the first frame
Caching completes signal and is changed into effective, and the first frame buffer completes signal and is changed into effective, produces the first frame buffer and completes signal, and is input into
To read address counter；
Read operation control module adopts read address counter；
In the case of the read control signal for having outside input：
When the read control signal of outside input is effective, the first frame buffer completes signal effectively and write address highest order refers to
During to main part spatial cache, read address counter is entered as backing up the initial address of spatial cache, produces and reads address signal, and defeated
Enter to DPRAM modules；
When the read control signal of outside input is effective, the first frame buffer completes signal effectively and write address highest order refers to
During to backup spatial cache, the initial address of part spatial cache, produces and reads address signal based on read address counter assignment, and defeated
Enter to DPRAM modules；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value
When, read address counter is constant, produces and reads address signal, and is input to DPRAM modules；
When the read control signal of outside input is invalid, and address bit of the read address counter in addition to highest order is not equal to threshold
During value, read address counter adds 1, produces and reads address signal, and is input to DPRAM modules；
When outside input read control signal effectively, and the first frame buffer complete signal it is effective when, read data effective marker
Position signal is changed into effective, produces and reads data effective marker position signal, and exports to outside；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value
When, read data effective marker position signal and be changed into invalid, produce and read data effective marker position signal, and export to outside；
In the case of the read control signal without outside input：
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup and delays from main part spatial cache
When depositing space, the initial address of the main part spatial cache of read address counter assignment is produced and reads address signal, and is input to DPRAM
Module；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part delay
When depositing space, read address counter assignment backs up the initial address of spatial cache, produces and reads address signal, and is input to DPRAM
Module；
When address bit of the read address counter in addition to highest order is equal to threshold value, read address counter is constant, produces reading
Address signal, and it is input to DPRAM modules；
When address bit of the read address counter in addition to highest order is not equal to threshold value, read address counter adds 1, produces reading
Address signal, and it is input to DPRAM modules；
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup and delays from main part spatial cache
When depositing space, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part delay
When depositing space, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When address bit of the read address counter in addition to highest order is equal to threshold value, reads data effective marker position signal and be changed into
It is invalid, produce and read data effective marker position signal, and export to outside；
Main part spatial cache and backup spatial cache are that the write address highest order exported by write address counter is entered
What row was distinguished, main part spatial cache is respectively positioned in same DPRAM with backup spatial cache；
When write address highest order is ' 0 ', represent write operation in main part spatial cache；When write address highest order is ' 1 ',
Represent write operation in backup spatial cache；
The initial address of main part spatial cache is complete ' 0 ', and the initial address for backing up spatial cache is " 100 ... 0 "；Main part is delayed
The address of the address and backup spatial cache of depositing space represents can be contrary；
When there is the write control signal of outside input, main part spatial cache and standby is controlled by the write control signal of outside input
The switching of part spatial cache；When the write control signal without outside input, main part caching is controlled by write address highest order signal empty
Between and backup spatial cache switching；
The read operation control module output is read address and is deposited to the reading address signal of DPRAM modules to the output of DPRAM modules
There is 1 to read clock cycle or 2 delays for reading clock cycle or 3 reading clock cycle between the data of storage, now to reading data
Effective marker position signal carries out corresponding delay deposit.
Present invention additionally comprises reading clock register；Write clock zone and can be the same or different with clock zone is read；When
When the clock zone of write operation event is different from the clock zone of read operation event, reads clock register and write address highest order is believed
Number at least deposit twice, produce and read the synchronous write address highest order signal of clock, and be input to read address counter；First frame delays
Deposit and complete signal and read clock register at least to deposit twice, produce and read the first synchronous frame buffer of clock and complete signal,
And it is input to read address counter.
Present invention advantage compared with prior art is：
(1) present invention completes ping-pong buffer operation in a DPRAM, when reducing the generation of DPRAM modules, BlockRAM's
Control logic resource usage amount, improves the work efficiency of FPGA, saves cost, and practicality is greatly enhanced.
(2) present invention completes ping-pong buffer operation in a DPRAM, when a frame buffer data is less than 512,
BlockRAM units usage amount reduces by one times；When a frame buffer data is more than 2048, FPGA design instrument is facilitated to use
BlockRAM blocks splice optimisation technique, so as to reduce the usage amount of BlockRAM units, nervous BlockRAM storages in FPGA
Resource utilization has the raising of matter.
(3) present invention using complete in a DPRAM ping-pong buffer operation, reduce DPRAM outside write control logic,
Read the FPGA resource usage amount that control logic, active and standby output data select the DPRAM Read-write Catrol logics such as logic, improve FPGA
Work efficiency, save cost, practicality is greatly enhanced.
Description of the drawings
Fig. 1 is module diagram of the present invention；
Fig. 2 is structural representation when present invention reading clock zone is identical with clock zone is write；
Fig. 3 reads clock zone and writes the asynchronous structural representation of clock zone for the present invention；
Fig. 4 is the BlockRAM block optimisation technique schematic diagrams that the present invention is realized；
Fig. 5 is that tradition DPRAM ping-pong buffers operate structural representation；
Fig. 6 is that tradition DPRAM ping-pong buffers operate structural representation；
Fig. 7 is the effect contrast figure of three kinds of DPRAM ping-pong buffers operations.
Specific embodiment
Just combine accompanying drawing below to be described further the present invention.
As shown in Figure 1, 2, a kind of ping-pong buffer operation structure based on DPRAM in FPGA of the present invention, including：Write operation control
Molding block, read operation control module, DPRAM modules, reading clock register；Present invention work is generally operational in ping-pong buffer
Operation effectively write data bandwidth less than or equal to valid reading according to bandwidth in the case of.
Write data register group is deposited a Ge Sui roads clock cycle to the cache data signals of outside input, and data are write in generation
Signal, and it is input to DPRAM modules；
The data cached effective marker position signal one Ge Sui roads clock cycle of deposit for enabling register pair outside input is write, is produced
Raw write enable signal, and it is input to write address counter, DPRAM modules；
Write operation control module includes write data register group, writes enable depositor, write address counter；
In the case of the write control signal for having outside input：
When the write control signal of outside input is effective, write address counter highest order is negated, and write address counter is except most
Address bit assignment ' 0 ' beyond a high position, produces writing address signal, and is input to DPRAM modules, while write address highest order is believed
Number it is input to read address counter；
When the write control signal of outside input is invalid, it is effective to write enable, and write address counter is in addition to highest order
When address bit is equal to threshold value, write address counter is constant, produces writing address signal, and is input to DPRAM modules, while will write ground
Location highest order signal input is to read address counter；
When the write control signal of outside input is invalid, write enable effectively and write address counter is in addition to highest order
When address bit is not equal to threshold value, write address counter adds 1, produces writing address signal, and is input to DPRAM modules, while will write
Address highest order signal input is to read address counter；
When the write control signal of outside input it is invalid, and write enable it is invalid when, write address counter is constant, produce write address
Signal, and DPRAM modules are input to, while by write address highest order signal input to read address counter；
When the write control signal of outside input is invalid, write enable effectively and write address counter is in addition to highest order
When address bit is equal to threshold value, the first frame buffer completes signal and is changed into effective, produces the first frame buffer and completes signal, and is input to reading
Address counter；
In the case of the write control signal without outside input：
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being equal to threshold value, write address
Enumerator highest order is negated, address bit assignment ' 0 ' of the write address counter in addition to highest order, produces writing address signal, and defeated
Enter to DPRAM modules, while by write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being not equal to threshold value, writes ground
Location enumerator adds 1, produces writing address signal, and is input to DPRAM modules, while by write address highest order signal input to reading ground
Location enumerator；
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM modules,
Simultaneously by write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being equal to threshold value, the first frame
Caching completes signal and is changed into effective, and the first frame buffer completes signal and is changed into effective, produces the first frame buffer and completes signal, and is input into
To read address counter；
Read operation control module adopts read address counter；
In the case of the read control signal for having outside input：
When the read control signal of outside input is effective, the first frame buffer completes signal effectively and write address highest order refers to
During to main part spatial cache, read address counter is entered as backing up the initial address of spatial cache, produces and reads address signal, and defeated
Enter to DPRAM modules；
When the read control signal of outside input is effective, the first frame buffer completes signal effectively, and write address highest order refers to
During to backup spatial cache, the initial address of part spatial cache, produces and reads address signal based on read address counter assignment, and defeated
Enter to DPRAM modules；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value
When, read address counter is constant, produces and reads address signal, and is input to DPRAM modules；
When the read control signal of outside input is invalid, and address bit of the read address counter in addition to highest order is not equal to threshold
During value, read address counter adds 1, produces and reads address signal, and is input to DPRAM modules；
When outside input read control signal effectively, and the first frame buffer complete signal it is effective when, read data effective marker
Position signal is changed into effective, produces and reads data effective marker position signal, and exports to outside；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value
When, read data effective marker position signal and be changed into invalid, produce and read data effective marker position signal, and export to outside；
In the case of the read control signal without outside input：
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup and delays from main part spatial cache
When depositing space, the initial address of the main part spatial cache of read address counter assignment is produced and reads address signal, and is input to DPRAM
Module；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part delay
When depositing space, read address counter assignment backs up the initial address of spatial cache, produces and reads address signal, and is input to DPRAM
Module；
When address bit of the read address counter in addition to highest order is equal to threshold value, read address counter is constant, produces reading
Address signal, and it is input to DPRAM modules；
When address bit of the read address counter in addition to highest order is not equal to threshold value, read address counter adds 1, produces reading
Address signal, and it is input to DPRAM modules；
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup and delays from main part spatial cache
When depositing space, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part delay
When depositing space, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When address bit of the read address counter in addition to highest order is equal to threshold value, reads data effective marker position signal and be changed into
It is invalid, produce and read data effective marker position signal, and export to outside；
Main part spatial cache and backup spatial cache
Main part spatial cache and backup spatial cache are that the write address highest order exported by write address counter carries out area
Point, main part spatial cache is respectively positioned in same DPRAM with backup spatial cache；
When write address highest order is ' 0 ', represent write operation in main part spatial cache；When write address highest order is ' 1 ',
Represent write operation in backup spatial cache；
The initial address of main part spatial cache is complete ' 0 ', and the initial address for backing up spatial cache is " 100 ... 0 "；Main part is delayed
The address of the address and backup spatial cache of depositing space represents can be contrary；
When there is the write control signal of outside input, main part spatial cache and standby is controlled by the write control signal of outside input
The switching of part spatial cache；When the write control signal without outside input, main part caching is controlled by write address highest order signal empty
Between and backup spatial cache switching；
Read operation control module output to the address signal of reading of DPRAM modules exports the storage of reading address to DPRAM modules
There is 1 to read clock cycle or 2 delays for reading clock cycle or 3 reading clock cycle between data, it is now effective to reading data
Flag signal carries out corresponding delay deposit.
As shown in figure 3, this structure also reside in including：Read clock register；Writing clock zone can phase with reading clock zone
Together can also be different.When the clock zone of write operation event is different from the clock zone of read operation event, read clock register
Write address highest order signal is at least deposited twice, produce and read the synchronous write address highest order signal of clock, and be input to reading ground
Location enumerator；First frame buffer completes signal reads clock register and at least deposits twice, produce read clock it is synchronous the
One frame buffer completes signal, and is input to read address counter.Write operation event, is operated in and writes clock zone, by the side for writing clock
Along driving；Read operation event, is operated in reading clock zone, is driven by the edge of reading clock.
As shown in figure 4, the present invention completes ping-pong buffer operation in a DPRAM, when a frame buffer data is less than 512
When, BlockRAM units usage amount reduces by one times；When a frame buffer data is more than 2048, FPGA design instrument is facilitated to use
BlockRAM blocks splice optimisation technique, so as to reduce the usage amount of BlockRAM units, nervous BlockRAM storages in FPGA
Resource utilization has the raising of matter.
The non-detailed description of the present invention is known to the skilled person technology.
Claims (4)
1. a kind of ping-pong buffer based on DPRAM in FPGA operates structure, it is characterised in that include：Write operation control module, reading
Operational control module, DPRAM modules；
Write operation control module includes write data register group, writes enable depositor, write address counter；
Write data register group is deposited a Ge Sui roads clock cycle to the cache data signals of outside input, and data letter is write in generation
Number, and it is input to DPRAM modules；
The data cached effective marker position signal one Ge Sui roads clock cycle of deposit for enabling register pair outside input is write, generation is write
Signal is enabled, and is input to write address counter, DPRAM modules；
In the case of the write control signal for having outside input：
When the write control signal of outside input is effective, write address counter highest order is negated, and write address counter removes highest order
Address bit assignment ' 0 ' in addition, produces writing address signal, and is input to DPRAM modules, while write address highest order signal is defeated
Enter to read address counter；
When the write control signal of outside input is invalid, write the address that enable is effective and write address counter is in addition to highest order
When position is equal to threshold value, write address counter is constant, produces writing address signal, and is input to DPRAM modules, while by write address most
High signal is input to read address counter；
When the write control signal of outside input is invalid, write the address that enable is effective and write address counter is in addition to highest order
When being not equal to threshold value, write address counter adds 1 for position, produces writing address signal, and is input to DPRAM modules, while by write address
Highest order signal input is to read address counter；
When the write control signal of outside input it is invalid, and write enable it is invalid when, write address counter is constant, produce write address letter
Number, and DPRAM modules are input to, while by write address highest order signal input to read address counter；
When the write control signal of outside input is invalid, write the address that enable is effective and write address counter is in addition to highest order
When position is equal to threshold value, the first frame buffer completes signal and is changed into effective, produces the first frame buffer and completes signal, and is input to reading address
Enumerator；
In the case of the write control signal without outside input：
When write enable signal effectively, and address bit of the write address counter in addition to highest order, when being equal to threshold value, write address is counted
Device highest order is negated, address bit assignment ' 0 ' of the write address counter in addition to highest order, produces writing address signal, and is input to
DPRAM modules, while by write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being not equal to threshold value, write address meter
Number device adds 1, produces writing address signal, and is input to DPRAM modules, while write address highest order signal input is counted to address is read
Number device；
When write enable signal is invalid, write address counter is constant, produces writing address signal, and is input to DPRAM modules, while
By write address highest order signal input to read address counter；
When write enable signal effectively, and address bit of the write address counter in addition to highest order is when being equal to threshold value, the first frame buffer
Complete signal and be changed into effective, the first frame buffer completes signal and is changed into effective, produce the first frame buffer and complete signal, and be input to reading
Address counter；
Read operation control module adopts read address counter；
In the case of the read control signal for having outside input：
When the read control signal of outside input is effective, the first frame buffer completes signal effectively and write address highest order points to master
During part spatial cache, read address counter is entered as backing up the initial address of spatial cache, produces and reads address signal, and is input to
DPRAM modules；
When the read control signal of outside input is effective, the first frame buffer completes signal effectively and the sensing of write address highest order is standby
During part spatial cache, the initial address of part spatial cache, produces and reads address signal based on read address counter assignment, and is input to
DPRAM modules；
Wherein, main part spatial cache and backup spatial cache are that the write address highest order exported by write address counter is entered
What row was distinguished, main part spatial cache is respectively positioned in same DPRAM with backup spatial cache；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value when,
Read address counter is constant, produces and reads address signal, and is input to DPRAM modules；
When the read control signal of outside input is invalid, and address bit of the read address counter in addition to highest order is not equal to threshold value
When, read address counter adds 1, produces and reads address signal, and is input to DPRAM modules；
When outside input read control signal effectively, and the first frame buffer complete signal it is effective when, read data effective marker position letter
Number it is changed into effective, produces and read data effective marker position signal, and exports to outside；
When the read control signal of outside input it is invalid, and address bit of the read address counter in addition to highest order be equal to threshold value when,
Read data effective marker position signal and be changed into invalid, produce and read data effective marker position signal, and export to outside；
In the case of the read control signal without outside input：
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup caching sky from main part spatial cache
Between when, the initial address of the main part spatial cache of read address counter assignment is produced and reads address signal, and is input to DPRAM modules；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part caching it is empty
Between when, read address counter assignment backs up the initial address of spatial cache, produces and reads address signal, and is input to DPRAM modules；
When address bit of the read address counter in addition to highest order is equal to threshold value, read address counter is constant, produces and reads address
Signal, and it is input to DPRAM modules；
When address bit of the read address counter in addition to highest order is not equal to threshold value, read address counter adds 1, produces and reads address
Signal, and it is input to DPRAM modules；
When the first frame buffer completes signal effectively, and the sensing of write address highest order is changed into backup caching sky from main part spatial cache
Between when, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When the first frame buffer completes signal effectively, and the sensing of write address highest order by back up spatial cache become based on part caching it is empty
Between when, read data effective marker position signal and be changed into effective, produce and read data effective marker position signal, and export to outside；
When address bit of the read address counter in addition to highest order is equal to threshold value, reads data effective marker position signal and be changed into nothing
Effect, produces and reads data effective marker position signal, and exports to outside.
2. a kind of ping-pong buffer based on DPRAM in FPGA according to claim 1 operates structure, it is characterised in that：Institute
It is that the write address highest order exported by write address counter is made a distinction to state main part spatial cache and backup spatial cache, main
Part spatial cache and backup spatial cache are respectively positioned in same DPRAM；
When write address highest order is ' 0 ', represent write operation in main part spatial cache；When write address highest order is ' 1 ', represent
Write operation is in backup spatial cache；
The initial address of main part spatial cache is complete ' 0 ', and the initial address for backing up spatial cache is " 100 ... 0 "；Main part caching is empty
Between address and represent can be contrary the address of backup spatial cache；
When there is the write control signal of outside input, main part spatial cache is controlled by the write control signal of outside input and backup is slow
Deposit the switching in space；When the write control signal without outside input, by write address highest order signal control main part spatial cache and
The switching of backup spatial cache.
3. a kind of ping-pong buffer based on DPRAM in FPGA according to claim 1 operates structure, it is characterised in that：Institute
State read operation control module output to DPRAM modules read address signal to DPRAM modules export read address store data it
Between have 1 to read the delays that clock cycle or 2 read clock cycle or 3 reading clock cycle, now to reading data effective marker position
Signal carries out corresponding delay deposit.
4. a kind of ping-pong buffer operation structure based on DPRAM in FPGA according to claim 1, is further characterized in that bag
Include：Read clock register；Write clock zone and can be the same or different with clock zone is read；When the clock zone of write operation event
When different from the clock zone of read operation event, read clock register and write address highest order signal is at least deposited twice, produce
It is raw to read the synchronous write address highest order signal of clock, and it is input to read address counter；When first frame buffer completes signal reading
Clock SYN register is at least deposited twice, is produced the first synchronous frame buffer of reading clock and is completed signal, and is input to reading address meter
Number device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410459309.7A CN104239232B (en) | 2014-09-10 | 2014-09-10 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410459309.7A CN104239232B (en) | 2014-09-10 | 2014-09-10 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN104239232A CN104239232A (en) | 2014-12-24 |
| CN104239232B true CN104239232B (en) | 2017-05-10 |
Family
ID=52227346
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410459309.7A Active CN104239232B (en) | 2014-09-10 | 2014-09-10 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN104239232B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105022592B (en) * | 2015-06-30 | 2018-01-05 | 北京空间机电研究所 | A kind of control system of remote sensing camera magnetic RAM |
| CN109144889B (en) * | 2018-06-25 | 2022-11-25 | 中国科学院声学研究所 | Ultrasonic testing data storage module based on FPGA and FPGA circuit |
| CN110120922B (en) * | 2019-05-14 | 2022-09-20 | 中核控制系统工程有限公司 | FPGA-based data interaction network management system and method |
| CN113641625B (en) * | 2021-08-19 | 2023-03-14 | 电子科技大学 | Four-way parallel data processing transposition system based on FPGA |
| CN114265796B (en) * | 2021-11-22 | 2024-05-14 | 四川和芯微电子股份有限公司 | RAM read-write control method |
| CN114822385A (en) * | 2022-05-27 | 2022-07-29 | 中科芯集成电路有限公司 | Write protection circuit of LED display driving chip |
| CN118069580B (en) * | 2024-04-22 | 2024-06-28 | 江苏华存电子科技有限公司 | Synchronization method for recording information by using two ping-pong caches through double CPUs |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350036A (en) * | 2008-08-26 | 2009-01-21 | 天津理工大学 | High speed real-time data acquisition system |
| CN102043590A (en) * | 2010-11-26 | 2011-05-04 | 北京北方烽火科技有限公司 | DPRAM (Double-Port Random-Access Memory) access control system |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050144509A1 (en) * | 2003-12-24 | 2005-06-30 | Fernando Zayas | Cache search accelerator method |
| US8930627B2 (en) * | 2012-06-14 | 2015-01-06 | International Business Machines Corporation | Mitigating conflicts for shared cache lines |
-
2014
- 2014-09-10 CN CN201410459309.7A patent/CN104239232B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101350036A (en) * | 2008-08-26 | 2009-01-21 | 天津理工大学 | High speed real-time data acquisition system |
| CN102043590A (en) * | 2010-11-26 | 2011-05-04 | 北京北方烽火科技有限公司 | DPRAM (Double-Port Random-Access Memory) access control system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN104239232A (en) | 2014-12-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104239232B (en) | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) | |
| CN202453864U (en) | Large-capacity asynchronous first in first out (FIFO) buffer memory based on field programmable gate array (FPGA) and double data rate (DDR) 2 synchronous dynamic random access memory (SDRAM) | |
| CN103077132B (en) | A kind of cache handles method and protocol processor high-speed cache control module | |
| CN103593306A (en) | Design method for Cache control unit of protocol processor | |
| WO2023098099A1 (en) | Ddr-based large-scale fifo data processing implementation system, method and device, processor, and storage medium thereof | |
| CN105051823B (en) | Semiconductor device | |
| CN104679681A (en) | High-speed bridge device for AHB (advanced high-performance bus) accessing on-chip SRAM (static random access memory) and operating method of high-speed bridge device | |
| CN206272746U (en) | A kind of digital video display interface module based on FPGA | |
| CN209842608U (en) | DDR3 memory control based on FPGA FIFO module | |
| CN103325426A (en) | Seamless acquisition method based on DDR2SDRAM array segmented storage | |
| CN102968394A (en) | Field programmable gate array (FPGA) and digital signal processor (DSP) data transmission system based on Ping Pong mechanism | |
| CN100546191C (en) | A kind of big capacity does not have the high-speed statistical counter that refreshes | |
| CN102931994A (en) | High-speed signal sampling and synchronizing framework and method applied to signal processing chip | |
| CN102508803A (en) | Matrix transposition memory controller | |
| CN101697491B (en) | Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM | |
| CN103294836A (en) | PCIE (peripheral component interconnect express) based radar data acquisition displaying and controlling system and method thereof | |
| CN106095722B (en) | A kind of Virtual Channel low consumption circuit applied to network-on-chip | |
| CN102004626B (en) | Dual-port memory | |
| CN100517498C (en) | First in first out memory without read delay | |
| CN104461934B (en) | A kind of time solution convolutional interleave device and method of suitable DDR memory | |
| CN102789424B (en) | External extended DDR2 (Double Data Rate 2) read-write method on basis of FPGA (Field Programmable Gate Array) and external extended DDR2 particle storage on basis of FPGA | |
| CN115268246B (en) | Shared array time-to-digital converter based on-chip storage | |
| CN203733100U (en) | Memory system structure based on PCM (Phase Change Memory) | |
| CN106919363A (en) | A kind of SDRAM buffers based on asynchronous first in first out | |
| CN103685961B (en) | Real-time processing system for achieving video data synchronization using single-chip SRAM |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |