CN106095722B - A kind of Virtual Channel low consumption circuit applied to network-on-chip - Google Patents
A kind of Virtual Channel low consumption circuit applied to network-on-chip Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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Abstract
The invention discloses a kind of Virtual Channel low consumption circuits applied to network-on-chip；It is characterized in that including：The clock that generation module and gated clock generation module form is enabled by clock and prejudges ON/OFF module；The caching being made of read-write control module and segmentation Clock gating module is segmented gating module.The present invention can improve the utilization rate of single Virtual Channel caching, avoid relying on the nervous problem of software supervision and sequential, to reduce the power consumption of input-buffer in network-on-chip, and then reduce entire NoC power consumptions, and ensure the correct transmission of data.
Description
Technical field
The invention belongs to the fields of communication technology of integrated circuit network-on-chip more particularly to a kind of applied to network-on-chip
Virtual Channel low power dissipation design circuit.
Background technology
With integrated circuit feature size reduction, clock frequency increases, and the number of transistors integrated on one single chip is more than
1000000000 orders of magnitude, interconnection line density are continuously improved, and the proportion that interconnection architecture accounts for chip overall power is increasing, therefore reduce logical
The power consumption of communication network seems most important；The power consumption of network-on-chip essentially from data packet transmission power consumption, and storage power consumption；It grinds
The persons of studying carefully have been observed that the energy that one data packet of storage is consumed is much larger than the energy of transmission one data packet consumption；When big
Data are measured when node stores, then lead to prodigious storage power consumption, therefore the caching power consumption for reducing input channel becomes particularly to weigh
It wants.
Xian Electronics Science and Technology University's Jiang Xu rising suns master thesis in 2012《NoC routers and low power loss communication network
Design》In propose using gated clock close leave unused Virtual Channel mode reduce power consumption；Disadvantage is that FIFO reading and writing
It enables when being 1, opens clock；In this case clock can lag behind read-write and enable, and sequential can be caused nervous；Nanjing boat in 2009
Empty space flight university Zhai Liang is published in Nanjing Normal University's journal《Network-on-chip routing unit low-power consumption based on gated clock is set
Meter》What is proposed in one text closes idle Virtual Channel reduction power consumption with the mode of module level gating technology；Disadvantage is that not
The clock of energy automatic switch Virtual Channel, and software support is needed, the monitoring of network is gone dependent on software to close clock；Described two
The common shortcoming of piece article：In the case where the congestion of network is bigger, by increasing the number of Virtual Channel and closing in due course
Falling the method for idle Virtual Channel reduces power consumption, but this can greatly increase Virtual Channel input moderator and the algorithm of output president's device is multiple
Miscellaneous degree and resource overhead.
Invention content
The present invention is higher in network data injection rate to overcome, and buffer size is bigger, and each nodal cache distribution is uneven
In the case of even, it is proposed that a kind of Virtual Channel low consumption circuit applied to network-on-chip, it is slow to which single Virtual Channel can be improved
The utilization rate deposited avoids relying on the nervous problem of software supervision and sequential, to reduce the work(of input-buffer in network-on-chip
Consumption, and then entire NoC power consumptions are reduced, and ensure the correct transmission of data.
Used technical solution is the present invention in order to achieve the above objectives：
A kind of Virtual Channel low consumption circuit applied to network-on-chip of the invention, the network-on-chip are the two-dimensional mesh of M × N
Network, and be made of several routing nodes；It includes input state that each routing node, which has several channels, each routing node,
Machine, decoder, moderator and crossbar switch；The input state machine has several Virtual Channels and is carried out by Virtual Channel management circuit
Control, a Virtual Channel are made of synchronization fifo；M and N is the integer more than or equal to 2；
Current routing node is by the input state machine received data packet, and using the decoder into after row decoding,
Requests for arbitration is carried out to the moderator, if obtaining arbitration license, is transmitted to the data packet by the crossbar switch
Otherwise the data packet is stored in the Virtual Channel of current routing node by next routing node；Its main feature is that：
Be provided with the Virtual Channel low consumption circuit in the input state machine, and for control the Virtual Channel when
Clock switchs and the access of the data packet；
The Virtual Channel low consumption circuit includes：Clock prejudges ON/OFF module, caching segmentation gating module；
The clock prejudges ON/OFF module：Clock enables generation module, gated clock generation module；
The caching segmentation module includes：Read-write control module is segmented Clock gating module；
Caching in all Virtual Channels is divided into the first caching FIFO_1 and second and delayed by the read-write control module
Deposit FIFO_2；
The clock enables generation module and receives the clock unlatching request signal of a routing node decoder transmission simultaneously
It is handled, obtain Virtual Channel clock enable signal and is sent to the gated clock generation module；
The gated clock generation module handles the Virtual Channel clock enable signal received, when obtaining Virtual Channel
Clock signal of the clock signal as the first caching FIFO_1；
The Virtual Channel clock signal is simultaneously sent to the segmentation Clock gating module by the gated clock generation module
The segmentation Clock gating module receives the Virtual Channel clock signal and the second caching FIFO_2 is sent
The cachings of spacing wave empty_2 and first FIFO_1 send and by full signal alm_full_1 and handle, obtain described second
Cache the clock signal clk_2 of FIFO_2；
The read-write control module receives the spacing wave empty_1 of the first caching FIFO_1 transmissions, will completely believe
Spacing wave empty_2 that number alm_full_1 and full signal full_1 and the second caching FIFO_2 are sent, will full signal
Alm_full_2 and full signal full_2 is simultaneously handled, and the reading enable signal rd_en_1 of the first caching FIFO_1 is obtained
With the reading enable signal rd_en_2 and write enable signal wr_ of write enable signal wr_en_1 and the second caching FIFO_2
en_2；To control write-in and reading behaviour of the data packet in the first caching FIFO_1 and the second caching FIFO_2
Make.
The characteristics of Virtual Channel low consumption circuit of the present invention applied to network-on-chip, lies also in：
It includes n or door, n multiple selector that the clock, which enables generation module,；
I-th or door receive i-th of clock on the four direction of routing node decoder transmission and open request
Signal simultaneously carries out inclusive-OR operation, obtains i-th of operation result and is sent to i-th of multiple selector；1≤i≤n；
I-th of multiple selector is according to the spacing wave empty_1 and spacing wave empty_2 and i-th described
Operation result obtains i-th of Virtual Channel clock enable signal.
When i-th of Virtual Channel clock enable signal is " 0 ", if i-th of operation result is " 1 ", i-th
Virtual Channel clock enable signal is set to " 1 ", if i-th of operation result is " 0 ", i-th of Virtual Channel clock is enabled
Signal is set to " 0 "；
When i-th of Virtual Channel clock enable signal is " 1 ", if i-th of operation result is " 0 ", and it is described
When the with operation result of spacing wave empty_1 and spacing wave empty_2 is " 1 ", then i-th of Virtual Channel clock is enabled believes
It number is set to " 0 "；If i-th of operation result is " 0 ", and the "AND" behaviour of the spacing wave empty_1 and spacing wave empty_2
Make result be " 0 " when, then i-th of Virtual Channel clock enable signal is set to " 1 "；If i-th of operation result is " 1 ",
Then i-th of Virtual Channel clock enable signal is set to " 1 ".
The gated clock generation module includes：N latch, n and door；
I-th of latch receives i-th of Virtual Channel clock enable signal, and is obtained according to the clock signal of the network-on-chip
To i-th of latch signal and it is sent to i-th and door；
The clock signal of i-th of latch signal and the network-on-chip is handled with door for described i-th, is obtained
I-th of Virtual Channel clock signal.
The segmentation Clock gating module includes：One multiple selector, a latch, one and door；
The multiple selector receives the spacing wave empty_2 and first caching that the second caching FIFO_2 is sent
FIFO_1 send by full signal alm_full_1 and handle, obtain it is described second caching FIFO_2 clock enable signal
And it is sent to the latch；
Clock enable signal, i-th of the Virtual Channel clock signal that the latch caches FIFO_2 according to described second, obtain
To the latch signal of i-th of Virtual Channel；
By the latch signal and i-th of Virtual Channel clock signal of i-th of Virtual Channel "AND" is carried out with door by described
Operation obtains the clock signal clk_2 of the second caching FIFO_2.
When the clock enable signal of the second caching FIFO_2 is " 0 ", if the first caching FIFO_1's will expire
Signal alm_full_1 is " 0 ", then the clock enable signal of the second caching FIFO_2 is set to " 0 "；If first caching
Full signal alm_full_1 is " 1 " by FIFO_1, then the clock enable signal of the second caching FIFO_2 is set to " 1 "；
When the clock enable signal of the second caching FIFO_2 is " 1 ", if the first caching FIFO_1's will expire
Signal alm_full_1 is " 0 ", and when the spacing wave empty_2 is " 1 ", then the clock of the second caching FIFO_2 is enabled
Signal is set to " 0 "；If the first caching FIFO_1's will expire signal alm_full_1 for " 0 ", and the spacing wave empty_2
For " 0 " when, then it is described second caching FIFO_2 clock enable signal be set to " 1 "；If the first caching FIFO_1's will expire
Signal alm_full_1 is " 1 ", then the clock enable signal of the second caching FIFO_2 is set to " 1 ".
The read-write control module includes：Three multiple selector, read states selecting module, are write two registers
State selection module, counter；
The read states selecting module according to it is described first cache FIFO_1 send spacing wave empty_1, described second
Spacing wave empty_2, the carry signal of the counter, the read states of the first register output that FIFO_2 is sent are cached to believe
Number, it obtains the status signals of the first register input and is sent to first register and is stored；
First multiple selector will full signal alm_full_1, described second according to the first caching FIFO_1 transmissions
The status signals for exporting full signal alm_full_2, first register that FIFO_2 is sent are cached, the meter is obtained
The enable signal of number device is simultaneously sent to carry signal of the counter for obtaining the counter；
The reading of status signals, i-th of Virtual Channel that second multiple selector is exported according to first register enables
Signal and low level obtain the enabled letter of reading of the reading enable signal and the second caching FIFO_2 of the first caching FIFO_1
Number；
The write state selecting module according to described first cache that FIFO_1 sends will full signal alm_full_1 and full
What signal full_1, the second caching FIFO_2 were sent will full signal alm_full_2 and full signal full_2, described first
The status signals of register output, the write state signal of second register output, obtain writing for the second register input
Status signal is simultaneously sent to second register and is stored；
Write state signal that third multiple selector is exported according to second register, i-th Virtual Channel write it is enabled
Signal and level, the write enable signal and the second caching FIFO_2 for obtaining the first caching FIFO_1 write enabled letter
Number；
If the write state signal of the second register output is the described first write state signal for caching FIFO_1, will
The write enable signal of i-th of Virtual Channel passes to the write enable signal of the first caching FIFO_1；And described second is cached
The write enable signal of FIFO_2 is set to " 0 "；
If the write state signal of the second register output is the described second write state signal for caching FIFO_2, will
The write enable signal of i-th of Virtual Channel passes to the write enable signal of the second caching FIFO_2；And described first is cached
The write enable signal of FIFO_1 is set to " 0 ".
When the status signals of the first register output are the status signals of the first caching FIFO_1；If the first caching
What FIFO_1 was sent is " 1 " by full signal alm_full_1, then the enable signal of counter is set to " 1 "；Until the counter
Counting size be equal to the described first depth for caching FIFO_1, the enable signal of the counter is set to " 0 "；If described first
Cache FIFO_1 is " 0 " by full signal alm_full_1, then the enable signal of the counter is set to " 0 "；Until described
Full signal alm_full_1 is " 1 " by one caching FIFO_1, and the enable signal of counter is set to " 1 "；
When the status signals of the first register output are the status signals of the second caching FIFO_2；If the second caching
What FIFO_2 was sent is " 1 " by full signal alm_full_2, then the enable signal of counter is set to " 1 "；Until the counter
Counting size be equal to the described second depth for caching FIFO_2, the enable signal of counter is set to " 0 "；If second caching
Full signal alm_full_2 is " 0 " by FIFO_2, then the enable signal of counter is set to " 0 "；Until second caching
Full signal alm_full_2 is " 1 " by FIFO_2, and the enable signal of the counter is set to " 1 "；
If the status signals of the first register output are the described first status signals for caching FIFO_1, will
The reading enable signal of i-th of Virtual Channel passes to the reading enable signal of the first caching FIFO_1；And described second is cached
The reading enable signal of FIFO_2 is set to " 0 "；
If the status signals of the first register output are the described second status signals for caching FIFO_2, will
The reading enable signal of i-th of Virtual Channel passes to the reading enable signal of the second caching FIFO_2；And described first is cached
The reading enable signal of FIFO_1 is set to " 0 ".
In the read states selecting module, when the status signals of the first register output are first caching
When the status signals of FIFO_1, if the carry signal of the counter is " 1 ", and the sky that the second caching FIFO_2 is sent
When signal empty_2 is " 0 ", then the status signals of the first register input are the described second reading shape for caching FIFO_2
State signal；If the carry signal of the counter is " 0 ", the status signals of the first register input are described first
Cache the status signals of FIFO_1；
When the status signals of the second register output are the status signals that described second caches FIFO_2, if described
The carry signal of counter is " 1 ", and when the spacing wave empty_1 that send of the first caching FIFO_1 are " 0 ", then described the
The status signals of one register input are the described first status signals for caching FIFO_1；If the carry of the counter is believed
Number it is " 0 ", then the status signals of first register input are the described second status signals for caching FIFO_2；
In the write state selecting module, when the write state signal of the second register output is first caching
When the write state signal of FIFO_1, if full signal alm_full_1 is " 1 " by the first caching FIFO_1 transmissions, and it is described
When the full signal full_2 that second caching FIFO_2 is sent is " 0 ", then the write state signal of the second register input is institute
State the write state signal of the second caching FIFO_2；If the full signal full_2 that the second caching FIFO_2 is sent is " 1 " or institute
State the first caching FIFO_1 transmissions is " 0 " by full signal alm_full_1, then the write state of the second register input is believed
Number for it is described first cache FIFO_1 write state signal；
When the write state signal of the second register output is the write state signal that described second caches FIFO_2, if described
What the second caching FIFO_2 was sent is " 1 " by full signal alm_full_2, and the full signal that the first caching FIFO_1 is sent
When full_1 is " 0 ", then the write state signal of the second register input is the described first write state letter for caching FIFO_1
Number；If the full signal full_1 that the first caching FIFO_1 is sent is " 1 " or what the second caching FIFO_2 was sent will expire
Signal alm_full_2 is " 0 ", then the write state signal of the second register input is writing for the second caching FIFO_2
Status signal.
Compared with prior art, advantageous effects of the invention are embodied in：
1, the Virtual Channel low consumption circuit proposed by the present invention applied to network-on-chip prejudges ON/OFF by using clock
Module and caching sectional door control module, efficiently solve caching and distribute uneven, the larger unfavorable shadow to power consumption of network congestion
It rings, the overall power of NoC is significantly reduced in the case where not increasing Virtual Channel number and not influencing network performance.
2, the present invention prejudges opening module by using clock, is gated using Method at Register Transfer Level gating technology, leads to
The switch that the method for opening request signal by upper routing node decoder tranmitting data register controls Virtual Channel clock is crossed, it is more logical than void
Enabled the problem of opening clock in advance, overcoming sequential anxiety and depended software, is write in road, to not influence network performance
In the case of reduce the power consumption of NoC.
3, Virtual Channel is divided into two sections by the present invention by using segmentation Clock gating module.Using turning off in Virtual Channel
The method of idle caching section clock, reduces caching and distributes uneven, the not high influence to power consumption of Buffer Utilization, to reduce
Power consumption in Virtual Channel.
4, the present invention is by using read-write control module, it is proposed that a kind of Read-write Catrol side being directed to two sections of cachings
Method only used a read counter and carry out reading control, and the resource that Read-write Catrol module uses is less, overcome additional control electricity
The too big problem of road resource overhead, to reduce adverse effect of the additional control circuit to lower power consumption.
Description of the drawings
Fig. 1 is the overall structure figure of the single routing node Virtual Channel setting of network-on-chip of the present invention；
Fig. 2 is low power dissipation design circuit overall structure figure of the present invention；
Fig. 3 is that the clock of Virtual Channel of the present invention prejudges the clock enable signal generation figure of ON/OFF module；
Fig. 4 is present invention segmentation Clock gating module circuit diagram；
Fig. 5 is the circuit diagram of Read-write Catrol in caching segmentation in a Virtual Channel of the invention；
Fig. 6 is the power consumption comparison diagram of Virtual Channel under the conditions of present invention segmentation FIFO；
Fig. 7 is that the present invention closes the non-north transmission Virtual Channel of multi-case data and opens the power consumption comparison diagram of three Virtual Channels；
Fig. 8 is that the present invention only opens multi-case data north transmission Virtual Channel and opens the power consumption comparison diagram of three Virtual Channels.
Specific implementation mode
In the present embodiment, network-on-chip is a kind of 6 × 6 two-dimensional network based on stratification, and it is more to be mainly used in mixing
Routing is broadcast, upper level router and bottom router are divided into, is made of 40 routing nodes；The network-on-chip is with 3 × 3 sub-network
It is divided into four multicast areas for unit；The intermediate router in each region passes through an additional port and upper level router phase
Even；It includes that input state machine, decoder, moderator and intersection are opened that each routing node, which has several channels, each routing node,
It closes；Input state machine is controlled there are three Virtual Channel and by Virtual Channel management circuit, as shown in Figure 1, these three Virtual Channels are
Unicast Virtual Channel is named as Virtual Channel 1, prevailing transmission unicast packet；Virtual Channel is transmitted in multi-case data north, is named as Virtual Channel
2, the data transfer direction of prevailing transmission upper level router is the data packet of northern transmission direction；The non-north transmission of multi-case data is empty logical
Road, is named as Virtual Channel 3, and the data transfer direction of prevailing transmission upper level router is the data packet of northern transmission direction；Virtual Channel
It includes input arbitration, output arbitration to manage circuit；Input arbitration is the channel number of the head microplate of input data packet, by writing for input
It is enabled to pass to corresponding Virtual Channel；Output arbitration is using round-robin arbitration algorithm；One Virtual Channel is made of synchronization fifo；
Current routing node is by input state machine received data packet, and using decoder into after row decoding, to moderator
Requests for arbitration is carried out, if obtaining arbitration license, data packet is transmitted to by next routing node by crossbar switch, otherwise,
Data packet is stored in the Virtual Channel of current routing node；
A kind of Virtual Channel low consumption circuit applied to network-on-chip is that the low work(of Virtual Channel is provided in input state machine
Power consumption road, and the access of the clock switch and data packet for controlling Virtual Channel；
As shown in Figure 1, Virtual Channel low consumption circuit includes：Clock prejudges ON/OFF module, caching segmentation gating module；Its
In, the switch that clock prejudges the Virtual Channel into the row clock that leave unused in ON/OFF three Virtual Channels of module pair controls.Caching segmentation gate
Module is read the caching to leave unused in Virtual Channel and is controlled into the switch of row clock.The gate control method combined by two modules can be not
In the case of changing Virtual Channel management circuit, such as when three Virtual Channels are opened, if only prejudging ON/OFF module with clock,
The clock of three Virtual Channels is all turned on, then without lower power consumption.But at this time in the case that three Virtual Channels use unevenness,
Caching segmentation gating module can be used to turn off the clock of the second idle caching FIFO_2, the work(of Virtual Channel can be effectively reduced
Consumption.
Clock prejudges ON/OFF module：Clock enables generation module, gated clock generation module；
Caching segmentation module includes：Read-write control module is segmented Clock gating module；
As shown in Fig. 2, read-write control module by the caching in all Virtual Channels be divided into the first caching FIFO_1 and
Second caching FIFO_2；Assuming that the depth of a Virtual Channel is set as 8, then the first caching FIFO_1 and the second caching FIFO_2 are equal
It is 4.
Clock enables generation module and receives the clock unlatching request signal of a routing node decoder transmission and carry out
Processing, obtains Virtual Channel clock enable signal and is sent to gated clock generation module；
Gated clock generation module handles the Virtual Channel clock enable signal received, obtains Virtual Channel clock letter
Number as first caching FIFO_1 clock signal；
Virtual Channel clock signal is simultaneously sent to segmentation Clock gating module by gated clock generation module
The spacing wave that segmentation Clock gating module receives Virtual Channel clock signal and the second caching FIFO_2 is sent
The cachings of empty_2 and first FIFO_1 sends full signal alm_full_1 and handles, and obtains the second caching FIFO_2's
Clock signal clk_2；
Read-write control module receives the spacing wave empty_1 that the first caching FIFO_1 sends, will full signal alm_
Spacing wave empty_2 that full_1 and the cachings of full signal full_1 and second FIFO_2 are sent, will full signal alm_full_2
With full signal full_2 and handled, obtain the reading enable signal rd_en_1 and write enable signal wr_ of the first caching FIFO_1
The reading enable signal rd_en_2 and write enable signal wr_en_2 of the cachings of en_1 and second FIFO_2；To control data bag
Write-in in the first caching FIFO_1 and the second caching FIFO_2 and read operation.Read-write control module primarily to
Ensure the data input and output in an orderly manner in Virtual Channel.It is a reading state of a control machine that it, which is mainly formed, and one is write state of a control
Machine, a counter, reading state of a control owner will cache in control selections current time reading first under the auxiliary of counter
FIFO_1 still reads the second caching FIFO_2.
Specifically, it includes n or door, n multiple selector that clock, which enables generation module,；
I-th or door receive i-th of clock on the four direction of routing node decoder transmission and open request
Signal and progress or operation, obtain i-th of operation result and are sent to i-th of multiple selector；1≤i≤n；With present node
For western channel, as shown in figure 3, indicate three four of western channel inputs of present node or door must receive a node when
Clock opens request signal, and the above node of institute has north passageway, Nan Tongdao, western channel, local channel to carry out void to present node to lead to
It asks in road.
I-th of multiple selector is obtained according to spacing wave empty_1 and spacing wave empty_2 and i-th of operation result
I-th of Virtual Channel clock enable signal；
When i-th Virtual Channel clock enable signal is " 0 ", if i-th of operation result is " 1 ", when i-th of Virtual Channel
Clock enable signal is set to " 1 ", if i-th of operation result is " 0 ", i-th of Virtual Channel clock enable signal is set to " 0 "；
When i-th of Virtual Channel clock enable signal is " 1 ", if i-th of operation result is " 0 ", and spacing wave empty_1
When with operation result with spacing wave empty_2 is " 1 ", then i-th of Virtual Channel clock enable signal is set to " 0 "；If i-th
Operation result is " 0 ", and when the with operation result of spacing wave empty_1 and spacing wave empty_2 is " 0 ", then i-th it is empty logical
Road clock enable signal is set to " 1 "；If i-th of operation result is " 1 ", i-th of Virtual Channel clock enable signal is set to " 1 "；
As shown in figure 3, v1_wr_req_n indicates that upper node north passageway goes out to the Virtual Channel in present node western channel hair 1
Write request, v2_wr_req_n indicate that upper node north passageway sends out write request, v3_ to the Virtual Channel 2 in the western channel of present node
Wr_req_n indicates that upper node north passageway sends out write request to the Virtual Channel 3 in the western channel of present node, and v1_wr_req_s is indicated
Upper node Nantong road sends out write request to the Virtual Channel 1 in the western channel of present node, and v2_wr_req_s indicates upper node Nantong
Road sends out write request to the Virtual Channel 2 in the western channel of present node, and v3_wr_req_s indicates upper node Nantong road to present node
The Virtual Channel 3 in western channel sends out write request；V1_wr_req_w indicates that the upper western channel of a node is logical to the void in the western channel of present node
Road 1 sends out write request, and v2_wr_req_w, which indicates that the upper western channel of a node sends out to write to the Virtual Channel 2 in the western channel of present node, to be asked
It asks, v3_wr_req_w indicates that the upper western channel of a node sends out write request, v1_wr_ to the Virtual Channel 3 in the western channel of present node
Req_l indicates that upper node local channel sends out write request to the Virtual Channel 1 in the western channel of present node, and v2_wr_req_l is indicated
Upper node local channel sends out write request to the Virtual Channel 2 in the western channel of present node, and v3_wr_req_l indicates upper node sheet
Ground channel sends out write request to the Virtual Channel 3 in the western channel of present node；As v1_wr_req_n, v1_wr_req_s, v1_wr_
Req_w, v1_wr_req_l have signal when being " 1 ", by v1_wr_req sets, indicate that Virtual Channel 1 obtains clock and opens request,
Virtual Channel clock enable signal en_clk_1 sets；Otherwise when v1_wr_req is " 0 ", and empty_v1 is " 1 ", Virtual Channel
Clock enable signal en_clk_1 resets；When v2_wr_req_n, v2_wr_req_s, v2_wr_req_w, v2_wr_req_l have
When signal is 1, by v2_wr_req sets, indicate that Virtual Channel 2 obtains clock and opens request, Virtual Channel clock enable signal en_
Clk_2 sets；Otherwise when v2_wr_req is " 0 ", and empty_v2 is " 1 ", Virtual Channel clock enable signal en_clk_2
Reset；When it is " 1 " that v3_wr_req_n, v3_wr_req_s, v3_wr_req_w, v3_wr_req_l, which have signal, by v3_wr_
Req sets indicate that Virtual Channel 1 obtains clock and opens request, Virtual Channel clock enable signal en_clk_3 sets；Otherwise when
V3_wr_req be " 0 ", and empty_v3 be 1 when, Virtual Channel clock enable signal en_clk_3 resets；
In specific implementation, gated clock generation module includes：N latch, n and door；
I-th latch receives i-th of Virtual Channel clock enable signal, and obtains the according to the clock signal of network-on-chip
I latch signal is simultaneously sent to i-th and door；
The clock signal of i-th and i-th of latch signal of door pair and network-on-chip is handled, and obtains i-th of Virtual Channel
Clock signal.
As shown in figure 3, due to devising three Virtual Channels, it is therefore desirable to which three latch, three enabled to clock with door
Signal synchronizes processing, to avoid the burr of clock signal.For example, the clock that first latch can receive Virtual Channel 1 makes
The input signal of latch is exported when the clock of network-on-chip is low level, otherwise keeps initial value by energy signal.
As shown in figure 4, segmentation Clock gating module includes：One multiple selector, a latch, one and door；
Multiple selector receives what the cachings of spacing wave empty_2 and first FIFO_1 that the second caching FIFO_2 is sent was sent
It by full signal alm_full_1 and handles, obtain the clock enable signal of the second caching FIFO_2 and is sent to latch；
When the clock enable signal of the second caching FIFO_2 is " 0 ", if the first caching FIFO_1's will full signal alm_
Full_1 is " 0 ", then the clock enable signal of the second caching FIFO_2 is set to " 0 "；If the first caching FIFO_1's will full signal
Alm_full_1 is " 1 ", then the clock enable signal of the second caching FIFO_2 is set to " 1 "；
When the clock enable signal of the second caching FIFO_2 is " 1 ", if the first caching FIFO_1's will full signal alm_
Full_1 be " 0 ", and spacing wave empty_2 be " 1 " when, then second caching FIFO_2 clock enable signal be set to " 0 "；If the
Full signal alm_full_1 is " 0 " by one caching FIFO_1, and when spacing wave empty_2 is " 0 ", then the second caching FIFO_2
Clock enable signal be set to " 1 "；If full signal alm_full_1 is " 1 ", the second caching by the first caching FIFO_1
The clock enable signal of FIFO_2 is set to " 1 "；
Latch obtains i-th according to clock enable signal, i-th of the Virtual Channel clock signal of the second caching FIFO_2
The latch signal of Virtual Channel；
By the latch signal and i-th of Virtual Channel clock signal progress with operation of i-th of Virtual Channel, the second caching is obtained
The clock signal clk_2 of FIFO_2.
As shown in figure 5, read-write control module includes：Three multiple selector, two registers, read states select mould
Block, write state selecting module, counter；
Spacing wave empty_1, the second caching FIFO_2 that read states selecting module is sent according to the first caching FIFO_1 are sent out
The carry signal of the spacing wave empty_2, counter that send, the status signals of the first register output, obtain the first register
The status signals of input are simultaneously sent to the first register and are stored；
First multiple selector caches full signal alm_full_1, second according to what the first caching FIFO_1 was sent
The status signals for exporting full signal alm_full_2, the first register that FIFO_2 is sent, obtain the enabled letter of counter
Number and be sent to counter for obtaining the carry signal of counter；As shown in figure 5, the first register corresponds to register in figure
1, the first multiple selector corresponds to multiple selector 1 in figure.The main function of counter is counted to the data of reading,
Data are enable to export in an orderly manner, the size of counter is equal to the depth of each section of caching.
When the status signals of the first register output are the status signals of the first caching FIFO_1；If the first caching
What FIFO_1 was sent is " 1 " by full signal alm_full_1, then the enable signal of counter is set to " 1 "；Until the meter of counter
Number size is equal to the depth of first segment caching, and the enable signal of counter is set to " 0 "；If the first caching FIFO_1's will full signal
Alm_full_1 is " 0 ", then the enable signal of counter is set to " 0 "；It will expire signal alm_ until the first caching FIFO_1
Full_1 is " 1 ", and the enable signal of counter is set to " 0 "；
When the status signals of the first register output are the status signals of the second caching FIFO_2；If the second caching
What FIFO_2 was sent is " 1 " by full signal alm_full_2, then the enable signal of counter is set to " 1 "；Until the meter of counter
Number size is equal to the depth of second segment caching, and the enable signal of counter is set to " 0 "；If the second caching FIFO_2's will full signal
Alm_full_2 is " 0 ", then the enable signal of counter is set to " 0 "；It will expire signal alm_ until the second caching FIFO_2
Full_2 is " 1 ", and the enable signal of counter is set to " 0 "；
Status signals that second multiple selector is exported according to the first register, the reading enable signal of i-th Virtual Channel
And low level, obtain the reading enable signal of the reading enable signal and the second caching FIFO_2 of the first caching FIFO_1；Such as Fig. 5 institutes
Show, the second multiple selector corresponds to multiple selector 2 in figure.
If the status signals of the first register output are the status signals of the first caching FIFO_1, by i-th of void
The reading enable signal in channel passes to the reading enable signal of the first caching FIFO_1；And the reading of the second caching FIFO_2 is enabled into letter
It number is set to " 0 "；
If the status signals of the first register output are the status signals of the second caching FIFO_2, by i-th of void
The reading enable signal in channel passes to the reading enable signal of the second caching FIFO_2；And the reading of the first caching FIFO_1 is enabled into letter
It number is set to " 0 "；
Write state selecting module will full signal alm_full_1 and full signal full_ according to the first caching FIFO_1 transmissions
The read states by full signal alm_full_2 and full signal full_2, the output of the first register that 1, the second caching FIFO_2 are sent
Signal, the output of the second register write state signal, obtain the write state signal of the second register input and be sent to second and post
Storage is stored；
The write enable signal of write state signal that third multiple selector is exported according to the second register, i-th Virtual Channel
And low level, obtain the write enable signal of the write enable signal and the second caching FIFO_2 of the first caching FIFO_1；Such as Fig. 5 institutes
Show, the second register corresponds to register 2 in figure, and third multiple selector corresponds to multiple selector 3 in figure.
If the write state signal of the second register output is the write state signal of the first caching FIFO_1, by i-th of void
The write enable signal in channel passes to the write enable signal of the first caching FIFO_1；And the second caching FIFO_2 is write into enabled letter
It number is set to " 0 "；
If the write state signal of the second register output is the write state signal of the second caching FIFO_2, by i-th of void
The write enable signal in channel passes to the write enable signal of the second caching FIFO_2；And the first caching FIFO_1 is write into enabled letter
It number is set to " 0 ".
When it is implemented, in read states selecting module, when the status signals of the first register output are the first caching
When the status signals of FIFO_1, if the carry signal of counter is " 1 ", and the spacing wave that the second caching FIFO_2 is sent
When empty_2 is " 0 ", then the status signals of the first register input are the status signals of the second caching FIFO_2；If meter
The carry signal of number device is " 0 ", then the status signals of the first register input are the status signals of the first caching FIFO_1；
When the status signals of the second register output are the status signals of the second caching FIFO_2, if counter
Carry signal be " 1 ", and first caching FIFO_1 send spacing wave empty_1 be " 0 " when, then the first register input reading
Status signal is the status signals of the first caching FIFO_1；If the carry signal of counter is " 0 ", the input of the first register
Status signals be second caching FIFO_2 status signals；
In write state selecting module, when the write state signal of the second register output writes shape for the first caching FIFO_1
When state signal, if what the first caching FIFO_1 sent is " 1 " by full signal alm_full_1, and the second caching FIFO_2 is sent
When full signal full_2 is " 0 ", then the write state signal of the second register input is the write state signal of the second caching FIFO_2；
It will full signal alm_ if the full signal full_2 that the second caching FIFO_2 is sent is " 1 " or the first caching FIFO_1 is sent
Full_1 is " 0 ", then the write state signal of the second register input is the write state signal of the first caching FIFO_1；
When the write state signal of the second register output is the write state signal of the second caching FIFO_2, if the second caching
What FIFO_2 was sent is " 1 " by full signal alm_full_2, and the full signal full_1 that the first caching FIFO_1 is sent is " 0 "
When, then the write state signal of the second register input is the write state signal of the first caching FIFO_1；If the first caching FIFO_1
The full signal full_1 sent is " 1 " or what the second caching FIFO_2 was sent is " 0 " by full signal alm_full_2, then second posts
The write state signal of storage input is the write state signal of the second caching FIFO_2.
As shown in fig. 6, a Virtual Channel is divided into two sections, closes idle one by the present invention in caching segmentation gate
FIFO is to reduce power consumption for section, respectively with the power consumption that Virtual Channel FIFO depth is 8,16,24,32 test input channels, works as FIFO_2
It in the case of idle, integrated based on synosys EDA platform Design Compiler, power consumption test is carried out on PT, surveyed
Test result and lower power consumption when not adding caching segmentation gate about 40%.
As shown in fig. 7, the present invention only ought transmit the idle measurement of power consumption of Virtual Channel in the non-north of multi-case data, respectively with void
Channel FIFO depth is the power consumption of 4,8,16,24 test input channels, is based on synosys EDA platform Design Compiler
Integrated, carry out power consumption test on PT, test result with lower power consumption not plus when Virtual Channel low power dissipation design circuit about
16%.
As shown in figure 8, the present invention is led to void respectively when measurement of power consumption under multi-case data only north transmission Virtual Channel working condition
Road FIFO depth is the power consumption of 4,8,16,24 test input channels, based on synosys EDA platform Design Compiler
Integrated, carry out power consumption test on PT, test result with lower power consumption not plus when Virtual Channel low power dissipation design circuit about
51%.
Claims (10)
1. a kind of Virtual Channel low consumption circuit applied to network-on-chip, the network-on-chip is the two-dimensional network of M × N, and by
Several routing nodes are constituted；It includes input state machine, decoding that each routing node, which has several channels, each routing node,
Device, moderator and crossbar switch；The input state machine has several Virtual Channels and is controlled by Virtual Channel management circuit, one
A Virtual Channel is made of synchronization fifo；M and N is the integer more than or equal to 2；
Current routing node is by the input state machine received data packet, and using the decoder into after row decoding, to institute
It states moderator and carries out requests for arbitration, if obtaining arbitration license, be transmitted to the data packet by the crossbar switch next
Otherwise the data packet is stored in the Virtual Channel of current routing node by a routing node；It is characterized in that：
The Virtual Channel low consumption circuit is provided in the input state machine, and the clock for controlling the Virtual Channel is opened
The access of pass and the data packet；
The Virtual Channel low consumption circuit includes：Clock prejudges ON/OFF module, caching segmentation gating module；
The clock prejudges ON/OFF module：Clock enables generation module, gated clock generation module；
The caching is segmented gating module：Read-write control module is segmented Clock gating module；
Caching in all Virtual Channels is divided into the cachings of the first caching FIFO_1 and second by the read-write control module
FIFO_2；
The clock enables generation module and receives the clock unlatching request signal of a routing node decoder transmission and carry out
Processing, obtains Virtual Channel clock enable signal and is sent to the gated clock generation module；
The gated clock generation module handles the Virtual Channel clock enable signal received, obtains Virtual Channel clock letter
Number as it is described first caching FIFO_1 clock signal；
The Virtual Channel clock signal is simultaneously sent to the segmentation Clock gating module by the gated clock generation module；
The sky that the segmentation Clock gating module receives the Virtual Channel clock signal and the second caching FIFO_2 is sent
The cachings of signal empty_2 and first FIFO_1 send by full signal alm_full_1 and handle, it is slow to obtain described second
Deposit the clock signal clk_2 of FIFO_2；
The read-write control module receives the spacing wave empty_1 of the first caching FIFO_1 transmissions, will expire signal
Spacing wave empty_2 that alm_full_1 and full signal full_1 and the second caching FIFO_2 are sent, will full signal
Alm_full_2 and full signal full_2 is simultaneously handled, and the reading enable signal rd_en_1 of the first caching FIFO_1 is obtained
With the reading enable signal rd_en_2 and write enable signal wr_ of write enable signal wr_en_1 and the second caching FIFO_2
en_2；To control write-in and reading behaviour of the data packet in the first caching FIFO_1 and the second caching FIFO_2
Make.
2. the Virtual Channel low consumption circuit according to claim 1 applied to network-on-chip, characterized in that the clock makes
Energy generation module includes n or door, n multiple selector；
I-th or door receive i-th of clock on the four direction of routing node decoder transmission and open request signal
And inclusive-OR operation is carried out, it obtains i-th of operation result and is sent to i-th of multiple selector；1≤i≤n；
I-th of multiple selector is according to the spacing wave empty_1 and spacing wave empty_2 and i-th of operation
As a result, obtaining i-th of Virtual Channel clock enable signal.
3. the Virtual Channel low consumption circuit according to claim 2 applied to network-on-chip, it is characterized in that：
When i-th of Virtual Channel clock enable signal is " 0 ", if i-th of operation result is " 1 ", i-th empty logical
Road clock enable signal is set to " 1 ", if i-th of operation result is " 0 ", i-th of Virtual Channel clock enable signal
It is set to " 0 "；
When i-th of Virtual Channel clock enable signal is " 1 ", if i-th of operation result is " 0 ", and the empty letter
When the with operation result of number empty_1 and spacing wave empty_2 is " 1 ", then i-th of Virtual Channel clock enable signal is set
For " 0 "；If i-th of operation result is " 0 ", and the with operation knot of the spacing wave empty_1 and spacing wave empty_2
When fruit is " 0 ", then i-th of Virtual Channel clock enable signal is set to " 1 "；If i-th of operation result is " 1 ", i-th
A Virtual Channel clock enable signal is set to " 1 ".
4. the Virtual Channel low consumption circuit according to claim 1 applied to network-on-chip, characterized in that when the gate
Clock generation module includes：N latch, n and door；
I-th latch receives i-th of Virtual Channel clock enable signal, and obtains the according to the clock signal of the network-on-chip
I latch signal is simultaneously sent to i-th and door；
The clock signal of i-th of latch signal and the network-on-chip is handled with door for described i-th, obtains i-th
A Virtual Channel clock signal.
5. the Virtual Channel low consumption circuit according to claim 1 applied to network-on-chip, characterized in that when the segmentation
Clock gating module includes：One multiple selector, a latch, one and door；
The multiple selector receives the spacing wave empty_2 and first caching that the second caching FIFO_2 is sent
FIFO_1 send by full signal alm_full_1 and handle, obtain it is described second caching FIFO_2 clock enable signal
And it is sent to the latch；
Clock enable signal, i-th of the Virtual Channel clock signal that the latch caches FIFO_2 according to described second obtain the
The latch signal of i Virtual Channel；
With operation is carried out with door by described by the latch signal and i-th of Virtual Channel clock signal of i-th of Virtual Channel,
Obtain the clock signal clk_2 of the second caching FIFO_2.
6. the Virtual Channel low consumption circuit according to claim 5 applied to network-on-chip, characterized in that
When the clock enable signal of the second caching FIFO_2 is " 0 ", if the first caching FIFO_1's will full signal
Alm_full_1 is " 0 ", then the clock enable signal of the second caching FIFO_2 is set to " 0 "；If the first caching FIFO_
The 1 signal alm_full_1 that will expire is " 1 ", then the clock enable signal of the second caching FIFO_2 is set to " 1 "；
When the clock enable signal of the second caching FIFO_2 is " 1 ", if the first caching FIFO_1's will full signal
Alm_full_1 be " 0 ", and the spacing wave empty_2 be " 1 " when, then it is described second caching FIFO_2 clock enable signal
It is set to " 0 "；If full signal alm_full_1 is " 0 " by the first caching FIFO_1, and the spacing wave empty_2 is
When " 0 ", then the clock enable signal of the second caching FIFO_2 is set to " 1 "；If the first caching FIFO_1's will completely believe
Number alm_full_1 is " 1 ", then the clock enable signal of the second caching FIFO_2 is set to " 1 ".
7. the Virtual Channel low consumption circuit according to claim 1 applied to network-on-chip, characterized in that the read-write letter
Number control module includes：Three multiple selector, read states selecting module, write state selecting module, count two registers
Device；
The read states selecting module caches spacing wave empty_1, second caching that FIFO_1 is sent according to described first
The carry signal of spacing wave empty_2, the counter that FIFO_2 is sent, the status signals of the first register output, obtain
The status signals that are inputted to the first register are simultaneously sent to first register and are stored；
First multiple selector caches the caching full signal alm_full_1, described second of FIFO_1 transmissions according to described first
The status signals for exporting full signal alm_full_2, first register that FIFO_2 is sent, obtain the counter
Enable signal and be sent to the counter for obtaining the carry signal of the counter；
Status signals that second multiple selector is exported according to first register, the reading enable signal of i-th Virtual Channel
And low level, obtain the reading enable signal of the reading enable signal and the second caching FIFO_2 of the first caching FIFO_1；
The write state selecting module will full signal alm_full_1 and full signal according to the first caching FIFO_1 transmissions
What full_1, the second caching FIFO_2 were sent will full signal alm_full_2 and full signal full_2, first deposit
The status signals of device output, the write state signal of second register output, obtain the write state of the second register input
Signal is simultaneously sent to second register and is stored；
The write enable signal of write state signal that third multiple selector is exported according to second register, i-th Virtual Channel
And low level, obtain the write enable signal of the write enable signal and the second caching FIFO_2 of the first caching FIFO_1；
If the write state signal of the second register output is the described first write state signal for caching FIFO_1, by i-th
The write enable signal of a Virtual Channel passes to the write enable signal of the first caching FIFO_1；And described second is cached
The write enable signal of FIFO_2 is set to " 0 "；
If the write state signal of the second register output is the described second write state signal for caching FIFO_2, by i-th
The write enable signal of a Virtual Channel passes to the write enable signal of the second caching FIFO_2；And described first is cached
The write enable signal of FIFO_1 is set to " 0 ".
8. the Virtual Channel low consumption circuit according to claim 7 applied to network-on-chip, characterized in that
When the status signals of the first register output are the status signals of the first caching FIFO_1；If the first caching
What FIFO_1 was sent is " 1 " by full signal alm_full_1, then the enable signal of counter is set to " 1 "；Until the counter
Counting size be equal to the described first depth for caching FIFO_1, the enable signal of the counter is set to " 0 "；If described first
Cache FIFO_1 is " 0 " by full signal alm_full_1, then the enable signal of the counter is set to " 0 "；Until described
Full signal alm_full_1 is " 1 " by one caching FIFO_1, and the enable signal of counter is set to " 1 "；
When the status signals of the first register output are the status signals of the second caching FIFO_2；If the second caching
What FIFO_2 was sent is " 1 " by full signal alm_full_2, then the enable signal of counter is set to " 1 "；Until the counter
Counting size be equal to the described second depth for caching FIFO_2, the enable signal of counter is set to " 0 "；If second caching
Full signal alm_full_2 is " 0 " by FIFO_2, then the enable signal of counter is set to " 0 "；Until second caching
Full signal alm_full_2 is " 1 " by FIFO_2, and the enable signal of the counter is set to " 1 ".
9. the Virtual Channel low consumption circuit according to claim 7 applied to network-on-chip, characterized in that
If the status signals of the first register output are the described first status signals for caching FIFO_1, by i-th
The reading enable signal of a Virtual Channel passes to the reading enable signal of the first caching FIFO_1；And described second is cached
The reading enable signal of FIFO_2 is set to " 0 "；
If the status signals of the first register output are the described second status signals for caching FIFO_2, by i-th
The reading enable signal of a Virtual Channel passes to the reading enable signal of the second caching FIFO_2；And described first is cached
The reading enable signal of FIFO_1 is set to " 0 ".
10. the Virtual Channel low consumption circuit according to claim 7 applied to network-on-chip, characterized in that
In the read states selecting module, when the status signals of the first register output are the first caching FIFO_1
When status signals, if the carry signal of the counter is " 1 ", and the spacing wave that the second caching FIFO_2 is sent
When empty_2 is " 0 ", then the status signals of the first register input are the described second read states letter for caching FIFO_2
Number；If the carry signal of the counter is " 0 ", the status signals of the first register input are first caching
The status signals of FIFO_1；
When the status signals of the second register output are the status signals that described second caches FIFO_2, if the counting
The carry signal of device be " 1 ", and it is described first caching FIFO_1 send spacing wave empty_1 be " 0 " when, then described first post
The status signals of storage input are the described first status signals for caching FIFO_1；If the carry signal of the counter is
" 0 ", then the status signals of the first register input are the described second status signals for caching FIFO_2；
In the write state selecting module, when the write state signal of the second register output is the first caching FIFO_1
When write state signal, if what the first caching FIFO_1 sent is " 1 " by full signal alm_full_1, and second caching
When the full signal full_2 that FIFO_2 is sent is " 0 ", then the write state signal of the second register input is described second slow
Deposit the write state signal of FIFO_2；If the full signal full_2 that the second caching FIFO_2 is sent is that " 1 " or described first are delayed
Deposit FIFO_1 transmissions is " 0 " by full signal alm_full_1, then the write state signal of the second register input is described
The write state signal of first caching FIFO_1；
When the write state signal of the second register output is the write state signal that described second caches FIFO_2, if described second
What caching FIFO_2 was sent is " 1 " by full signal alm_full_2, and described first caches the full signal full_ that FIFO_1 is sent
1 when being " 0 ", then the write state signal of second register input is the described first write state signal for caching FIFO_1；If
The full signal full_1 that the first caching FIFO_1 is sent is " 1 " or the second caching FIFO_2 is sent will full signal
Alm_full_2 is " 0 ", then the write state signal of the second register input is the described second write state for caching FIFO_2
Signal.
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