CN106525231B - A kind of multi-photon coincidence counting device based on PLD - Google Patents
A kind of multi-photon coincidence counting device based on PLD Download PDFInfo
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Abstract
The invention discloses a kind of multi-photon coincidence counting device based on PLD, Large Copacity based on DDR, it can support to multiple coincidence species while count, and solve the problems, such as that DDR read or write speeds are inadequate using shunting mechanism, improve the incident rate for meeting system；Also, it is capable of the generation of double inhibition random signals by the introducing of pulse shaping and synchronised clock；Meanwhile pulse delay can be with dynamic regulation, as a result of FPGA I/O resource, degree of regulation is up to tens psecs, and the linearity is good.It is consistent that dynamic regulation solves the problems, such as that the delay of input signal may not ensure every time；Moreover, introduce scan mechanism so that in the case where obtaining Single-pass count distribution, extrapolated can meet the correctness of result.In addition, PC can learn working state of system according to status word, then by control word de-regulation systematic parameter, make workflow automation, while add system robustness.
Description
Technical field
The present invention relates to photon counting field, more particularly to a kind of multi-photon coincidence counting based on PLD
Device.
Background technology
It is a kind of peculiar quantum appearance that multi-photon, which tangles, and it is in research quantum simulator, quantum error correction and quantum mould
All it is indispensable resource in the research of plan.Number of photons is more, and the free degree of single photon is bigger, multi-photon system processing letter
The ability of breath is stronger.In newest experiment progress, eight tangling for photon are achieved.
Tangled in multi-photon in experiment, the amount needs that this Quantum Properties will be tangled is converted into our world of experiences and can observe
Counting statistics is carried out to number of photons, is a kind of process of more bodies due to tangling, so it is coincidence counting to count.Coincidence counting device
Function is that meeting between two or more signals is judged and counted.
2005, Gaertner et al. proposed the scheme of address of cache.As shown in figure 1, system is by meeting probe unit, it is first
Enter first to go out buffer (FIFO), random access memory (RAM) are formed on microcontroller and piece.Meet probe unit
Operation principle be using input signal take logic or after signal as sample trigger, ground of the pattern for sampling to obtain as counter
Location is cached to FIFO.
2015, BYUNG KWON PARK et al. also achieved the counter that eight bodies meet on FPGA with door.Such as figure
Shown in 2, the system integration is on FPGA, wherein comprising time delay module, pulse shaping module meets signal generator, counter and
Processor, FPGA turn USB by serial ports and communicated with PC.The principle for meeting signal generator be by Port Multiplier gate multi input with
Door determines to meet configuration, and each multi input one kind corresponding with door meets species.
In optical quantum communication and light quantum calculate, usually require that measurement multi-photon meets event, the experiment of eight photons is led to
Road number has reached 16, meets species up to 216- 1, reject some it is insignificant meet, meet species be at least also geometry increase
Long, meanwhile, light-source brightness also reaches single channel counting rate megahertz, the level that ten megahertzs of system event rate.With experiment
The fast development of technology, port number and light-source brightness can be all continuously increased.
But Gaertner scheme realizes eight any of passage and met, and can not simply expand to dozens of
Passage because meet species be as port number exponential increase, incident rate can also increase, now the capacity of memory and
Speed can turn into bottleneck.The integrated level of discrete device and flexibility can not also match in excellence or beauty with FPGA.The more importantly event of system
Rate is 0.8MHz, dead time 14ns, it is impossible to read them in real time, therefore current experiment demand can not be met.
Meanwhile although it is 0.47ns that PARK scheme minimum, which meets window, maximum incoming frequency is 163MHz, due to
Arrived with door, several situations that meet for selecting in advance can only be counted simultaneously.After port number increases to dozens of, with door
Line will become very complicated.
The content of the invention
It is an object of the invention to provide a kind of multi-photon coincidence counting device based on PLD, by FPGA
On realize several tens of channels, tens of megahertzs of example rates, it is more to meet species, below random signals 1ppm, reads count in real time, from
Dynamicization and prolongable multi-photon coincidence counting device scheme, the coincidence counting device are also applicable in particle physics experiment.
The purpose of the present invention is achieved through the following technical solutions：
A kind of multi-photon coincidence counting device based on PLD, including：Fpga chip, DDR and PC；Wherein：
The fpga chip, the N roads electric pulse for that will receive carry out delay adjustment, integer operation, sampling, symbol successively
It is stored in after logical judgement in corresponding FIFO, then the counter by being connected with corresponding FIFO carries out coincidence counting and operated；On
The trigger condition for stating sampling is the clock signal of fpga chip internal clocking management module output；
The DDR is controlled by the MCB in fpga chip, for storing the coincidence counting of corresponding counter；
The PC, for reading the coincidence counting inside DDR and fpga chip in Block RAM and being post-processed.
Further, the fpga chip includes：Delay unit, pulse shaping unit, sample register, meet logic and sentence
Disconnected module, Clock management module, Block RAM FIFO and the first counter, DDR FIFO and the second counter, Block
RAM, WISHBONE bus and MCB；Wherein：
The delay unit, for carrying out delay adjustment to the N roads electric pulse received so that N roads electric pulse is completely right
Together；
The pulse shaping unit, for being burst pulse by the N roads electric pulse integer after alignment；
The Clock management module, for exporting corresponding clock signal after the synchronised clock of laser offer is received
Trigger condition as sampling；
The sample register, for storing sampled result；
The logic judgment module that meets has diverter function, for according to predetermined judgment mode to sampled result successively
Meet logic judgment, and according to judged result corresponding will meet address of cache send to Block RAM FIFO or
DDR FIFO；
First counter is connected with Block RAM FIFO, and second counter is connected with DDR FIFO, two
Counter is used to coincidence counting；The count results of first counter are stored in Block RAM, the meter of the second counter
Number result is stored in DDR by MCB；
The WISHBONE buses are connected by USB interface with PC, for reading and writing the data in Block RAM and DDR, with
And control word and reading state word are write into delay unit and Clock management module.
Further, delay adjustment and scan mechanism is used, its step is as follows：
The first step, the phase of Clock management module is adjusted to minimum；
Second step, Clock management module often increase by a unit of phase, and all passages are carried out with the single channel meter of certain time
Number, when phase reaches maximum, because the distribution of counting reflects the waveform of pulse, you can learn whether all pulses are all scanning
In the range of；If not, then it represents that delay exceeds dynamic regulation scope, after manually plus-minus line length again since the first step up to institute
There is pulse all in scanning range；
3rd step, regulation delay unit align all pulse centers to the maximum pulse center of delay, center definition
For pulse center；
4th step, Clock management module is adjusted by clock sampling edge alignment pulse center.
Further, meet logic judgment module to be sent out the high species address that meets of counting rate according to predetermined judgment mode
Block RAM FIFO are delivered to, remaining is met into species address sends to DDR FIFO.
Further, Block RAM and MCB include dual-port, and one of port uses for counter, another end
Confession PC passes through WISHBONE bus access；Block RAM two ports can not carry out write operation to same address simultaneously,
MCB two ports share bandwidth, i.e. two port data rates add up the bandwidth no more than DDR.
Further, delay unit, Clock management module, and Block RAM FIFO and DDR FIFO be all provided with it is stateful
Word, PC obtain current system working condition by status word；It includes：Clock is abnormal when in sync, Block RAM FIFO or
DDR FIFO write completely, and PC can prompt error message；Afterwards, PC, which attempts to restart automatically, adopts number, adopts several processes and terminates, data are automatic
Preserve into PC；
PC to delay unit and Clock management module also by writing control word to control delay unit and Clock management mould
The working method of block；It includes：Control word is write to delay unit to control the delay adjustment process of electric pulse；To Clock management
Module writes control word to adjust dynamic dephasing processes.
Further, this method also includes：Using predetermined way change described in meet logic judgment module meet address
Mapping scheme.
As seen from the above technical solution provided by the invention, 1) DDR Large Copacity causes to more meeting species
It can be counted simultaneously.2) shunting mechanism solves the problems, such as that DDR read or write speeds are slow, improves the incident rate for meeting system.
3) generation of double inhibition random signals is capable of in the introducing of pulse shaping and synchronised clock.4) pulse delay can with dynamic regulation,
As a result of FPGA I/O resource, degree of regulation is up to tens psecs, and the linearity is good.Dynamic regulation solves input signal
Delay may not ensure the problem of every time consistent.5) synchronised clock can dynamic phase shift, introduce scan mechanism so that
In the case of Single-pass count distribution, it extrapolated can meet the correctness of result, must be by known to test better than prior art
Meet signal meets result scheme whether consistent with expection.6) when carrying out counting statistics, coincidence counting can be read, only
Counting loss would not be caused in DDR bandwidth by reading and writing speed.7) PC can learn working state of system according to status word, then
By control word de-regulation systematic parameter, make workflow automation, while add system robustness.8) meeting logic can weigh
Configuration, therefore in system speed, capacity permissible range, can be applied to difference and meet experiment.9) structure is portable high.
Brief description of the drawings
In order to illustrate the technical solution of the embodiments of the present invention more clearly, required use in being described below to embodiment
Accompanying drawing be briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this
For the those of ordinary skill in field, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings
Accompanying drawing.
Fig. 1 is the address-mapping schemes schematic diagram that background of invention provides；Wherein, (a) is structured flowchart；(b) it is
Meet probe unit detailed structure view；
Fig. 2 be background of invention provide on FPGA with the schematic diagram that eight body coincidence counting devices are realized with door；Its
In, (a) is overall plan structured flowchart；(b) it is to meet signal generator structure chart；
Fig. 3 is a kind of multi-photon coincidence counting device based on PLD provided in an embodiment of the present invention；Wherein,
(a) it is the schematic diagram of overall plan；(b) it is fpga logic structure chart；
Fig. 4 is pulse delay provided in an embodiment of the present invention, integer, the timing diagram of sampling process；Wherein, (a)~(d) according to
It is secondary to be：Timing diagram after the timing diagram of initial signal, delay, the timing diagram after integer, the timing diagram according to clock sampling
Fig. 5 is scan method flow chart provided in an embodiment of the present invention.
Embodiment
With reference to the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Ground describes, it is clear that described embodiment is only part of the embodiment of the present invention, rather than whole embodiments.Based on this
The embodiment of invention, the every other implementation that those of ordinary skill in the art are obtained under the premise of creative work is not made
Example, belongs to protection scope of the present invention.
The embodiment of the present invention provides a kind of multi-photon coincidence counting device based on PLD；The multi-photon meets
Counter mainly contains the fpga chip for judging to meet species and counted, the synchronised clock that laser provides, for depositing
The substantial amounts of Double Data Rate Synchronous Dynamic RAM (DDR) for meeting data of storage and dynamic adjustment symbol
Close parameter and read the PC (PC) of coincidence counting.
Fpga chip contains substantial amounts of programmable logic resource, but only when user is organically mutual by these logical resources
Connection is even integral, could complete specific task.The fpga logic of the present invention includes delay unit, pulse shaping unit, adopted
Sample register, meet logic judgment module, Clock management module, Block RAM FIFO and the first counter, DDR FIFO and
Second counter, Block RAM, WISHBONE buses (WISHBONE Bus) and MCB (Memory Controller
Block)。
DDR has that capacity is big, fireballing advantage, is suitable as the memory for meeting data.When port number is n, symbol
Close species and share 2n- 1, exponentially increase.If port number is 20, data width 32bit, required memory capacity is
32Mbit, therefore the limited SRAM of capacity and do not apply to.
In the embodiment of the present invention, solve the problems, such as that DDR read or write speeds are inadequate using shunting mechanism, improve to meet and be
The incident rate of system.That is, sampled result is carried out successively to meet logic by meeting logic judgment module according to predetermined judgment mode
Judge, and sent corresponding data to Block RAM FIFO or DDR FIFO according to judged result；Again by counting accordingly
Number device reads the address of FIFO cachings, and the data of RAM (Block RAM FIFO or DDR FIFO) appropriate address are counted
Number.
In addition, counting loss can also be avoided using above-mentioned shunting mechanism.Assuming that the bit wide of data is 64bit, counting operation
Add one to write back it is required that reading data, example rate is 30MHz, then data volume 3840Mbps, depend alone DDR be possible to handle it is endless
Cause to lose number.And above-mentioned shunting mechanism is based on, DDR readings data add to write back in the lump to be met only for a part, another part symbol
Block RAM that (can be counting rate big meet data) be branched in fpga chip are closed to handle, because its speed is compared with DDR
Faster, it ensure that the integrality of data.But Block RAM limited storage space, therefore the scheme shunted should be appropriate according to experiment
Choose.
Dark noise and ambient noise in detector signal be present, referred to as random signals are met as caused by noise.Accidentally
The result of mistake can be caused by meeting, and be that we are undesirable.To reduce the probability that random signals occur, this invention takes
Dual measure, it is that compression meets window first, next to that the use of synchronised clock.It could only accord with meeting the pulse in window
Close, the parameter for influenceing to meet window in the present invention is pulse width, therefore is compressed into narrow arteries and veins through integer unit meeting prepulse
Punching, this compression do not influence the time of rising edge generation.Make sampling triggering with synchronised clock, rather than with the pulse occurred at first
Trigger, eliminate the possibility of false triggering.
In multi-photon experimentation, laboratory technician need to obtain some countings met in real time and carry out regulation experiment parameter, also exist
If it find that counting of abnormal can stop testing immediately when carrying out adopting several for a long time, the time has been saved.In order to realize count into
The function of data can also be read during row, Block RAM and MCB use the design of dual-port, and a port uses for counter, separately
A port accesses for USB.Block RAM two ports can not carry out write operation, MCB two ends to same address simultaneously
The shared bandwidth of mouth, as long as USB is read, data transfer rate is not too big, i.e., two port data rates add up the bandwidth no more than DDR, just
It will not cause to lose the problem of several.
If adopting several processes needs the artificial mechanically actuated step by step of laboratory technician, the waste of human resources can be caused.The present invention
It can automate and adopt number, aside earnestly be waited without laboratory technician.PC obtains current system working condition by status word, then passes through
Control word regulating system parameter.Delay unit, Clock management module, two FIFO are designed with status word.Clock is abnormal when in sync,
Block RAM FIFO or DDR FIFO write completely, and PC can prompt error message, and attempt to restart automatically and adopt number.Adopt several processes
Terminate, data are automatically saved in PC.In addition, PC with Clock management module to delay unit also by writing control word to control
Delay unit and the working method of Clock management module；It includes：Control word is write to delay unit to control prolonging for electric pulse
When adjust process；Dynamic dephasing processes are adjusted to Clock management module write state word.
Different experiments has the different demands that meets, and such as port number, meets species, or even same experiment can also become
Change.If the same set of system that meets can apply to these different scenes, objective time and fund will be saved.Because FPGA has
Reconfigurable characteristic, for different demands, as long as port number, data volume is changed without departing from the limitation of system and meets logic
, realize the recycling of same set of hardware.
In order to make it easy to understand, such scheme of the present invention is described in detail below in conjunction with the accompanying drawings.
Fig. 3 is a kind of multi-photon coincidence counting device based on PLD provided in an embodiment of the present invention；Wherein,
(a) it is the schematic diagram of overall plan；(b) fpga logic structure chart.
In the schematic diagram of overall plan as shown in Fig. 3 (a), dotted arrow is optical signal, and other arrows are electric signal.Swash
Light (laser) is incident in optical system (Optical System), is spatially separated into n light path respectively by n single-photon detecting
Survey device to receive, be converted into n roads electric pulse.Electric pulse first passes through discriminator and is converted into 3.3V TTL signals, then is managed by common IO
Pin inputs to fpga chip (FPGA Chip), laser and inputs one and laser pulse synchronization by clock dedicated pin
76MHz clocks are to fpga chip.Fpga chip is connected by PCB layout with DDR and USB chips, PC again by USB cable with
USB chips are connected.
The major function of above-mentioned fpga chip, DDR and PC is as follows：Fpga chip, for the N roads electric pulse that will receive according to
Secondary delay adjustment, the integer of carrying out is operated, sampled, meeting the address that RAM (Block RAM or DDR) is encoded to after logic judgment
It is stored in corresponding FIFO, then the counter by being connected with corresponding FIFO carries out coincidence counting and operated；DDR is controlled by FPGA cores
MCB in piece, for storing the coincidence counting of corresponding counter；PC, for reading DDR and Block RAM inside fpga chip
In coincidence counting and post-processed and controlled the course of work of coincidence counting device.
In the embodiment of the present invention, involved concrete numerical value is that citing is not construed as limiting；Exemplary, above-mentioned implementation
In example, it can apply in the experiment of eight photon entanglements, the free degree of each photon is 2, then one shares 22× 8=32 logical
Road, i.e., above-mentioned n=32.
Exemplary, fpga chip can select XILINX companies SPARTAN-6XC6SLX16-2CSG324C, DDR can be with
The CY7C68013A of CYPRESS companies is selected from Micron Technology MT46H64M16LFCK-5, USB.Can basis
Each device parameters are adjusted flexibly in experimental program, for example, selection capacity is more than 1Gbit DDR, bandwidth is in the serial of more than 10MBps
Communication such as kilomega network.
In the embodiment of the present invention, shown in fpga chip internal structure such as Fig. 3 (b), wherein solid arrow is 1bit signals, single
It is more bit signals to hollow arrow, two-way filled arrows are control signal and status signal, and bidirectional hollow arrow is believed for data
Number.
The fpga chip mainly includes：Delay unit (IODELAY2), pulse shaping unit (Pulse Shaping),
Sample register (Register), meet logic judgment module (Coincidence Logic), Clock management module (DCM),
Block RAM FIFO and the first counter, DDR FIFO and the second counter, Block RAM, WISHBONE buses and
MCB；Wherein：
The delay unit, for carrying out delay adjustment to the N roads electric pulse received so that N roads electric pulse is completely right
Together；
The pulse shaping unit, it is burst pulse for the N roads electric pulse after alignment to be carried out into integer；
The Clock management module, for exporting corresponding clock signal after the synchronised clock of laser offer is received
Trigger condition as sampling；
The sample register, for storing sampled result；
It is described to meet logic judgment module, for being carried out meeting logic successively to sampled result according to predetermined judgment mode
Judge, and mapping address will be met accordingly according to judged result and sent to Block RAM FIFO or DDR FIFO；
First counter is connected with Block RAM FIFO, and second counter is connected with DDR FIFO, two
Counter is used to coincidence counting；The count results of first counter are stored in Block RAM, the meter of the second counter
Number result is stored in DDR by MCB；
The WISHBONE buses are connected by USB interface with PC, for reading and writing the data in Block RAM and DDR, with
And control word and reading state word are write into delay unit and Clock management module.
It is exemplary, as mentioned before, it is assumed that n=32, then 32 road electric pulses pass through the IODELAY2 in I/O resource first
Carry out delay adjustment, the clock sampling that pulse after alignment is exported after integer module is changed into burst pulse by DCM, pulse when
Sequence figure is as shown in figure 4, DCM input clock is the synchronised clock that laser provides.Pattern after sampling is through meeting logic judgment
Module is cached to Block according to two parts, the FIFO of part of cache to DDR, another part is divided into after default judgment mode
RAM FIFO.After Block RAM counter obtains the data in Block RAM FIFO, read from Block RAM appropriate address
Go out data and add to write back Block RAM in the lump.It is corresponding from DDR by MCB after DDR counter obtains the data in DDR FIFO
Address read-outing data adds writes back DDR in the lump.WISHBONE buses can write control word to IODELAY2 and DCM and read shape
State word, additionally it is possible to arbitrary data in direct read/write Block RAM and pass through the arbitrary data that MCB is read and write in DDR.
USB main equipment in WISHBONE is connected by common I/O pin with USB chips.
For example, IODELAY2 status word is busy, and whether instruction delay unit is currently in displaced condition, if
For busy to put height, IODELAY2 can not receive new shift instruction.The status word of Clock management module is lock, psdone,
Limit, indicates respectively whether clock locks, and whether phase shift is completed, and whether phase goes beyond the scope.Two FIFO status word is
Whether full, instruction FIFO are full.WISHBONE buses are connected by status word and control word with two FIFO, in Fig. 3 (b) not
Show.
As shown in figure 4, (a) therein~(d) is followed successively by：After timing diagram, integer after the timing diagram of initial signal, delay
Timing diagram, the timing diagram according to clock sampling.CH1~CH3,3 tunnel pulses are only illustrated in Fig. 4.
In the embodiment of the present invention, completing the alignment of pulse and sampling needs the mechanism of scanning, as shown in figure 5, its step
It is as follows：
The first step, the phase of Clock management module is adjusted to minimum；
Second step, Clock management module often increase by a unit of phase, and all passages are carried out with the single channel meter of certain time
Number, when phase reaches maximum, because the distribution of counting reflects the waveform of pulse, you can learn whether all pulses are all scanning
In the range of；If not, then it represents that delay exceeds dynamic regulation scope, after manually plus-minus line length again since the first step up to institute
There is pulse all in scanning range；
3rd step, regulation delay unit align all pulse centers to the maximum pulse center of delay, center definition
For pulse center；
4th step, Clock management module is adjusted by clock sampling edge alignment pulse center.
Can be according to actual feelings it will be understood by those skilled in the art that meeting judgment mode predetermined in logic judgment module
Condition adjusts, for example, according to predetermined judgment mode sent the high species address that meets of counting rate to Block RAM FIFO,
Remaining is met into species address to send to DDR FIFO.
It is exemplary, in the experiment of eight photon entanglements, account for always meeting example because single photon and two photons meet
More than 90%, reach 20MHz, therefore, meeting logic judgment module can be according to predetermined judgment mode by single photon and two light
Subdata is sent to the fast Block RAM of processing speed, and DDR is enough to deal with more than two photons meeting.
Can discussion meets address-mapping schemes after shunting scheme is determined.Meet in species counting rate it is maximum up to megahertz
Hereby, once test and be possible to carry out dozens of hour, the bit wide of counter can guarantee that enough to great talent and will not overflow, therefore select
With 64bit bit wides.The species that meets of 32 passages shares 232- 1, but wherein have it is many it is invalid meet, corresponding to a photon
Can only at most have one in passage while there is meeting for pulse to be defined as effectively meeting, thus a photon have 6 kinds may, it is necessary to
3bit is encoded, 8 common 24bit of photon.24bit address widths, 64bit data widths, common 1Gbit spaces, so big storage
Space requirement, DDR are preferably to select.
Block RAM do not have 1Gbit memory space, therefore the address-mapping schemes of single photon and two photons require ground
Location width is as far as possible small, and address is divided into two parts, and corresponding two photons, it is that a photon only needs to know for which photon, which
Individual two information of passage, photon information account for 3bit, and channel information accounts for 2bit, photon 5bit, two common 10bit of photon, such as
Fruit is that single photon meets, then two photon informations are the same.
In the embodiment of the present invention, because fpga chip employs the logical construction as shown in Fig. 3 (b), it is therefore possible to use
The predetermined way change Block RAM's meets address-mapping schemes.It is it will be understood by those skilled in the art that described predetermined
Mode can be this area usual manner.
The such scheme of the embodiment of the present invention, mainly obtain following beneficial effect：
1) DDR Large Copacity allows counts simultaneously to more meeting species.
2) shunting mechanism solves the problems, such as that DDR read or write speeds are inadequate, improves the incident rate for meeting system.
3) generation of double inhibition random signals is capable of in the introducing of pulse shaping and synchronised clock.
4) pulse delay can be with dynamic regulation, and as a result of FPGA I/O resource, degree of regulation is up to tens psecs, line
Property degree is good.It is consistent that dynamic regulation solves the problems, such as that the delay of input signal may not ensure every time.
5) synchronised clock can dynamic phase shift, introduce scan mechanism so that in the case of Single-pass count distribution,
Extrapolated can meet the correctness of result, better than prior art must by meet known to test signal meet result whether with advance
Phase consistent scheme.
6) when carrying out counting statistics, coincidence counting can be read, as long as read-write speed would not cause in DDR bandwidth
Counting loss.
7) PC can learn working state of system according to status word, then by control word de-regulation systematic parameter, make work
Process automation, while add system robustness.
8) it is reconfigurable to meet logic, therefore in system speed, capacity permissible range, can be applied to difference and meet reality
Test.
9) structure is portable high, the SPARTAN of XILINX companies, VIRTEX, and the Series FPGA such as KINTEX supports this
The structure of invention.
The foregoing is only a preferred embodiment of the present invention, but protection scope of the present invention be not limited thereto,
Any one skilled in the art is in the technical scope of present disclosure, the change or replacement that can readily occur in,
It should all be included within the scope of the present invention.Therefore, protection scope of the present invention should be with the protection model of claims
Enclose and be defined.
Claims (5)
- A kind of 1. multi-photon coincidence counting device based on PLD, it is characterised in that including：Fpga chip, DDR with PC；Wherein：The fpga chip, for by the N received roads electric pulse carries out delay adjustment successively, integer operates, sample, meet and patrol Collect and be stored in after judging in corresponding FIFO, then the counter by being connected with corresponding FIFO carries out coincidence counting and operated；It is above-mentioned to adopt The trigger condition of sample is the clock signal of fpga chip internal clocking management module output；The DDR is controlled by the MCB in fpga chip, for storing the coincidence counting of corresponding counter；The PC, for reading the coincidence counting inside DDR and fpga chip in Block RAM and being post-processedWherein, the fpga chip includes：Delay unit, pulse shaping unit, sample register, meet logic judgment module, Clock management module, Block RAM FIFO and the first counter, DDR FIFO and the second counter, Block RAM, WISHBONE buses and MCB；Wherein：The delay unit, for carrying out delay adjustment to the N roads electric pulse received so that N roads electric pulse is perfectly aligned；The pulse shaping unit, it is burst pulse for the N roads electric pulse after alignment to be carried out into integer；The Clock management module, for exporting corresponding clock signal conduct after the synchronised clock of laser offer is received The trigger condition of sampling；The sample register, for storing sampled result；The logic judgment module that meets has diverter function, for being carried out successively to sampled result according to predetermined judgment mode Meet logic judgment, and address of cache will be met accordingly according to judged result and sent to Block RAM FIFO or DDR FIFO；Specially：Meet logic judgment module according to predetermined judgment mode by counting rate it is high meet species address send to Block RAM FIFO, remaining is met into species address and sent to DDR FIFO；First counter is connected with Block RAM FIFO, and second counter is connected with DDR FIFO, two countings Device is used to coincidence counting；The count results of first counter are stored in Block RAM, the counting knot of the second counter Fruit is stored in DDR by MCB；The WISHBONE buses are connected by USB interface with PC, for reading and writing the data in Block RAM and DDR, Yi Jixiang Delay unit is with writing control word and reading state word in Clock management module.
- A kind of 2. multi-photon coincidence counting device based on PLD according to claim 1, it is characterised in that Delay adjustment and use scan mechanism, its step is as follows：The first step, the phase of Clock management module is adjusted to minimum；Second step, Clock management module often increase by a unit of phase, and the single channel that all passages are carried out with certain time counts, when Whether phase reaches maximum, because the distribution of counting reflects the waveform of pulse, you can learn all pulses all in scanning range It is interior；If not, then it represents that delay exceeds dynamic regulation scope, after manually plus-minus line length again since the first step up to all arteries and veins Punching is all in scanning range；3rd step, regulation delay unit align all pulse centers to the maximum pulse center of delay, and the center is defined as arteries and veins Rush center；4th step, Clock management module is adjusted by clock sampling edge alignment pulse center.
- A kind of 3. multi-photon coincidence counting device based on PLD according to claim 1, it is characterised in thatBlock RAM and MCB include dual-port, and one of port uses for counter, and another port passes through for PC WISHBONE bus access；Block RAM two ports can not carry out write operation, MCB two ends to same address simultaneously The shared bandwidth of mouth, i.e. two port data rates add up the bandwidth no more than DDR.
- A kind of 4. multi-photon coincidence counting device based on PLD according to claim 1, it is characterised in thatDelay unit, Clock management module, and Block RAM FIFO and DDR FIFO are equipped with status word, and PC passes through state Word obtains current system working condition；It includes：Clock exception, Block RAM FIFO or DDR FIFO write full when in sync, PC can prompt error message；Afterwards, PC, which attempts to restart automatically, adopts number, adopts several processes and terminates, data are automatically saved in PC；PC to delay unit and Clock management module also by writing control word to control delay unit and Clock management module Working method；It includes：Control word is write to delay unit to control the delay adjustment process of electric pulse；To Clock management module Control word is write to adjust dynamic dephasing processes.
- A kind of 5. multi-photon coincidence counting device based on PLD according to claim 1, it is characterised in that Also include：Using predetermined way change described in meet logic judgment module meet address-mapping schemes.
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| CN107656881A (en) * | 2017-09-13 | 2018-02-02 | 中国科学院半导体研究所 | Data storage transit system based on FPGA |
| CN108280437B (en) * | 2018-01-30 | 2021-06-15 | 四川新先达测控技术有限公司 | Pulse signal processing method and device and user terminal |
| CN109324542B (en) * | 2018-09-12 | 2021-03-09 | 中国原子能科学研究院 | Special pulse signal processor for neutron multiplicity measurement |
| CN109272099B (en) * | 2018-09-19 | 2022-07-15 | 上海星秒光电科技有限公司 | Coincidence counting management method and device |
| CN109238480B (en) * | 2018-10-19 | 2024-02-23 | 中国科学技术大学 | Multiphoton coincidence counting method and device |
| CN109253808B (en) * | 2018-10-26 | 2020-04-21 | 上海星秒光电科技有限公司 | Time coincidence counting system, method and device |
| CN110175095B (en) * | 2019-04-28 | 2023-09-22 | 南京大学 | Man-machine interaction type multifunctional FPGA coincidence measurement system and measurement method thereof |
| CN111143273B (en) * | 2019-11-12 | 2023-07-04 | 广东高云半导体科技股份有限公司 | System on chip |
| CN112069095B (en) * | 2020-09-09 | 2022-01-28 | 北京锐马视讯科技有限公司 | DDR3 read-write transmission method and device |
| CN112486247B (en) * | 2020-11-13 | 2022-07-05 | 深圳市贝斯达医疗股份有限公司 | Coincidence controller, realization method thereof and positron emission tomography system |
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