CN109324542B - Special pulse signal processor for neutron multiplicity measurement - Google Patents

Abstract

The invention belongs to the technical field of non-destructive analysis of nuclear materials, and in particular relates to a special pulse signal processor for neutron multiplicity measurement, comprising an interface board between an FPGA and a peripheral circuit, an FPGA signal processing board connected with a single-chip microcomputer data display and a high-voltage power supply board, and an FPGA signal processing board connected with the single-chip microcomputer. The touch screen connected with the data display and the high-voltage power supply board also includes a DC power supply connected with the data display of the single-chip microcomputer, the high-voltage power supply board and the touch screen; by programming the FPGA signal processing board, three counter circuits including the first counter are obtained; each counter The circuit records and stores one neutron pulse signal; one of the counter circuits can also process the multiplicity pulse signal, that is, the coincidence count and multiplicity analysis result of the neutron pulse signal recorded by the counter circuit are given.

Description

A special pulse signal processor for neutron multiplicity measurement

technical field

The invention belongs to the technical field of nondestructive analysis of nuclear materials, and in particular relates to a special pulse signal processor for neutron multiplicity measurement.

Background technique

The neutron multiplicity pulse signal processor is mainly used for non-destructive analysis of nuclear materials, and is an important equipment for the measurement of special fissionable materials. The programmable logic array (FPGA) is used to realize the rapid processing and analysis of the neutron coincidence pulse signal, which can provide high-voltage and low-voltage power supply for the measuring equipment, can communicate with the computer through the RS-422 interface, and can complete the whole process through the computer software. Measurement and analysis work.

SUMMARY OF THE INVENTION

In order to realize the rapid processing and analysis of the neutron coincident pulse signal, the research work of this device is carried out.

In order to achieve the above purpose, the technical solution adopted in the present invention is a special pulse signal processor for neutron multiplicity measurement, which includes an FPGA signal processing board connected with the interface board of the FPGA and the peripheral circuit, the single-chip data display and the high-voltage power supply board, and is connected with the FPGA signal processing board. The touch screen connected with the single-chip data display and the high-voltage power supply board also includes a DC power supply connected with the single-chip data display, the high-voltage power supply board and the touch screen; by programming the FPGA signal processing board, three channels including the first counter are obtained. Counter circuit; each of the counter circuits records and stores one neutron pulse signal; one of the counter circuits can also process multiple pulse signals, that is, to give the neutron pulse signal recorded by the counter circuit The A, R+A, R and multiplicity analysis results of ;

The R+A is true coincidence count + accidental coincidence count, which refers to the number and frequency of pulses in the true coincidence count + occasional coincidence count time window, and the true coincidence count + occasional coincidence count time window refers to after the trigger pulse arrives. , a second time after the delay of the first time;

The A is the accidental coincidence count, which refers to the number and frequency of pulses within the accidental coincidence count time window, and the accidental coincidence count time window refers to the third delay after the true coincidence count + the accidental coincidence count time window. the fourth time after the time;

The R is a true coincidence count, obtained by subtracting the A from the R+A.

further,

The three-way counter circuits in the FPGA signal processing board are connected to the neutron pulse signal through the interface board of the FPGA and the peripheral circuit, and the interface board of the FPGA and the peripheral circuit is used to complete the neutralization of the input. The sub-pulse signal is processed and converted into a level signal and A/D conversion that the FPGA signal processing board can receive; the interface board between the FPGA and the peripheral circuit is also provided with an RS-422 interface, through the RS-422 interface. The 422 interface transmits the record of the neutron pulse signal in the counter circuit and the analysis results of the A, R+A, R and multiplicity of the neutron pulse signal to an external computer.

further,

The single-chip data display and high-voltage power supply board are used for receiving the FPGA analysis results, and realizing the display and output of data through the touch screen, while providing high-voltage power supply for the compliance measurement device; the compliance measurement device is used to provide the neutron devices for pulsing signals;

The touch screen is used to cooperate with the FPGA signal processing board to realize data display and to control the FPGA signal processing board to start and stop measurement;

The DC power supply can provide DC currents of 5V and 24V.

further,

By programming the FPGA signal processing board, a shift register sequence and a second counter are also connected in the counter circuit that realizes the multiplicity pulse signal processing, and the neutron pulse is realized by the shift register sequence. For signal recording and storage, the R+A and A are recorded and counted through the second counter.

further,

By programming the FPGA signal processing board, 256 storage locations allocated for the R+A and A are also connected in the counter circuit that realizes the multiplexed pulse signal processing, and each of the R+ The values of A and A are used as the address of the storage location. If the R+A and A are between 1 and 254, then each of the R+A and A is recorded in one of the storage locations; If the R+A and A are greater than or equal to 255, then the R+A is all recorded in the 255th storage location for storing the R+A, and the A is all recorded in the 255th storage location. in the storage location of the A.

further,

In the internal control software of the FPGA signal processing board, two arrays are established for the 256 storage locations allocated by the R+A and A respectively, and the value of each of the R+A and A is used as the address, and the The content in the storage location corresponding to the address can be incremented by 1;

The two arrays are cleared when the dedicated pulse signal processor for neutron multiplicity measurement is initialized;

When performing the coincidence pulse signal processing and the multiplicity pulse signal processing on the neutron pulse signal, the FPGA control unit in the FPGA signal processing board needs to accumulate the R+A and A.

further,

After reaching a predetermined measurement time, the FPGA control unit in the FPGA signal processing board reads the stored records of the three groups of the neutron pulse signals, and calculates a group of the multiplicity pulse signal processing during this period the R+A, A, R of the neutron pulse signal, and send the final measurement data to the computer after the entire measurement time, including T, A, R+A, R, and multiplicity measurements result;

The T refers to the total value in the first counter in the counter circuit that implements the multiplicity of pulse signal processing, and is the sum of the pulse counts input during a period of measurement time;

The multiplicity measurement result refers to the data in the two sets of the arrays established in the internal control software of the FPGA signal processing board.

further,

The FPGA control unit can receive the control command and parameter setting command sent by the computer, and send the measurement and calculation results to the computer according to the specified data format; the FPGA control unit controls the high voltage through the digital potentiometer, and simultaneously Use ADC to read back the analog signal that becomes 0-5V after voltage division.

further,

Also includes a chassis, the chassis includes BNC, indicator lights, switches, input and output interfaces, the chassis is used to fix and protect the FPGA signal processing board, the interface board between the FPGA and the peripheral circuit, the single-chip data display and the high-voltage power supply board, Touchpad, DC power supply and fixed input and output connection plug-ins, while preventing external electromagnetic interference.

The beneficial effects of the present invention are:

1. It can quickly record the total count of three random neutron pulse signals, and store it according to the preset measurement time. After the measurement is completed, the data and other calculation results need to be sent to the computer through the RS-422 interface.

2. It can analyze and process one of the three random neutron pulse signals, and can give true coincidence count (R), true coincidence count + accidental coincidence count (R+A), accidental coincidence count (A), and multiplicity analysis results.

Description of drawings

Fig. 1 is the realization principle block diagram of a kind of special-purpose pulse signal processor for neutron multiplicity measurement described in the specific embodiment of the present invention;

2 is a schematic diagram of a specific implementation method of a special pulse signal processor for neutron multiplicity measurement described in the specific embodiments of the present invention;

Fig. 3 is the schematic diagram of the algorithm of A, R+A, R of the neutron pulse signal described in the specific embodiment of the present invention;

4 is an internal circuit board layout diagram of the pulse signal processor dedicated to neutron multiplicity measurement described in the specific embodiments of the present invention;

5 is a schematic diagram of a device data acquisition interface of the device data acquisition and parameter setting software described in the specific embodiments of the present invention;

6 is a schematic diagram of a device parameter setting interface of the device data acquisition and parameter setting software described in the specific embodiment of the present invention.

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and embodiments. A special pulse signal processor (referred to as processor) for neutron multiplicity measurement provided by the present invention includes 6 parts:

1. FPGA signal processing board: mainly completes the storage and processing of the input neutron pulse signal, and sends the analysis results to the computer and single-chip microcomputer;

2. The interface board between FPGA and peripheral circuits: It mainly completes the processing of the input neutron pulse signal, converts it into a level signal that the FPGA can receive, and realizes the functions of RS-422 and A/D conversion of the FPGA;

3. Single-chip data display and high-voltage power supply board: mainly used to receive FPGA analysis results, and realize data display and output through the touch screen, as well as A/D conversion function, and provide high-voltage power supply for the compliance measurement device; (the compliance measurement device consists of multiple It is a device composed of He-3 proportional counter tube, moderator, preamplifier, etc., which can measure neutron-emitting substances and provide neutron signal pulses to the processor. The device needs 5V and high-voltage power supply when working. )

4. Touch screen, used to cooperate with FPGA signal processing board to realize data display and control FPGA signal processing board to start and stop measurement, etc.;

5. DC power supply: connected to the interface board of FPGA and peripheral circuits, single-chip data display and high-voltage power supply board, FPGA signal processing board, and touch screen, providing +5V and 24V DC current;

6. Chassis: including BNC, indicator lights, switches, input and output interfaces, the chassis is used to fix and protect the FPGA signal processing board, the interface board of the FPGA and peripheral circuits, the single-chip data display and high-voltage power supply board, touch panel, DC power supply and fixed Input and output connection plug-ins, while preventing external electromagnetic interference.

In addition, it also includes a temperature and humidity sensor connected to the FPGA control unit in the FPGA signal processing board.

The special pulse signal processor for neutron multiplicity measurement provided by the present invention adopts the V6130T FPGA produced by Xilinx Company (the chip is taken as an embodiment in the following description), and the chip realizes the rapid processing of neutron pulse signals. , the input pulse is TTL pulse, the pulse arrival time is random, the maximum input pulse frequency is designed to be 10 ⁷ Hz, the minimum pulse width is 20 nanoseconds, and the minimum interval between adjacent pulses is 30 nanoseconds. The FPGA system uses a 250MHz crystal oscillator as the internal system clock. The realization principle block diagram of the system is shown in Fig. 1. The specific implementation method inside the system is shown in Figure 2.

The FPGA signal processing board is connected with the interface board of the FPGA and the peripheral circuit, the data display of the single-chip microcomputer and the high-voltage power supply board, and the touch screen is connected with the data display of the single-chip microcomputer and the high-voltage power supply board;

As shown in Figure 1, by programming the FPGA signal processing board, three counter circuits including a first counter are obtained; each counter circuit performs pulse signal processing on a random neutron pulse signal, that is, the neutron pulse signal Recording and storage (coincidence pulse signal processing is mainly to analyze neutron pulses with time correlation, because spontaneous fission and induced fission can emit two or more neutrons at the same time, these neutrons are correlated in time) ;

One of the counter circuits can also perform multiplicity pulse signal processing, that is, to give the A, R+A, R and multiplicity analysis results of the neutron pulse signal recorded by the counter circuit. (The main function of the multiplicity pulse signal processing device is to analyze the time distribution of the neutron pulse signal. The specific method is to use the shift register sequence to realize the storage of the pulse signal, and use the counter to realize the recording of the pulse in the time window. When a pulse arrives, a trigger is realized, and the number and frequency of pulses in the R+A and A time windows at the trigger time are recorded, and finally the results that conform to the count and multiplicity distribution can be obtained.)

About the algorithm of A, R+A, R of the neutron pulse signal (that is, the calculation method of the coincidence count, as shown in Figure 3):

R+A is true coincidence count + accidental coincidence count, which refers to the number and frequency of pulses in the true coincidence count + accidental coincidence count time window, and the true coincidence count + accidental coincidence count time window refers to the trigger pulse (t= 0 time) arrives and the second time after the delay of the first time; the first time is called the pre-delay time, which is adjustable from 0 to 7.5 microseconds. In this embodiment, the first time (P in FIG. 3 ) The duration is 4 microseconds; the second time is called the first gate width, and is adjustable from 0 to 256 microseconds. In this embodiment, the duration of the second time is 256 microseconds;

A is the accidental coincidence count, which refers to the number and frequency of pulses within the accidental coincidence count time window; the accidental coincidence count time window refers to the fourth time after the true coincidence count + the third time delay after the accidental coincidence count time window time, the third time is called the long delay time, and is adjustable from 0 to 1024 microseconds. In this embodiment, the duration of the third time is 1024 microseconds; the fourth time is called the second gate width, and is adjustable from 0 to 256 microseconds. , the duration of the fourth time in this embodiment is 256 microseconds;

R is the true coincidence count, obtained by subtracting A from R+A.

When each pulse comes, calculate the value of R+A and A, and accumulate these two data. After analyzing one pulse as described above, analyze the next pulse in the same manner until all pulses have been analyzed. After the system reaches a preset time (such as 1000 seconds), it needs to calculate the values of R+A, A, R during this period.

About the multiplicity calculation method:

Multiplicity uses the values of R+A and A as addresses, and each of R+A and A has 256 channels. If the number of recorded pulses is between 1 and 254, they are recorded in each track respectively, and if the number of pulses is greater than or equal to 255, they are all recorded in the 255th track. The specific implementation is as follows:

By programming the FPGA signal processing board, the shift register sequence and the second counter in the FPGA signal processing board are also connected in the counter circuit (see the circuit including the counter 1 in FIG. 1 ) that realizes the multiplicity of pulse signal processing. The register sequence realizes the recording and storage of the neutron pulse signal. By programming the FPGA signal processing board, the second counter realizes the recording and statistics of R+A and A, and finally the result conforming to the counting and multiplicity distribution can be obtained.

By programming the FPGA signal processing board, 256 storage locations allocated for R+A and A are also connected in the counter circuit that realizes multiplexed pulse signal processing, and the value of each R+A and A is used as the address of the storage location. , if R+A, A is between 1-254, then each R+A, A is recorded in a storage location; if R+A, A is greater than or equal to 255, then R+A is all recorded in the 255th Among the storage locations for storing R+A, A is all recorded in the 255th storage location for storing A.

In addition, for the multiplicity calculation method, in the internal control software of the FPGA signal processing board, two arrays are established for the 256 storage locations allocated by R+A and A respectively, and the value of each R+A and A is used as the address. Just add 1 to the content in the storage location corresponding to the address; for example: the R+A array is represented by R_A[i], and the A array is represented by A[i], when a trigger pulse arrives, if this When the number of pulses in the R+A window is 5, and the number of pulses in the A window is 2, then add 1 to the value in the array R_A[5], and add 1 to the value in the array A[2].

These two arrays are cleared when the special pulse signal processor for neutron multiplicity measurement is initialized;

When processing the neutron pulse signal according to the pulse signal and the multiplicity pulse signal, the FPGA control unit in the FPGA signal processing board should accumulate R+A and A.

After reaching a predetermined measurement time, such as 1 second, the FPGA control unit in the FPGA signal processing board reads the stored records of three groups of random neutron pulse signals (ie, the number of pulses), and calculates the multiplicity pulse during this period. Signal processing of R+A, A, R of a group of neutron pulse signals, and send the final measurement data to the computer after the entire measurement time, including T, A, R+A, R, and multiplicity measurement results .

in,

T is the total value in the first counter in the counter circuit that realizes the multiplicity of pulse signal processing, and is the sum of the pulse counts input in a period of measurement time; (the counter circuit that realizes the multiplicity of pulse signal processing is included in FIG. The circuit of the counter 1, the first counter is the counter 1 in Figure 1)

The multiplicity measurement result refers to the data in the two sets of arrays established in the internal control software of the FPGA signal processing board, that is, the data in the arrays R_A[i] and A[i];

where the relationship between R+A and R_A[i] is

where the relationship between A and A[i] is

R=(R+A)-A;

R[i]=R_A[i]-A[i].

The three-way counter circuit in the FPGA signal processing board is connected to the neutron pulse signal through the interface board of the FPGA and the peripheral circuit. The interface board of the FPGA and the peripheral circuit is used to complete the processing of the input neutron pulse signal and transform it into an FPGA signal processing board. The level signal that can be received (that is, the externally input pulse signal is shaped by the shaping circuit to form a pulse signal of the same width) and A/D conversion; the interface board between the FPGA and the peripheral circuit is also equipped with RS -422 interface, the neutron pulse signal record in the counter circuit and the analysis results of A, R+A, R and multiplicity of the neutron pulse signal are sent to the external computer through the RS-422 interface.

The FPGA control unit in the FPGA signal processing board can receive the control commands and parameter setting commands sent by the computer, and send the measurement and calculation results to the computer according to the specified data format (in this embodiment, the corresponding device data acquisition is made by using VB. and parameter setting software, see Figures 5 and 6); the FPGA control unit controls the high voltage through a digital potentiometer (specifically, it is realized by controlling the high voltage module in Figure 1), and at the same time, the ADC is used to read back the divided voltage and become 0-5V analog signal.

The device described in the present invention is not limited to the embodiments described in the specific embodiments, and those skilled in the art can obtain other embodiments according to the technical solutions of the present invention, which also belong to the technical innovation scope of the present invention.

Claims (4)

1. A special pulse signal processor for neutron multiplicity measurement is characterized in that: the system comprises an FPGA signal processing board, a touch screen and a direct current power supply, wherein the FPGA signal processing board is connected with an interface board of an FPGA and a peripheral circuit, a singlechip data display and high-voltage power supply board, the touch screen is connected with the singlechip data display and high-voltage power supply board, and the direct current power supply is connected with the singlechip data display and high-voltage power supply board and the touch screen; programming the FPGA signal processing board to obtain three counter circuits including a first counter; each path of counter circuit carries out coincidence pulse signal processing on one path of neutron pulse signal, wherein the coincidence pulse signal processing refers to recording and storing the neutron pulse signal; one path of the counter circuit can also process multiple pulse signals, namely A, R + A, R of the neutron pulse signals recorded by the counter circuit and analysis results of the multiple are given;

the R + A is a true coincidence count and an accidental coincidence count, and refers to the number and frequency of pulses in a time window of the true coincidence count and the accidental coincidence count, and the time window of the true coincidence count and the accidental coincidence count refers to a second time after the trigger pulse arrives and a delay of a first time;

the A is an accidental coincidence count which refers to the number and frequency of pulses in an accidental coincidence counting time window, and the accidental coincidence counting time window refers to the fourth time after the third time delayed after the true coincidence count + the accidental coincidence counting time window;

the R is a true coincidence count and is obtained by subtracting the A from the R + A;

the three counter circuits in the FPGA signal processing board are connected with the neutron pulse signal through an interface board of the FPGA and a peripheral circuit, and the interface board of the FPGA and the peripheral circuit is used for processing the input neutron pulse signal and converting the neutron pulse signal into a level signal which can be received by the FPGA signal processing board and A/D conversion; an RS-422 interface is further arranged on an interface board between the FPGA and a peripheral circuit, and the neutron pulse signal record in the counter circuit, the A, R + A, R of the neutron pulse signal and the analysis result of the multiplicity are sent to an external computer through the RS-422 interface;

programming the FPGA signal processing board to enable a shift register sequence and a second counter to be further connected in the counter circuit for realizing the processing of the multiple pulse signals, realizing the recording and storage of the neutron pulse signals through the shift register sequence, and realizing the recording and statistics of the R + A, A through the second counter;

by programming the FPGA signal processing board to connect 256 storage positions respectively allocated to the R + A, A in the counter circuit for realizing the multiple pulse signal processing, taking the value of each R + A, A as the address of the storage position, and if the R + A, A is between 1-254, recording each R + A, A in one storage position respectively; if the R + A, A is greater than or equal to 255, then the R + As are all posted in the 255 th storage location for storing the R + As, and the As are all posted in the 255 th storage location for storing the As;

in the internal control software of the FPGA signal processing board, two arrays are established aiming at 256 storage positions respectively allocated to the R + A, A, the value of each R + A, A is used as an address, and the content in the storage position corresponding to the address is added with 1; the R + A array is represented by R _ A [ i ], and the A array is represented by A [ i ];

the two arrays are cleared when the special pulse signal processor for the neutron multiplicity measurement is initialized;

when the coincidence pulse signal processing and the multiple pulse signal processing are carried out on the neutron pulse signals, the FPGA control unit in the FPGA signal processing board accumulates the R + A, A;

after reaching the preset measurement time, reading the record of three stored groups of neutron pulse signals by an FPGA control unit in the FPGA signal processing board, calculating the R + A, A, R of a group of neutron pulse signals subjected to the multiple pulse signal processing in the period, and sending final measurement data including T, A, R + A, R and multiple measurement results to the computer after the whole measurement time is over;

the T is the total count value in the first counter in the counter circuit for realizing the processing of the multiple pulse signals, and is the sum of the pulse counts input in a measuring time;

the result of the measurement of the multiplicity refers to the data in the two groups of arrays established in the internal control software of the FPGA signal processing board, namely the data in the R _ A [ i ] and the A [ i ];

wherein R + A and R _ A [ i ]]Is in the relationship of

Wherein A and A [ i ]]Is in the relationship of

R＝(R+A)-A；

R[i]＝R_A[i]-A[i]。

2. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein:

the singlechip data display and high-voltage power supply board is used for receiving an FPGA analysis result, displaying and outputting data through the touch screen and providing a high-voltage power supply for the coincidence measurement device; the coincidence measurement device is a device for providing the neutron pulse signal;

the touch screen is used for being matched with the FPGA signal processing board to realize data display and controlling the FPGA signal processing board to start and stop measurement;

the DC power supply can provide +5V and 24V DC current.

3. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein: the FPGA control unit can receive a control command and a parameter setting command sent by the computer and send a measurement and calculation result to the computer according to a specified data format; the FPGA control unit controls high voltage through a digital potentiometer, and simultaneously adopts ADC to read back an analog signal which is changed into 0-5V after voltage division.

4. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein: the intelligent FPGA signal processing device is characterized by further comprising a case, wherein the case comprises a BNC, an indicator lamp, a switch and an input/output interface, and is used for fixing and protecting the FPGA signal processing board, an interface board of the FPGA and a peripheral circuit, a single chip microcomputer data display and high-voltage power supply board, a touch pad, a direct-current power supply and a fixed input/output connecting plug-in unit and preventing external electromagnetic interference.

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