CN109324542A - A kind of neutron multiplicity measurement Special pulse signal processor - Google Patents
A kind of neutron multiplicity measurement Special pulse signal processor Download PDFInfo
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Abstract
The invention belongs to nuclear material nondestructive analysis technical fields, Special pulse signal processor is measured more particularly to a kind of neutron multiplicity, it is shown including FPGA with the interface board of peripheral circuit, single-chip data and FPGA signal-processing board that high-voltage electricity source plate is connected, it is shown with single-chip data and touch screen that high-voltage electricity source plate is connected, further includes being shown with single-chip data and DC power supply that high-voltage electricity source plate, touch screen are connected；By being programmed to FPGA signal-processing board, the counter circuit that three tunnels include the first counter is obtained；Every road counter circuit carries out recording and storage to neutron pulse signal all the way；Wherein counter circuit can also carry out multiplicity pulse signal processing all the way, that is, provide the coincidence counting for the neutron pulse signal that the counter circuit is recorded and the analysis result of multiplicity.
Description
Technical Field
The invention belongs to the technical field of nondestructive analysis of nuclear materials, and particularly relates to a special pulse signal processor for neutron multiplicity measurement.
Background
The neutron multiplicity pulse signal processor is mainly used for nondestructive analysis of nuclear materials and is important equipment for measuring special fissionable materials. The neutron coincidence pulse signal is rapidly processed and analyzed by adopting a programmable logic array (FPGA), a high-voltage power supply and a low-voltage power supply can be provided for measuring equipment, the measuring equipment can communicate with a computer through an RS-422 interface, and all measurement and analysis work can be completed through computer software.
Disclosure of Invention
In order to realize the rapid processing and analysis of neutron coincidence pulse signals, research work of the device is carried out.
In order to achieve the purposes, the technical scheme adopted by the invention is a special pulse signal processor for neutron multiplicity measurement, which comprises an FPGA signal processing board, a touch screen and a direct current power supply, wherein the FPGA signal processing board is connected with an interface board of a peripheral circuit and a singlechip data display and high-voltage power supply board; programming the FPGA signal processing board to obtain three counter circuits including a first counter; each path of the counter circuit records and stores one path of the neutron pulse signals; one path of the counter circuit can also process multiple pulse signals, namely A, R + A, R of the neutron pulse signals recorded by the counter circuit and analysis results of the multiple are given;
the R + A is a true coincidence count and an accidental coincidence count, and refers to the number and frequency of pulses in a time window of the true coincidence count and the accidental coincidence count, and the time window of the true coincidence count and the accidental coincidence count refers to a second time after the trigger pulse arrives and a delay of a first time;
the A is an accidental coincidence count which refers to the number and frequency of pulses in an accidental coincidence counting time window, and the accidental coincidence counting time window refers to the fourth time after the third time delayed after the true coincidence count + the accidental coincidence counting time window;
and the R is a true coincidence count and is obtained by subtracting the A from the R + A.
Further, in the present invention,
the three counter circuits in the FPGA signal processing board are connected with the neutron pulse signal through an interface board of the FPGA and a peripheral circuit, and the interface board of the FPGA and the peripheral circuit is used for processing the input neutron pulse signal and converting the neutron pulse signal into a level signal which can be received by the FPGA signal processing board and A/D conversion; an RS-422 interface is further arranged on an interface board between the FPGA and a peripheral circuit, and the neutron pulse signal record in the counter circuit, the A, R + A, R of the neutron pulse signal and the analysis result of the multiplicity are sent to an external computer through the RS-422 interface.
Further, in the present invention,
the singlechip data display and high-voltage power supply board is used for receiving an FPGA analysis result, displaying and outputting data through the touch screen and providing a high-voltage power supply for the coincidence measurement device; the coincidence measurement device is a device for providing the neutron pulse signal;
the touch screen is used for being matched with the FPGA signal processing board to realize data display and controlling the FPGA signal processing board to start and stop measurement;
the DC power supply can provide 5V and 24V DC current.
Further, in the present invention,
the FPGA signal processing board is programmed to enable a shift register sequence and a second counter to be further connected in the counter circuit for realizing the processing of the multiple pulse signals, the neutron pulse signals are recorded and stored through the shift register sequence, and the R + A, A is recorded and counted through the second counter.
Further, in the present invention,
by programming the FPGA signal processing board to connect 256 storage positions respectively allocated to the R + A, A in the counter circuit for realizing the multiple pulse signal processing, taking the value of each R + A, A as the address of the storage position, and if the R + A, A is between 1-254, recording each R + A, A in one storage position respectively; if the R + A, A is greater than or equal to 255, then the R + As are all posted in the 255 th storage location for storing the R + As and the As are all posted in the 255 th storage location for storing the As.
Further, in the present invention,
in the internal control software of the FPGA signal processing board, two arrays are established aiming at 256 storage positions respectively allocated to the R + A, A, the value of each R + A, A is used as an address, and the content in the storage position corresponding to the address is added by 1;
the two arrays are cleared when the special pulse signal processor for the neutron multiplicity measurement is initialized;
when the coincidence pulse signal processing and the multiple pulse signal processing are performed on the neutron pulse signals, the FPGA control unit in the FPGA signal processing board accumulates the R + A, A.
Further, in the present invention,
after reaching the preset measurement time, reading the record of three stored groups of neutron pulse signals by an FPGA control unit in the FPGA signal processing board, calculating the R + A, A, R of a group of neutron pulse signals subjected to the multiple pulse signal processing in the period, and sending final measurement data including T, A, R + A, R and multiple measurement results to the computer after the whole measurement time is over;
the T is the total count value in the first counter in the counter circuit for realizing the processing of the multiple pulse signals, and is the sum of the pulse counts input in a measuring time;
the result of the measurement of the multiplicity refers to data in two groups of the arrays established in the internal control software of the FPGA signal processing board.
Further, in the present invention,
the FPGA control unit can receive a control command and a parameter setting command sent by the computer and send a measurement and calculation result to the computer according to a specified data format; the FPGA control unit controls high voltage through a digital potentiometer, and simultaneously adopts ADC to read back an analog signal which is changed into 0-5V after voltage division.
Further, in the present invention,
the intelligent FPGA signal processing device is characterized by further comprising a case, wherein the case comprises a BNC, an indicator lamp, a switch and an input/output interface, and is used for fixing and protecting the FPGA signal processing board, an interface board of the FPGA and a peripheral circuit, a single chip microcomputer data display and high-voltage power supply board, a touch pad, a direct-current power supply and a fixed input/output connecting plug-in unit and preventing external electromagnetic interference.
The invention has the beneficial effects that:
1. the total count of three paths of random neutron pulse signals can be rapidly recorded and stored according to preset measuring time, and after the measurement is finished, the data and other calculation results are required to be sent to a computer through an RS-422 interface.
2. One path of the three paths of random neutron pulse signals can be analyzed and processed, and a true coincidence count (R), a true coincidence count + accidental coincidence count (R + A), an accidental coincidence count (A) and a multiple analysis result can be given.
Drawings
Fig. 1 is a functional block diagram of a pulse signal processor dedicated for neutron multiplicity measurement according to an embodiment of the present invention;
fig. 2 is a schematic diagram of an implementation method of a pulse signal processor dedicated for neutron multiplicity measurement according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of an A, R + A, R algorithm for neutron pulse signals, in accordance with an embodiment of the present invention;
FIG. 4 is a layout diagram of an internal circuit board of a pulse signal processor dedicated for neutron multiplicity measurement according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a device data acquisition interface of the device data acquisition and parameter setting software according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a device parameter setting interface of the device data acquisition and parameter setting software according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the figures and examples. The invention provides a special pulse signal processor (processor for short) for neutron multiplicity measurement, which comprises 6 parts:
the FPGA signal processing board: the method mainly completes storage and processing of input neutron pulse signals and sends analysis results to a computer and a single chip microcomputer;
interface board of FPGA and peripheral circuit: the method mainly completes the processing of the input neutron pulse signal, converts the neutron pulse signal into a level signal which can be received by the FPGA, and simultaneously realizes the functions of RS-422, A/D conversion and the like of the FPGA;
3. single chip data display and high voltage power supply board: the device is mainly used for receiving FPGA analysis results, realizing data display and output through a touch screen, realizing an A/D conversion function and simultaneously providing a high-voltage power supply for a coincidence measurement device; (coincidence measuring device is composed of a plurality of He-3 proportional counter tubes, a slowing body, a preamplifier, etc., can measure the substance emitting neutrons, provides neutron signal pulse for the processor, and needs 5V and high voltage power supply when working)
4. The touch screen is used for being matched with the FPGA signal processing board to realize data display, controlling the FPGA signal processing board to start and stop measurement and the like;
5. a direct-current power supply: the interface board, the singlechip data display and high-voltage power supply board, the FPGA signal processing board and the touch screen are connected with the FPGA and the peripheral circuit to provide +5V and 24V direct current;
6. a case: the intelligent protection box comprises a BNC, an indicator light, a switch and an input/output interface, wherein the case is used for fixing and protecting an FPGA signal processing board, an interface board of the FPGA and a peripheral circuit, a single chip microcomputer data display and high-voltage power supply board, a touch pad, a direct-current power supply and a fixed input/output connection plug-in unit, and meanwhile, external electromagnetic interference is prevented.
In addition, the temperature and humidity sensor is connected with an FPGA control unit in the FPGA signal processing board.
The special pulse signal processor for neutron multiplicity measurement provided by the invention adopts a V6130T type FPGA (the chip is taken as an embodiment in the following description) produced by Xilinx company, the chip is used for realizing the rapid processing of neutron pulse signals, the input pulses are TTL pulses, the arrival time of the pulses is random, and the highest input pulse frequency is designed to be 107Hz, the minimum pulse width is 20 nanoseconds, the minimum interval of adjacent pulses is 30 nanoseconds, and the FPGA system uses a 250MHz crystal oscillator as an internal system clock. The implementation block diagram of the system is shown in fig. 1. The specific implementation method inside the system is shown in fig. 2.
The FPGA signal processing board is connected with an interface board of the FPGA and peripheral circuits, a singlechip data display and high-voltage power supply board, and the touch screen is connected with the singlechip data display and high-voltage power supply board;
as shown in fig. 1, three counter circuits including a first counter are obtained by programming an FPGA signal processing board; each counter circuit carries out coincidence pulse signal processing on one random neutron pulse signal, namely, the neutron pulse signal is recorded and stored (the coincidence pulse signal processing mainly analyzes neutron pulses with time correlation, and because spontaneous fission and induced fission can simultaneously emit two or more neutrons which are correlated in time);
one of the counter circuits can also process multiple pulse signals, namely A, R + A, R of the neutron pulse signals recorded by the counter circuit and analysis results of the multiple are given. (the main function of the multiple pulse signal processing device is to analyze the time distribution of the neutron pulse signal. the specific method is to adopt a shift register sequence to realize the storage of the pulse signal, adopt a counter to realize the recording of the pulse in a time window, realize the triggering once when the pulse arrives, record the number and the frequency of the pulse in R + A and A time windows at the triggering moment, and finally obtain the result which accords with the counting and the multiple distribution.)
Algorithm A, R + A, R for neutron pulse signals (i.e. coincidence counting method, as shown in fig. 3):
r + a is true coincidence count + accidental coincidence count, which refers to the number and frequency of pulses in a time window of true coincidence count + accidental coincidence count, and the time window of true coincidence count + accidental coincidence count refers to the second time after the delay of the first time after the trigger pulse (time t ═ 0 in fig. 3) arrives; the first time is called pre-delay time, and is adjustable from 0 to 7.5 microseconds, and the duration of the first time (P in fig. 3) in this embodiment is 4 microseconds; the second time is called as a first gate width, and is adjustable from 0 microsecond to 256 microseconds, and the duration of the second time is 256 microseconds in the embodiment;
a is accidental coincidence counting, which means the number and frequency of pulses in an accidental coincidence counting time window; the accidental coincidence counting time window is the fourth time after the third time delayed after the real coincidence counting + the accidental coincidence counting time window, the third time is called long delay time, the time is adjustable from 0 to 1024 microseconds, and the duration of the third time is 1024 microseconds in the embodiment; the fourth time is called a second gate width, and is adjustable from 0 to 256 microseconds, wherein the duration of the fourth time is 256 microseconds in the embodiment;
r is the true coincidence count obtained by subtracting a from R + a.
The R + a, a value is calculated at the arrival of each pulse and the two data are accumulated. After one pulse has been analyzed as described above, the next pulse is analyzed again in the same manner until all pulses have been analyzed. After the system reaches a preset time (such as 1000 seconds), the values of R + A, A and R in the period are calculated.
Regarding the multiplicity calculation method:
the multiplicity is that the values of R + A and A are used as addresses, and each of R + A and A has 256 channels. If the number of recorded pulses is between 1 and 254, each track is entered, and if the number of pulses is greater than or equal to 255, all the tracks are entered. The specific implementation mode is as follows:
the FPGA signal processing board is programmed to be connected with a shift register sequence and a second counter in the FPGA signal processing board in a counter circuit (see a circuit containing the counter 1 in figure 1) for realizing the processing of the multiple pulse signals, the recording and the storage of the neutron pulse signals are realized through the shift register sequence, the second counter is programmed to realize the recording and the statistics of R + A, A, and finally, a result conforming to the counting and the multiple distribution can be obtained.
By programming the FPGA signal processing board, 256 storage positions respectively allocated to R + A, A are also connected in the counter circuit for realizing the multiple pulse signal processing, the value of each R + A, A is used as the address of the storage position, and if R + A, A is between 1-254, each R + A, A is respectively recorded in one storage position; if R + A, A is greater than or equal to 255, then R + A is all logged into the 255 th storage location for storing R + A and A is all logged into the 255 th storage location for storing A.
In addition, aiming at a multiple calculation method, in internal control software of an FPGA signal processing board, two arrays are established aiming at 256 storage positions respectively distributed by R + A, A, the value of each R + A, A is used as an address, and the content in the storage position corresponding to the address is added by 1; for example: when a trigger pulse comes, if the number of pulses in the R + A window is 5 and the number of pulses in the A window is 2, the value in the array R _ A [5] is added with 1, and the value in the array A [2] is added with 1.
The two arrays are reset when a pulse signal processor special for the neutron multiplicity measurement is initialized;
when the coincidence pulse signal processing and the multiple pulse signal processing are carried out on the neutron pulse signals, the FPGA control unit in the FPGA signal processing board accumulates R + A, A.
After a predetermined measurement time, such as 1 second, is reached, the FPGA control unit in the FPGA signal processing board reads the stored record (i.e., the number of pulses) of the three sets of random neutron pulse signals, calculates R + A, A, R of the set of neutron pulse signals subjected to the multiplicity pulse signal processing during this period, and sends the final measurement data, including T, a, R + a, R, and the measurement results of multiplicity, to the computer after the entire measurement time is over.
Wherein,
t is a total count value in a first counter in a counter circuit that realizes multiple pulse signal processing, and is a sum of pulse counts input over a measurement time; (the counter circuit for realizing the processing of the multiple pulse signals is the circuit comprising the counter 1 in FIG. 1, and the first counter is the counter 1 in FIG. 1)
The result of the measurement of the multiplicity refers to the data in two groups of arrays established in the internal control software of the FPGA signal processing board, namely the data in the arrays R _ A [ i ] and A [ i ];
wherein R + A and R _ A [ i ]]Is in the relationship of
Wherein A and A [ i ]]Is in the relationship of
R＝(R+A)-A；
R[i]＝R_A[i]-A[i]。
The three counter circuits in the FPGA signal processing board are connected with neutron pulse signals through an interface board of the FPGA and a peripheral circuit, and the interface board of the FPGA and the peripheral circuit is used for processing the input neutron pulse signals and converting the neutron pulse signals into level signals which can be received by the FPGA signal processing board (namely, shaping of the externally input pulse signals is realized through a shaping circuit so as to form pulse signals with the same width) and A/D conversion; and an RS-422 interface is also arranged on an interface board of the FPGA and the peripheral circuit, and the neutron pulse signal record in the counter circuit, A, R + A, R of the neutron pulse signal and the analysis result of the multiplicity are sent to an external computer through the RS-422 interface.
The FPGA control unit in the FPGA signal processing board can receive the control command and the parameter setting command sent from the computer, and send the measurement and calculation results to the computer according to the specified data format (in this embodiment, it is implemented by programming corresponding device data acquisition and parameter setting software using VB, see fig. 5 and 6); the FPGA control unit controls high voltage through a digital potentiometer (specifically, the high voltage control module in the figure 1 is controlled), and simultaneously, an ADC is adopted to read back the analog signal which is changed into 0-5V after voltage division.
The device according to the present invention is not limited to the embodiments described in the specific embodiments, and those skilled in the art can derive other embodiments according to the technical solutions of the present invention, and also belong to the technical innovation scope of the present invention.
Claims (9)
1. A special pulse signal processor for neutron multiplicity measurement is characterized in that: the system comprises an FPGA signal processing board, a touch screen and a direct current power supply, wherein the FPGA signal processing board is connected with an interface board of an FPGA and a peripheral circuit, a singlechip data display and high-voltage power supply board, the touch screen is connected with the singlechip data display and high-voltage power supply board, and the direct current power supply is connected with the singlechip data display and high-voltage power supply board and the touch screen; programming the FPGA signal processing board to obtain three counter circuits including a first counter; each path of the counter circuit records and stores one path of the neutron pulse signals; one path of the counter circuit can also process multiple pulse signals, namely A, R + A, R of the neutron pulse signals recorded by the counter circuit and analysis results of the multiple are given;
the R + A is a true coincidence count and an accidental coincidence count, and refers to the number and frequency of pulses in a time window of the true coincidence count and the accidental coincidence count, and the time window of the true coincidence count and the accidental coincidence count refers to a second time after the trigger pulse arrives and a delay of a first time;
the A is an accidental coincidence count which refers to the number and frequency of pulses in an accidental coincidence counting time window, and the accidental coincidence counting time window refers to the fourth time after the third time delayed after the true coincidence count + the accidental coincidence counting time window;
and the R is a true coincidence count and is obtained by subtracting the A from the R + A.
2. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein: the three counter circuits in the FPGA signal processing board are connected with the neutron pulse signal through an interface board of the FPGA and a peripheral circuit, and the interface board of the FPGA and the peripheral circuit is used for processing the input neutron pulse signal and converting the neutron pulse signal into a level signal which can be received by the FPGA signal processing board and A/D conversion; an RS-422 interface is further arranged on an interface board between the FPGA and a peripheral circuit, and the neutron pulse signal record in the counter circuit, the A, R + A, R of the neutron pulse signal and the analysis result of the multiplicity are sent to an external computer through the RS-422 interface.
3. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein:
the singlechip data display and high-voltage power supply board is used for receiving an FPGA analysis result, displaying and outputting data through the touch screen and providing a high-voltage power supply for the coincidence measurement device; the coincidence measurement device is a device for providing the neutron pulse signal;
the touch screen is used for being matched with the FPGA signal processing board to realize data display and controlling the FPGA signal processing board to start and stop measurement;
the DC power supply can provide 5V and 24V DC current.
4. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein: the FPGA signal processing board is programmed to enable a shift register sequence and a second counter to be further connected in the counter circuit for realizing the processing of the multiple pulse signals, the neutron pulse signals are recorded and stored through the shift register sequence, and the R + A, A is recorded and counted through the second counter.
5. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 4, wherein: by programming the FPGA signal processing board to connect 256 storage positions respectively allocated to the R + A, A in the counter circuit for realizing the multiple pulse signal processing, taking the value of each R + A, A as the address of the storage position, and if the R + A, A is between 1-254, recording each R + A, A in one storage position respectively; if the R + A, A is greater than or equal to 255, then the R + As are all posted in the 255 th storage location for storing the R + As and the As are all posted in the 255 th storage location for storing the As.
6. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 5, wherein: in the internal control software of the FPGA signal processing board, two arrays are established aiming at 256 storage positions respectively allocated to the R + A, A, the value of each R + A, A is used as an address, and the content in the storage position corresponding to the address is added by 1;
the two arrays are cleared when the special pulse signal processor for the neutron multiplicity measurement is initialized;
when the coincidence pulse signal processing and the multiple pulse signal processing are performed on the neutron pulse signals, the FPGA control unit in the FPGA signal processing board accumulates the R + A, A.
7. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 6, wherein: after reaching the preset measurement time, reading the record of three stored groups of neutron pulse signals by an FPGA control unit in the FPGA signal processing board, calculating the R + A, A, R of a group of neutron pulse signals subjected to the multiple pulse signal processing in the period, and sending final measurement data including T, A, R + A, R and multiple measurement results to the computer after the whole measurement time is over;
the T is the total count value in the first counter in the counter circuit for realizing the processing of the multiple pulse signals, and is the sum of the pulse counts input in a measuring time;
the result of the measurement of the multiplicity refers to data in two groups of the arrays established in the internal control software of the FPGA signal processing board.
8. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 7, wherein: the FPGA control unit can receive a control command and a parameter setting command sent by the computer and send a measurement and calculation result to the computer according to a specified data format; the FPGA control unit controls high voltage through a digital potentiometer, and simultaneously adopts ADC to read back an analog signal which is changed into 0-5V after voltage division.
9. The pulse signal processor special for neutron multiplicity measurement as claimed in claim 1, wherein: the intelligent FPGA signal processing device is characterized by further comprising a case, wherein the case comprises a BNC, an indicator lamp, a switch and an input/output interface, and is used for fixing and protecting the FPGA signal processing board, an interface board of the FPGA and a peripheral circuit, a single chip microcomputer data display and high-voltage power supply board, a touch pad, a direct-current power supply and a fixed input/output connecting plug-in unit and preventing external electromagnetic interference.
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| CN116299650A (en) * | 2023-05-18 | 2023-06-23 | 中国工程物理研究院材料研究所 | Neutron multiple distribution on-line reconstruction method based on digital acquisition |
| CN116299650B (en) * | 2023-05-18 | 2023-07-25 | 中国工程物理研究院材料研究所 | Neutron multiple distribution on-line reconstruction method based on digital acquisition |
| CN116718626A (en) * | 2023-05-22 | 2023-09-08 | 中国工程物理研究院材料研究所 | Data acquisition and analysis system based on neutron multiple measurement |
| CN116718626B (en) * | 2023-05-22 | 2023-12-29 | 中国工程物理研究院材料研究所 | Data acquisition and analysis system based on neutron multiple measurement |
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