CN107656881A - Data storage transit system based on FPGA - Google Patents
Data storage transit system based on FPGA Download PDFInfo
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- CN107656881A CN107656881A CN201710820767.2A CN201710820767A CN107656881A CN 107656881 A CN107656881 A CN 107656881A CN 201710820767 A CN201710820767 A CN 201710820767A CN 107656881 A CN107656881 A CN 107656881A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
- G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/32—Monitoring with visual or acoustical indication of the functioning of the machine
- G06F11/324—Display of status information
- G06F11/328—Computer systems status display
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0893—Caches characterised by their organisation or structure
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/22—Employing cache memory using specific memory technology
Abstract
Present disclose provides a kind of data storage transit system based on FPGA, including：Data resource interface module (1), the data transmitted for receiving data source；DDR cache interface modules (2), for providing cache interface to the data for passing in and out DDR storage chips；External storage interface module (5), for providing interface to the data for passing in and out external memory storage；DDR buffer control modules (3), it is connected with data resource interface module (1), DDR cache interface modules (2) and external storage interface module (5), for by data resource interface module (1) monitoring data reading state, according to the state by data storage to DDR storage chips or by from the data storage that DDR storage chips are read to external memory storage.The disclosure is simple in construction, requirement on devices is low, cost is cheap, can be widely applied to need the occasion for carrying out big data quantity high speed real-time storage.
Description
Technical field
The present invention relates to data transfer and technical field of memory, more particularly to a kind of data storage of the high speed based on FPGA
Transit system.
Background technology
The transmission of big data and real-time storage are relatively conventional in the scene of high frame per second camera, scientific research is needed to use,
In these application scenarios, the one second speed that can produce data tends to reach hundreds of Mbytes of even greater than 1GB.In order to
High-speed data is stored, data are first often had into computer memory using capture card, internal memory again turns data after being filled with
On the hard disk deposited.The program is disadvantageous in that：It is capable of the data volume size of Coutinuous store every time by available memory size
Limitation.Another kind solves the scheme that data high-speed stores：By external circuit, directly writing data into multiple has SATA3
The hard disk of interface or the hard disk of PCIe interface.The program is disadvantageous in that：Although using multiple hard with high-speed interface
Disk, data rate memory can be per second more than 1GB, but because these high-speed interfaces have verification and retransmission mechanism, can not
Ensure that there is real-time storage speed can be stable at nominal value for it.
Disclosure
(1) technical problems to be solved
Present disclose provides a kind of data storage transit system of the high speed based on FPGA, at least partly to solve above institute
The technical problem of proposition.
(2) technical scheme
According to an aspect of this disclosure, there is provided a kind of data storage transit system based on FPGA, including：Data source
Interface module, the data transmitted for receiving data source；DDR cache interface modules, for the data to passing in and out DDR storage chips
Cache interface is provided；External storage interface module, for providing interface to the data for passing in and out external memory storage；DDR buffer controls
Module, it is connected with data resource interface module, DDR cache interface modules and external storage interface module, for passing through data source
Interface module monitoring data reading state, it will be read according to the state by data storage to DDR storage chips or from DDR storage chips
The data storage taken is to external memory storage；Wherein, data resource interface module, DDR cache interface modules, DDR buffer control modules
And external access interface module is realized based on FPGA.
In the disclosure some embodiments, the DDR buffer control modules include：DDR cachings use control submodule, with
Data resource interface module, DDR cache interface modules, the connection of external storage interface module, read and write pointer, timesharing passes through for realizing
DDR cache interface modules are written and read to DDR buffer control modules.
In the disclosure some embodiments, wherein DDR cachings use control submodule, when data resource interface module has
When data transmit, DDR cache interface modules are write data into；When data resource interface module does not have data to transmit, FIFO is used
Mode data are read by DDR cache interface modules, and the data read are transmitted to external storage interface module.
In the disclosure some embodiments, the DDR buffer control modules also include：Prediction and monitoring submodule, with number
Cache according to source interface module, external storage interface module and DDR and connected using control submodule, counter is realized as inside,
The DDR cache sizes for needing to use for simulation test.
In the disclosure some embodiments, the prediction and monitoring submodule, when data resource interface module has data to transmit
When, increase rolling counters forward；When DDR cachings read data using control module from DDR cache interface modules, counter is reduced
Count, the maximum count that final counter is reached is required buffer memory capacity size.
In the disclosure some embodiments, the prediction and monitoring submodule also use control mould by reading DDR cachings
The pointer that block is read and write to DDR cache interface modules, calculate the service condition of DDR cachings.
In the disclosure some embodiments, LCD display interface modules, prediction and monitoring submodule are connected to, it is included outside
Portion's display driving, for being connected with prediction and monitoring submodule and external display, when DDR is transmitted in prediction and monitoring submodule
When cache prediction value and use value, external display can be controlled to show.
In the disclosure some embodiments, the external display is LCD1602.
In the disclosure some embodiments, the external storage interface module, it is connected to DDR cachings and uses control submodule
And prediction and monitoring submodule, the data read and write interface that external memory storage is provided using control submodule is cached for DDR, for prediction
The state of high-speed interface controller is provided with monitoring submodule, the external memory storage of the external storage interface module connection is big
Capacity memory, its memory capacity are 1T-4T.
In the disclosure some embodiments, data resource interface module includes optical fiber, camera link and FPGA I/O Parallel three
Kind of interface, any one interface use by the toggle switch selection of FPGA development boards, by Data Integration into uniformly and line number
According to stream, and produce corresponding data valid signal.
(3) beneficial effect
It can be seen from the above technical proposal that the data storage transit system of high speed of the disclosure based on FPGA at least has
One of following beneficial effect：
(1) stored by using DDR as caching, real-time stabilization can be carried out to high-speed data and transmit and deposit for a long time
Storage；
(2) control module is used by DDR cachings, it is possible to achieve high speed data transfer and storage, timesharing are cached to DDR and controlled
Molding block is written and read；
(3) cached using prediction and monitoring module, can monitored required when carrying out the transmission of data real-time stabilization by DDR
DDR amount of capacity and the service condition of DDR cachings are simultaneously shown.
Brief description of the drawings
Fig. 1 is the schematic diagram of the data storage transit system of the high speed based on FPGA according to the embodiment of the present invention.
【Embodiment of the present disclosure main element symbol description in accompanying drawing】
1- data resource interface modules；
2-DDR cache interface modules
3-DDR buffer control modules；
31-DDR cachings use control submodule；
32- is predicted and monitoring submodule；
4-LCD display interface modules；
5- external storage interface modules.
Embodiment
Present disclose provides a kind of data storage transit system of the high speed based on FPGA, height is realized using FPGA system
The real-time data storage of speed.The disclosure is simple in construction, requirement on devices is low, cost is cheap, can be widely applied to need to carry out to count greatly
According to the occasion of amount high speed real-time storage, the high speed image data real-time storage application especially suitable for biomedical sector.
For the purpose, technical scheme and advantage of the disclosure are more clearly understood, below in conjunction with specific embodiment, and reference
Accompanying drawing, the disclosure is further described.
The some embodiments of the disclosure will be done with reference to appended accompanying drawing in rear and more comprehensively describe to property, some of but not complete
The embodiment in portion will be illustrated.In fact, the various embodiments of the disclosure can be realized in many different forms, and should not be construed
To be limited to this several illustrated embodiment；Relatively, there is provided these embodiments cause the disclosure to meet applicable legal requirement.
In first exemplary embodiment of the disclosure, there is provided a kind of data storage path of the high speed based on FPGA
System, the real-time data storage of high speed is realized using FPGA system.Fig. 1 is high speed of the first embodiment of the present disclosure based on FPGA
Data storage transit system schematic diagram.As shown in figure 1, the data storage transit system bag of high speed of the disclosure based on FPGA
Include：Data resource interface module 1, DDR cache interface modules 2, DDR buffer control modules 3, LCD display interface modules 4 and outside are deposited
Take interface module 5.Wherein, data resource interface module 1, DDR buffer control modules 3 and external access interface module 5 are sequentially connected,
DDR buffer control modules 3 are also connected to DDR cache interface modules 2 and LCD display interface modules 4 simultaneously.
Each part of the data storage transit system of high speed of the present embodiment based on FPGA is carried out individually below
It is described in detail.
Data resource interface module 1 includes three kinds of optical fiber, camera link and FPGA I/O Parallel interfaces, can be answered according to actual
Any one interface is used with the toggle switch selection by FPGA development boards, to receive the data that data source transmits, by data
It is integrated into unified parallel data stream, and produces corresponding data valid signal.
DDR cache interface modules 2 are connected to DDR cachings and use control module 31, and it contains DDR controller, with outside DDR
Storage chip connects, and provides data read and write interface for DDR buffer control modules 3, read-write interface shares a set of address signal.
External storage interface module 5 is connected to DDR cachings and uses control submodule 31 and prediction and monitoring submodule 32, bag
High-speed interface controller is included, is connected with external memory storage, the external memory storage is mass storage, and its memory capacity is
1T-4T, it can be selected according to real needs, the external storage interface module 5 is provided outer for DDR cachings using control submodule 31
The data read and write interface of portion's memory, to predict the state that high-speed interface controller is provided with monitoring submodule 32.
DDR buffer control modules 3 are the core components of the disclosure, its internal realization described further below：
As shown in figure 1, DDR buffer control modules 3, which include DDR cachings, uses control submodule 31 and prediction and monitoring submodule
Block 32, wherein：
DDR cachings are connect using control submodule 31 and data resource interface module 1, DDR cache interface modules 2 and external storage
Mouth mold block 5 connects.DDR cachings realize read-write pointer using control submodule 31, can be with timesharing to DDR buffer control modules 3
It is written and read, when data resource interface module 1 there are data to transmit, DDR cachings write data into DDR using control submodule 31 and delayed
Deposit interface module 2；When 1 no data of data resource interface module transmit, DDR cachings use FIFO's using control submodule 31
Mode reads data by DDR cache interface modules 2, and the data read are transmitted into external storage interface module 5.
Prediction and monitoring submodule 32 and data resource interface module 1, external storage interface module 5, LCD display interface modules
4 and DDR cachings are connected using control submodule 31.Counter is realized inside prediction and monitoring submodule 32, is surveyed available for simulation
Examination needs the DDR cache sizes used：When data resource interface module 1 has data to transmit, prediction and the increase of monitoring submodule 32 are counted
Rolling counters forward, when DDR cachings read data using control submodule 31 from DDR cache interface modules 2, DDR cachings use prediction
Rolling counters forward is reduced with monitoring module 32, the maximum count that final counter is reached is required buffer memory capacity size；
During normal work, prediction and monitoring submodule 32 are by reading DDR cachings using control submodule 31 to DDR cache interface modules
The pointer of 2 read-writes, the service condition of DDR cachings can be calculated.
Especially, the data storage transit system of high speed of the disclosure based on FPGA also includes：
LCD display interface modules, prediction and monitoring submodule 32 are connected to, it includes external display driving, with prediction
Connected with monitoring module 32 with external display, can when prediction transmits DDR cache predictions value and use value with monitoring module 32
To control external display to show, the external display is LCD1602.
Certainly, above-mentioned hardware configuration should also include the functional modules such as power module (not shown), and these are in the art
Those skilled in the art it should be understood that those skilled in the art in the art can also add corresponding according to the needs of function
Functional module, therefore not to repeat here.
So far, the data storage transit system introduction of high speed of the first embodiment of the present disclosure based on FPGA finishes.
So far, the embodiment of the present disclosure is described in detail combined accompanying drawing.It should be noted that in accompanying drawing or say
In bright book text, the implementation that does not illustrate or describe is form known to a person of ordinary skill in the art in art, and
It is not described in detail.In addition, the above-mentioned definition to each element and method be not limited in mentioning in embodiment it is various specific
Structure, shape or mode, those of ordinary skill in the art simply can be changed or replaced to it.
Those skilled in the art, which are appreciated that, to be carried out adaptively to the module in the equipment in embodiment
Change and they are arranged in one or more equipment different from the embodiment.Can be the module or list in embodiment
Member or component be combined into a module or unit or component, and can be divided into addition multiple submodule or subelement or
Sub-component.In addition at least some in such feature and/or process or unit exclude each other, it can use any
Combination is disclosed to all features disclosed in this specification (including adjoint claim, summary and accompanying drawing) and so to appoint
Where all processes or unit of method or equipment are combined.Unless expressly stated otherwise, this specification (including adjoint power
Profit requires, summary and accompanying drawing) disclosed in each feature can be by providing the alternative features of identical, equivalent or similar purpose come generation
Replace.Also, in if the unit claim of equipment for drying is listed, several in these devices can be by same hard
Part item embodies.
Similarly, it will be appreciated that in order to simplify the disclosure and help to understand one or more of each open aspect,
Above in the description to the exemplary embodiment of the disclosure, each feature of the disclosure is grouped together into single implementation sometimes
In example, figure or descriptions thereof.However, the method for the disclosure should be construed to reflect following intention：I.e. required guarantor
The disclosure of shield requires features more more than the feature being expressly recited in each claim.It is more precisely, such as following
Claims reflect as, open aspect is all features less than single embodiment disclosed above.Therefore,
Thus the claims for following embodiment are expressly incorporated in the embodiment, wherein each claim is in itself
Separate embodiments all as the disclosure.
Particular embodiments described above, the purpose, technical scheme and beneficial effect of the disclosure are carried out further in detail
Describe in detail bright, should be understood that the specific embodiment that the foregoing is only the disclosure, be not limited to the disclosure, it is all
Within the spirit and principle of the disclosure, any modification, equivalent substitution and improvements done etc., the guarantor of the disclosure should be included in
Within the scope of shield.
Claims (10)
1. a kind of data storage transit system based on FPGA, including：
Data resource interface module (1), the data transmitted for receiving data source；
DDR cache interface modules (2), for providing cache interface to the data for passing in and out DDR storage chips；
External storage interface module (5), for providing interface to the data for passing in and out external memory storage；
DDR buffer control modules (3), with data resource interface module (1), DDR cache interface modules (2) and external storage interface mould
Block (5) is connected, for by data resource interface module (1) monitoring data reading state, according to the state by data storage extremely
DDR storage chips or by from the data storage that DDR storage chips are read to external memory storage；
Wherein, data resource interface module (1), DDR cache interface modules (2), DDR buffer control modules (3) and external access connect
Mouth mold block (5) is realized based on FPGA.
2. data storage transit system according to claim 1, the DDR buffer control modules (3) include：
DDR cachings use control submodule (31), with data resource interface module (1), DDR cache interface modules (2), external storage
Interface module (5) connects, and reads and writes pointer for realizing, timesharing is by DDR cache interface modules (2) to DDR buffer control modules
(3) it is written and read.
3. data storage transit system according to claim 2, wherein DDR cachings use control submodule (31),
When data resource interface module (1) there are data to transmit, DDR cache interface modules (2) are write data into；
When data resource interface module (1) no data transmit, read using FIFO mode by DDR cache interface modules (2)
Access evidence, and the data read are transmitted to external storage interface module (5).
4. data storage transit system according to claim 3, the DDR buffer control modules (3) also include：
Prediction and monitoring submodule (32), cache and use with data resource interface module (1), external storage interface module (5) and DDR
Control submodule (31) is connected, and counter is realized as inside, the DDR cache sizes for needing to use for simulation test.
5. data storage transit system according to claim 4, wherein, the prediction and monitoring submodule (32),
When data resource interface module (1) there are data to transmit, increase rolling counters forward；
When DDR cachings read data using control module (31) from DDR cache interface modules (2), rolling counters forward is reduced, most
The maximum count that whole counter is reached is required buffer memory capacity size.
6. data storage transit system according to claim 5, wherein, the prediction and monitoring submodule (32) also pass through
The pointer that DDR cachings are read and write using control module (31) to DDR cache interface modules (2) is read, calculates the use feelings of DDR cachings
Condition.
7. data storage transit system according to claim 6, in addition to：
LCD display interface modules (4), be connected to prediction and monitoring submodule (32), it include external display drive, for
Prediction connects with monitoring submodule (32) with external display, when DDR cache prediction values are transmitted in prediction and monitoring submodule (32)
During with use value, external display can be controlled to show.
8. data storage transit system according to claim 7, the external display is LCD1602.
9. data storage transit system according to claim 6, wherein,
The external storage interface module (5), it is connected to DDR cachings and uses control submodule (31) and prediction and monitoring submodule
(32) data read and write interface of external memory storage, is provided using control submodule (31) for DDR cachings, to predict and monitoring submodule
Block (32) provides the state of high-speed interface controller, and the external memory storage of external storage interface module (5) connection is great Rong
Memory is measured, its memory capacity is 1T-4T.
10. data storage transit system according to claim 6, wherein,
Data resource interface module (1) includes three kinds of optical fiber, camera link and FPGA I/O Parallel interfaces, passes through FPGA development boards
Toggle switch selection use any one interface, by Data Integration into unified parallel data stream, and produce corresponding data
Useful signal.
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| CN201710820767.2A CN107656881A (en) | 2017-09-13 | 2017-09-13 | Data storage transit system based on FPGA |
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Cited By (1)
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