WO2016082362A1

WO2016082362A1 - Method, device and apparatus for converting data bit width

Info

Publication number: WO2016082362A1
Application number: PCT/CN2015/073508
Authority: WO
Inventors: 姬明春; 谢小龙; 吕安新; 杨敏华
Original assignee: 中兴通讯股份有限公司
Priority date: 2014-11-25
Filing date: 2015-03-02
Publication date: 2016-06-02
Also published as: CN105607888A

Abstract

A method, device and apparatus for converting the data bit width. The method comprises the following steps: selecting input data through at least one level of input multiplexer and obtaining the data needed to be cached; writing the data needed to be cached into a preset number of caches, wherein there is a common divisor relationship between the preset number of the caches and the preset number of the output data; reading the corresponding cached data from the caches, and selecting the read data through the output multiplexer on the basis of the common divisor relationship between the preset number of the caches and the preset number of the output data, and obtaining the preset number of output data.

Description

Data bit width conversion method, device and device

Technical field

The present invention relates to the field of data processing technologies, and in particular, to a data bit width conversion method, apparatus, and device.

Background technique

In the field of digital logic design, the processing bandwidth requirements of data products are getting higher and higher. Therefore, the requirements for technical parameters such as data bit width, clock frequency and bandwidth utilization of the system are also higher. In order to ensure that the system processing clock frequency is also high in the data bit width in the system, and in order to minimize the complexity of the system processing logic, it is usually necessary to convert the input variable or fixed amount of data into a specific fixed bit width. . Therefore, data bit width conversion has become an important step in the system.

Currently, the commonly used data bit width conversion method is to perform bit width conversion directly through a multi-way selector (MUX) and shift logic. In the case of increasing data bit width and higher frequency, the branch of the multiplexer in the commonly used data bit width conversion method will increase sharply, and the data shift logic is very complicated, making the logic of its design complicated. The degree of improvement is greatly reduced, which seriously degrades the system performance, making it a bottleneck of the entire system and failing to meet the processing performance required by the system.

The above content is only used to assist in understanding the technical solutions of the present invention, and does not constitute an admission that the above is prior art.

Summary of the invention

The main purpose of the embodiments of the present invention is to solve the technical problem of logical complexity and low frequency of data bit width conversion.

To achieve the above objective, a data bit width conversion method provided by an embodiment of the present invention includes the following steps:

Selecting input data through at least one level input multiplexer to obtain data that needs to be cached;

Writing the data to be cached into a set number of buffers, wherein there is a common divisor relationship between the set number of buffers and the preset number of output data;

The corresponding cached data is read out from the cache, and based on the common divisor relationship between the set number of the cache and the preset number of output data, the read data is selected by the output multiplexer to obtain a preset quantity. Output data.

Optionally, the set number of the cache is f*e, the preset number of output data is g*e, and e is a common divisor between the set number of the cache and the preset number of output data, based on the cache setting. The common divisor relationship between the quantity and the preset number of output data, the read data is selected by the output multiplexer, and the preset number of output data is obtained:

The cache is divided into f groups, each group includes e caches, and the g group cache is selected from the f group cache by the output multiplexer, and the g*e data cached in the selected g group cache is obtained.

Optionally, the step of selecting input data by using at least one input multiplexer to obtain data that needs to be cached includes:

When the input data is selected by the multi-stage input multiplexer, intermediate data is stored between the multi-stage input multiplexers through the registers.

Optionally, the step of writing the data to be cached into the set number of caches comprises:

Write valid data from the data that needs to be cached to a set number of caches.

Optionally, e is the greatest common divisor between the set number of buffers and the preset number of output data.

Optionally, the output multiplexer is: a multiplexer after the number of branches eliminates a common divisor between the set number of buffers and the preset number of output data.

A data bit width conversion device includes:

The obtaining module is configured to: select at least one level of the input multiplexer to obtain the data to be cached;

Writing a module, configured to: write data to be cached into a set number of caches, wherein there is a common divisor relationship between the set number of caches and the preset number of output data;

The selection module is configured to: read the corresponding cached data from the cache, and perform the readout data through the output multiplexer based on a common divisor relationship between the set number of the cache and the preset number of output data. Select to get a preset amount of output data.

Optionally, the set number of the cache is f*e, the preset number of output data is g*e, and the selection module is set to:

Optionally, the obtaining module is further configured to:

Optionally, the writing module is further configured to:

A data bit width conversion device comprising:

At least one level input multiplexer, configured to select input data to obtain data to be cached;

a buffer, including a plurality of cache units, configured to cache data;

The output multiplexer is configured to: select the cached data based on a common divisor relationship between the set number of buffers and the preset number of output data, and obtain a preset number of output data.

Optionally, the number of cache units is f*e, the preset number of output data is g*e, and the output multiplexer is set to:

The cache unit is divided into f groups, each group includes e cache units, and the g group cache unit is selected from the f group cache units, and the g*e data cached in the selected g group cache unit is obtained.

Optionally, the device further includes a register configured to:

When the input data is selected by the multi-stage input multiplexer, intermediate data is stored between the multi-stage input multiplexers.

A computer readable storage medium storing program instructions that, when executed, implement the methods described above.

A data bit width conversion method and apparatus according to an embodiment of the present invention selects input data by at least one level input multiplexer, and writes the selected data into a set number of caches, wherein the cache setting The fixed amount is set to a common value relationship with the preset number of output data, so that when the data in the buffer is read and selected by the output multiplexer, the output is multiplexed. The number of branches of the selector can eliminate the common divisor between the set number of buffers and the preset number of output data, thereby greatly reducing the number of branches of the output multiplexer, and greatly simplifying the logic of the output multiplexer. Increased frequency to meet the processing performance required by the system.

BRIEF abstract

1 is a schematic flow chart of an embodiment of a data bit width conversion method according to the present invention;

2 is a schematic diagram of functional modules of an embodiment of a data bit width conversion device according to the present invention;

FIG. 3 is a schematic structural diagram of an embodiment of a data bit width conversion device according to the present invention.

The implementation, functional features, and advantages of the present invention will be further described in conjunction with the embodiments.

Preferred embodiment of the invention

It is understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The invention provides a data bit width conversion method.

Referring to FIG. 1, FIG. 1 is a schematic flowchart diagram of an embodiment of a data bit width conversion method according to the present invention.

In an embodiment, the data bit width conversion method comprises:

Step S10, selecting input data by using at least one level input multiplexer, and acquiring data that needs to be cached;

In this embodiment, when it is determined that there is data input, the input data is selected by at least one input multi-way selector (MUX), wherein when the input data is selected by the multi-stage input multiplexer, Select consecutive times to get the data that needs to be cached. Moreover, a register is inserted between each stage in the multi-stage input multiplexer, and the intermediate data generated during the selection process between the input multiplexers of each stage is stored through the inserted register, thus, compared to only passing The first-stage multiplexer selects the input data, selects the multi-stage input multiplexer, and inserts the register to store the intermediate data between the stages to cut the complex logic, which greatly simplifies the logic. The input system is used to select the system frequency.

Step S20, writing the data to be cached into a set number of caches, wherein there is a common divisor relationship between the set number of buffers and the preset number of output data;

After selecting the data to be cached, the data to be cached is written into the set number of caches, and the set number of the cache is set to the preset number of output data according to the preset number of final output data required by the system. There is a common divisor relationship between the set number of buffers and the preset number of output data, so that when the data is selected by the output multiplexer, the number of branches of the output multiplexer can be The common divisor between the set number of buffers and the preset number of output data is eliminated, thereby greatly reducing the number of branches of the output multiplexer and simplifying the logic. The data to be cached may be sequentially written into the set number of caches according to the pointer, wherein the set number of caches may form a cache group.

Step S30, reading corresponding cached data from the cache, and selecting, according to a common divisor relationship between the set number of the cache and the preset number of output data, selecting the read data by the output multiplexer to obtain A preset amount of output data.

The corresponding cached data is read out from the set number of caches of the cache group, and the read data is selected by the output multiplexer to obtain the converted preset number of output data. The output multiplexer eliminates the set number of the cache and the preset of the output data, because the number of branches in the cache group is in a common number relationship with the preset number of output data. A multiplexer after the number of conventions between the numbers.

For example, if the number of caches in the cache group is f*e, where f represents a cache block in the cache group, each cache block contains e caches, and correspondingly, the preset number of output data is g*e, Where e is the common divisor between the set number f*e of the cache and the preset number g*e of the output data, and the number of branches of the output multiplexer can eliminate the common divisor e, that is, only from the cache group Among the f cache blocks, g cache blocks are selected, wherein each cache block contains e caches, and the valid data buffered in the g cache blocks is a preset number of output data, thereby realizing conversion of output data. Compared with the related art, the number of output data required by the system is selected from all the caches of the cache group by the multiplexer. In this embodiment, the number of branches of the output multiplexer is greatly reduced, and the output multiplexer is greatly simplified. Logic, which increases the frequency.

In this embodiment, the input data is selected by at least one level input multiplexer, and the selected data is written into the set number of buffers, wherein the set number of buffers is set to be the preset number of output data. A common number relationship, such that when the data in the buffer is read and selected by the output multiplexer, the number of branches of the output multiplexer can eliminate the set number and output of the cache. The common divisor between the preset numbers of data, so that the number of branches of the output multiplexer is greatly reduced, the logic of the output multiplexer is greatly simplified, the frequency is increased, and the processing performance required by the system is satisfied.

In other embodiments, in the above step S20, when the data to be cached is written into the set number of caches, only the valid data in the data to be cached is written into the set number of caches, which will need to be cached. The invalid data in the data is eliminated, so that the system cache space can be saved, the system cache space can be wasted to store invalid data, and the subsequent selection of the output data by the output multiplexer in the read cache data can be prevented. Obtaining invalid data, that is, ensuring that the final output data is valid data, improving the utilization of system bandwidth, and further improving the frequency and system performance.

In other embodiments, in the above step S20, the common divisor between the set number of buffers and the preset number of output data is the greatest common divisor, and the cache is set according to a preset number of final output data required by the system. When the number is set, the common divisor between the set number of the set buffer and the preset number of output data is the greatest common divisor, so that the number of branches of the output multiplexer is eliminated by the set number of the cache and the output data. The minimum common divisor between the preset numbers is the least, which maximizes the logic simplification of the output multiplexer, maximizes the frequency, and satisfies the system's required frequency and processing performance even when the input data is large.

The invention also provides a data bit width conversion device.

Referring to FIG. 2, FIG. 2 is a schematic diagram of functional blocks of an embodiment of a data bit width conversion device according to the present invention.

In an embodiment, the data bit width conversion device comprises:

The obtaining module 01 is configured to select input data by using at least one input multiplexer to obtain data that needs to be cached;

In this embodiment, when it is determined that there is data input, the input data is selected by at least one input multi-way selector (MUX), wherein when the input data is selected by the multi-stage input multiplexer, Select consecutive times to get the data that needs to be cached. Moreover, a register is inserted between the multi-stage input multiplexers, and the intermediate data generated during the selection process between the input multiplexers of each level is stored through the inserted register, thus, compared with only one level Road selection The selector selects the input data, selects the multi-stage input multiplexer, and inserts the register to store the intermediate data between the stages to cut the complex logic, greatly simplifying the logic and selecting the input data. Increased system frequency.

The writing module 02 is configured to write the data to be cached into the set number of buffers, wherein there is a common divisor relationship between the set number of buffers and the preset number of output data;

The selecting module 03 is configured to read the corresponding cached data from the cache, and perform the readout data through the output multiplexer based on the common divisor relationship between the set number of the cache and the preset number of the output data. Select to get a preset amount of output data.

For example, if the number of caches in the cache group is f*e, where f represents a cache block in the cache group, each cache block contains e caches, and correspondingly, the preset number of output data is g*e, Where e is the common divisor between the set number f*e of the cache and the preset number g*e of the output data, and the number of branches of the output multiplexer can eliminate the common divisor e, that is, only from the cache group Among the f cache blocks, g cache blocks are selected, wherein each cache block contains e caches, and the valid data buffered in the g cache blocks is a preset number of output data, thereby realizing conversion of output data. Compared with the existing multiplexer directly selecting the required amount of output data from all the caches of the cache group, the number of branches of the output multiplexer in this embodiment is greatly reduced, which greatly simplifies the output multiplexer. Logic, which increases the frequency.

In this embodiment, the input data is selected by at least one level input multiplexer, and the selected data is written into the set number of buffers, wherein the set number of buffers is set to be the preset number of output data. A common number relationship, such that when the data in the buffer is read and selected by the output multiplexer, the number of branches of the output multiplexer can eliminate the set number of buffers and the preset number of output data. The common divisor thus greatly reduces the number of branches of the output multiplexer, greatly simplifies the logic of the output multiplexer, improves the frequency, and satisfies the processing performance required by the system.

In other embodiments, the writing module 02 is further configured to: when writing the data to be cached into the set number of caches, only write valid data in the data to be cached into the set number of caches, Invalid data culling in the data that needs to be cached, thus saving the system's cache space, avoiding wasting system cache space to store invalid data, and preventing subsequent selection by the output multiplexer in the read cache data. When the data is output, the invalid data is obtained, that is, the output data finally obtained is guaranteed to be valid data, which improves the utilization of the system bandwidth and improves the frequency and system performance.

In other embodiments, the common divisor between the set number of buffers and the preset number of output data is the greatest common divisor, and when the set number of caches is set according to a preset number of final output data required by the system, The common divisor between the set number of settings of the cache and the preset number of output data is the greatest common divisor, so that the number of branches of the output multiplexer is between the set number of the erase buffer and the preset number of output data. The least commonality is minimized, which maximizes the logic simplification of the output multiplexer and maximizes the frequency. Even when the input data is large, the system can meet the required frequency and processing performance.

3 is a schematic structural diagram of an embodiment of a data bit width conversion device according to the present invention. The data bit width conversion device includes:

a buffer, including a plurality of cache units, configured to cache data;

The number of cache units is f*e, the preset number of output data is g*e, and the output multiplexer can be set to:

The data bit width conversion device may further include a register configured to:

Where e can be the greatest common divisor between the set number of buffers and the preset number of output data.

The above are only preferred embodiments of the present invention and are not intended to limit the scope of the invention.

One of ordinary skill in the art will appreciate that all or a portion of the steps of the above-described embodiments can be implemented using a computer program flow, which can be stored in a computer readable storage medium, such as on a corresponding hardware platform (eg, The system, device, device, device, etc. are executed, and when executed, include one or a combination of the steps of the method embodiments.

Alternatively, all or part of the steps of the above embodiments may also be implemented by using an integrated circuit. These steps may be separately fabricated into individual integrated circuit modules, or multiple modules or steps may be fabricated into a single integrated circuit module. achieve.

The devices/function modules/functional units in the above embodiments may be implemented by a general-purpose computing device, which may be centralized on a single computing device or distributed over a network of multiple computing devices.

When each device/function module/functional unit in the above embodiment is implemented in the form of a software function module and sold or used as a stand-alone product, it can be stored in a computer readable storage medium. The above mentioned computer readable storage medium may be a read only memory, a magnetic disk or an optical disk or the like.

Industrial applicability

In the embodiment of the present invention, the data in the buffer is read out and is output through the output multiplexer. When selected, the number of branches of the output multiplexer can eliminate the common divisor between the set number of buffers and the preset number of output data, thereby greatly reducing the number of branches of the output multiplexer, and making the output multiplexer The logic is greatly simplified, the frequency is increased, and the processing performance required by the system is met.

Claims

A data bit width conversion method includes the following steps:

Selecting input data through at least one level input multiplexer to obtain data that needs to be cached;

Writing the data to be cached into a set number of buffers, wherein there is a common divisor relationship between the set number of buffers and the preset number of output data;

The corresponding cached data is read out from the cache, and based on the common divisor relationship between the set number of the cache and the preset number of output data, the read data is selected by the output multiplexer to obtain a preset quantity. Output data.
The data bit width conversion method according to claim 1, wherein the set number of buffers is f*e, the preset number of output data is g*e, and e is a set number of buffers and a preset number of output data. The common divisor is based on the common divisor relationship between the set number of buffers and the preset number of output data, and the read data is selected by the output multiplexer to obtain a preset number of output data including:

The cache is divided into f groups, each group includes e caches, and the g group cache is selected from the f group cache by the output multiplexer, and the g*e data cached in the selected g group cache is obtained.
The data bit width conversion method according to claim 1, wherein said step of selecting input data by at least one-stage input multiplexer to obtain data to be cached comprises:

When the input data is selected by the multi-stage input multiplexer, intermediate data is stored between the multi-stage input multiplexers through the registers.
The data bit width conversion method according to claim 1, wherein said step of writing data to be cached into a set number of buffers comprises:

Write valid data from the data that needs to be cached to a set number of caches.
The data bit width conversion method according to claim 2, wherein e is a greatest common divisor between the set number of buffers and the preset number of output data.
The data bit width conversion method according to any one of claims 1 to 5, wherein said The output multiplexer is a multiplexer after the number of branches eliminates the common divisor between the set number of buffers and the preset number of output data.
A data bit width conversion device includes:

The obtaining module is configured to: select at least one level of the input multiplexer to obtain the data to be cached;

Writing a module, configured to: write data to be cached into a set number of caches, wherein there is a common divisor relationship between the set number of caches and the preset number of output data;

The selection module is configured to: read the corresponding cached data from the cache, and perform the readout data through the output multiplexer based on a common divisor relationship between the set number of the cache and the preset number of output data. Select to get a preset amount of output data.
The apparatus according to claim 7, wherein the set number of buffers is f*e, the preset number of output data is g*e, and the selection module is set to:

The cache is divided into f groups, each group includes e caches, and the g group cache is selected from the f group cache by the output multiplexer, and the g*e data cached in the selected g group cache is obtained.
The apparatus of claim 7, wherein the obtaining module is further configured to:

When the input data is selected by the multi-stage input multiplexer, intermediate data is stored between the multi-stage input multiplexers through the registers.
The apparatus of claim 7 wherein said writing module is further configured to:

Write valid data from the data that needs to be cached to a set number of caches.
The apparatus of claim 8 wherein e is a greatest common divisor between the set number of buffers and the preset number of output data.
The apparatus according to any one of claims 7 to 11, wherein the output multiplexer is such that the number of branches eliminates a common divisor between the set number of buffers and the preset number of output data Road selector.
A data bit width conversion device comprising:

At least one level input multiplexer, configured to select input data to obtain data to be cached;

a buffer, including a plurality of cache units, configured to cache data;

The output multiplexer is configured to: select the cached data based on a common divisor relationship between the set number of buffers and the preset number of output data, and obtain a preset number of output data.
The apparatus of claim 13, wherein the number of cache units is f*e, the preset number of output data is g*e, and the output multiplexer is set to:

The cache unit is divided into f groups, each group includes e cache units, and the g group cache unit is selected from the f group cache units, and the g*e data cached in the selected g group cache unit is obtained.
The apparatus of claim 13 further comprising a register configured to:

When the input data is selected by the multi-stage input multiplexer, intermediate data is stored between the multi-stage input multiplexers.
The apparatus of claim 14, wherein e is a greatest common divisor between the set number of buffers and the preset number of output data.
A computer readable storage medium storing program instructions that, when executed, can implement the method of any of claims 1-6.