CN108701102A - Direct memory access controller, method for reading data and method for writing data - Google Patents
Direct memory access controller, method for reading data and method for writing data Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
Abstract
A kind of dma controller, method for reading data and method for writing data, the dma controller includes control access and read data path, control access includes reading control unit, control unit is read for generating read control signal, and read data path is controlled by read control signal and reads the first data from external memory via external bus;Read data path includes unwrapper unit, and for unwrapper unit for being unpacked to the first data, internal storage unit is written via internal bus in the first data after unpacking by read data path.Dma controller by being arranged control access and read data path inside it, read data path from external memory while reading data, data are unpacked by unwrapper unit, so that dma controller carries out de-packaging operation while data-moving, the two parallel processing, data processing speed can be improved, the performance of chip can be promoted.
Description
Copyright notice
This patent document disclosure includes material protected by copyright.The copyright is all for copyright holder.Copyright
Owner does not oppose the patent document in the presence of anyone replicates the proce's-verbal of Patent&Trademark Office and archives or should
Patent discloses.
Technical field
This application involves data processing field more particularly to direct memory access (Direct Memory Access,
DMA) controller, method for reading data and method for writing data.
Background technology
With the fast development of chip industry, the function complexity of chip is higher and higher.Chip is to complete data processing to lead to
Include often dma controller and data processing unit.The function of dma controller on the market is all more single now, major function
It is to complete data to move operation.To read data instance, as fruit chip needs reading and handles the picture number of different bit wide pixels
According to then usually a preprocessing module is arranged in data processing unit in chip, completes the de-packaging operation of image data.De-packaging operation
It is the image data solution of compact storage in memory to be bundled into the wieldy format of data processing unit, such as will make in DDR
It is bundled into 16bit or 32bit bit wides with the image data solution of 8 bits (bit), 10bit, 12bit or 16bit bit wide compact storage
According to rule storage etc..In currently existing scheme, which is completed by the preprocessing module of data processing unit, because
This, dma controller moves data and preprocessing module to data unpack and serially be carried out.In other words, such as
Fruit will handle one piece of image data, and dma controller is needed to complete data-moving first, and then preprocessing module could be completed to unpack
Operation, can not carry out parallel.This makes the speed that chip carries out data processing very slow.
Invention content
It, can be with this application provides a kind of direct memory access controller, method for reading data and method for writing data
Data processing speed is improved, the performance of chip can be promoted.
In a first aspect, a kind of direct memory access dma controller, including control access and read data path are provided,
The control access includes reading control unit, and the reading control unit is controlled for generating read control signal, and by the reading
Signal controls the read data path and reads the first data from external memory via external bus;The read data path includes solution
Packet unit, for the unwrapper unit for being unpacked to first data, the read data path counts first after unpacking
Internal storage unit is written according to via internal bus.
The dma controller of first aspect is existed by the way that control access and read data path, read data path are arranged inside it
While reading data from external memory, data are unpacked by unwrapper unit so that dma controller is in data-moving
It is carried out at the same time de-packaging operation, the two parallel processing can improve data processing speed, can promote the performance of chip.
Second aspect, provides a kind of direct memory access dma controller, including control access and writes data path,
The control access includes writing control unit, and the control unit of writing writes control for generating write control signal, and by described
Signal controls write data access and reads the second data from internal storage unit via internal bus;Write data access packet
Include packaged unit, the packaged unit is for being packaged second data, and write data access is by the after packing
External memory is written via external bus in two data.
The dma controller of second aspect writes data path and exists by the way that control access is arranged inside it and writes data path
Toward external memory write access according to while, data are packaged by packaged unit so that dma controller is in data-moving
It is carried out at the same time packaging operation, the two parallel processing can improve data processing speed, can promote the performance of chip.
The third aspect, provides a kind of method for reading data, and the method is held by direct memory access dma controller
Row, the dma controller include control access and read data path, and the control access includes reading control unit, the reading
Include unwrapper unit according to access, the method includes:The reading control unit generates read control signal, and is controlled by the reading
Signal controls the read data path and reads the first data from external memory via external bus;The unwrapper unit is to described
One data are unpacked, and internal storage unit is written via internal bus in the first data after unpacking by the read data path.
Fourth aspect, provides a kind of method for writing data, and the method is held by direct memory access dma controller
Row, the dma controller include control access and write data path, and the control access includes writing control unit, described to write number
Include packaged unit according to access, the method includes:The control unit of writing generates write control signal, and writes control by described
Signal controls write data access and reads the second data from internal storage unit via internal bus;The packaged unit is to institute
It states the second data to be packaged, external memory is written via external bus in the second data after packing by write data access.
5th aspect, provides a kind of integrated circuit, including dma controller described in claim first aspect and/or
Dma controller described in second aspect.
6th aspect, provides a kind of movable equipment, including dma controller described in claim first aspect and/
Or the dma controller described in second aspect.
Description of the drawings
Fig. 1 is the dma controller schematic block diagram of the application one embodiment.
Fig. 2 is the schematic diagram of the data de-packaging operation of the application one embodiment.
Fig. 3 is a kind of schematic diagram of realization method of the descriptor caching of the application one embodiment.
Fig. 4 is the schematic diagram of the descriptor format of the application one embodiment.
Fig. 5 is the dma controller schematic block diagram of another embodiment of the application.
Fig. 6 is the dma controller schematic block diagram of another embodiment of the application.
Fig. 7 is the schematic flow chart of the method for reading data of the application one embodiment.
Fig. 8 is the schematic flow chart of the method for writing data of the application one embodiment.
Specific implementation mode
Below in conjunction with attached drawing, technical solutions in the embodiments of the present application is described.
Unless otherwise defined, all of technologies and scientific terms used here by the article and belong to the technical field of the application
The normally understood meaning of technical staff is identical.The term used in the description of the present application is intended merely to description tool herein
The purpose of the embodiment of body, it is not intended that in limitation the application.
The embodiment of the present application provides a kind of dma controller, has and reads data function.Fig. 1 is one implementation of the application
The schematic block diagram of the dma controller 100 of example.As shown in Figure 1, dma controller 100 includes that control access 110 and reading data are logical
Road 120.Control access 110 may include reading control unit 112, read control unit 112 for generating read control signal, and pass through
Read control signal controls read data path 120 and reads the first data from external memory 220 via external bus 210.It is logical to read data
Road 120 may include unwrapper unit 122, and for being unpacked to the first data, read data path 120 will solve unwrapper unit 122
Internal storage unit 240 is written via internal bus 230 in the first data after packet.
It should be understood that in the embodiment of the present application, external bus 210 can be level expansion interface (Advanced
EXtensible Interface, AXI) bus can also be bus as defined in other agreements.External memory 220 can be double
Haplotype data rate SDRAM (Double Data Rate SDRAM, DDR SDRAM), or referred to as DDR memories, wherein SDRAM
It is synchronous DRAM (Synchronous Dynamic Random Access Memory).Internal bus 230 can
To be crossbar switch (CROSSBAR) bus.The embodiment of the present application is to external bus 210, external memory 220, internal bus 230
It is not construed as limiting with the specific implementation form of internal storage unit 240 etc..
It should also be understood that as shown in Figure 1, the embodiment of the present application specifically can read unit by the external of read data path 120
126 read the first data via external bus 210 from external memory 220, and the embodiment of the present application is not construed as limiting this.
It is logical to read data by the way that control access and read data path are arranged inside it for the dma controller of the embodiment of the present application
While Lu Cong external memories read data, data are unpacked by unwrapper unit so that dma controller is removed in data
De-packaging operation is carried out while shifting, the two parallel processing can improve data processing speed, can promote the performance of chip.
Further, since dma controller unpacks data, the downstream units of dma controller need not again will be former
Beginning data are unpacked, and which increase the flexibilities of the downstream units of dma controller so that the dma controller can be used in more
The different application scenarios of kind, such as big end storage, small end storage etc..
Optionally, as shown in Figure 1, read data path 120 can also include the first clock processing unit 124, for reading
Data path 120 read the first data into line asynchronous first in, first out (First Input First Output, FIFO) across
Clock domain processing, unwrapper unit 122 are specifically used for that treated that the first data unpack to the cross clock domain that carries out FIFO.The
One clock processing unit 124 can synchronize the data from different clock-domains using FIFO technologies.
First clock processing unit 124 can will be read from external memory 220 (for example, can be DDR memories)
After first data carry out the cross clock domain processing of FIFO, unwrapper unit 122 is given.It should be understood that in practical applications, in order to save
The bandwidth of DDR memories, the pixel value of data especially image generally all can be stored compactly in DDR memories.Different bit wide pictures
The format that the image of element stores in DDR memories is different.The unwrapper unit 122 of the embodiment of the present application is in order to facilitate subsequent cell
Data processing mends 0 to the first data of reading in the high-order of original pixels numerical value, by pixel bit wide be extended to 16bit or
32bit.I.e. unwrapper unit 122 need to carry out the conversion of data format.
Optionally, unwrapper unit 122 can unpack the first data according to the solution pack mode of systemic presupposition.This Shen
Please embodiment support solution pack mode may include Direct Model, low level word pattern, half word pattern of low level, parity column split mould
In formula, one piece of (one-bank) replication mode, high-order word pattern, high-order half word pattern and two pieces of (two-bank) replication modes
At least one, and the embodiment of the present application is not limited to that.
Direct Model is to export data as former state, does not do format conversion.Low level word pattern is using a word (word, packet
Include 32bit) one pixel value of lower memory, high-order zero padding.In this way, can be by 8bit, 10bit, 12bit and 16bit bit wide
Pixel-expansion at 32bit.Half word pattern of low level is one pixel value of lower memory using half of word, high-order zero padding.This
Sample, can be by the pixel-expansion of 8bit, 10bit and 12bit bit wide at 16bit.High-order word pattern is the height using a word
One pixel value of position storage, low level zero padding.High-order half word pattern is one pixel value of higher memory using half of word, low level
Zero padding.Under one-bank replication modes, each bank is one group, data is copied as 16 parts, every part of data are placed on a bank
In.Under two-bank replication modes, each two bank is one group, data is copied as 8 parts, every part of data are placed on two bank
In.Parity column split mode is to split data into two parts, is respectively stored in even bank and odd bank, such as by least-significant byte
Data are stored in even bank, and most-significant byte data are stored in odd bank, and the embodiment of the present application is not construed as limiting this.
The pixel bit wide (pixel width) that can be supported of the embodiment of the present application may include 8bit, 10bit, 12bit
And 16bit, and it is not limited only to this.
Fig. 2 is the schematic diagram of the data de-packaging operation of the application one embodiment.As shown in Fig. 2, data are with 12bit pixels
Format be stored in external memory, include the data of pixel 0- pixels 9.The present embodiment is solved using half word pattern of low level
Packet, each pixel 16bit, a high position are inserted into 0 to fill after unpacking.Wherein, the preceding most significant bit with data after unpacking is unpacked
(Most Significant Bit, MSB) and least significant bit (Least Significant Bit, LSB) are respectively such as Fig. 2 institutes
Show.The embodiment of the present application need not deposit the image data (such as data after Fig. 2 unpackings) comprising bulk redundancy information as a result,
Storage stores the data before Fig. 2 is unpacked in external memory, to save memory bandwidth.
Optionally, unwrapper unit 122 may include 3 grades of pipelines (pipeline).
Data (such as first data) solution of different bit wide pixels can be bundled into a certain bit wide, example by first order pipeline
Such as 16bit.In a specific example, the input of first order pipeline is can be with 128bit data.For 8bit pixels,
One beat of data includes 16 pixels;For 10bit pixels, a beat of data includes 12 pixels;For 12bit pixels, a umber of beats
According to including 10 pixels, after first order pipeline unpacks data, data bit width 16bit.
Second level pipeline can be filled data (padding) operation.Padding operations are will be wide high insufficient
256 × 256 band (tile) is extended to 256 × 256 tile, wherein extended area mends 0 pixel.
Third level pipeline can complete half-word to the conversion of word, the conversion of low level a to high position.Because of the first order
Data after pipeline is unpacked are half word patterns of low level, if current solution pack mode requires other patterns, it is necessary to logarithm
It is converted according to format.
It should be understood that unwrapper unit includes 3 grades of pipeline exemplary only, rather than the restriction to the embodiment of the present application.
Optionally, as shown in Figure 1, control access 110 can also include DCU data control unit 114.DCU data control unit 114
It can be used for reading the first descriptor of the first data, read control unit 112 and be specifically used for generating reading control according to the first descriptor
Signal processed.
Optionally, as shown in Figure 1, DCU data control unit 114 can be via kernel bus 250 from kernel (core) 260
Read the first descriptor of the first data.
The descriptor of the embodiment of the present application can serve to indicate that priority, wherein need to consider there are many situation, for example, the
One descriptor may include the first field, and the type that the first field is used to indicate the first data is immediate, 1D data or 2D numbers
According to.The priority of immediate is more than the priority of one-dimensional (1D) data and two-dimentional (2D) data.In general, 1D tasks and 2D tasks point
The data volume of the defeated 1D data of supplementary biography and 2D data is bigger.During 1D data and 2D data are transmitted, if data control
The descriptor of an immediate is pressed into unit 114 processed, then according to descriptor, the task of the immediate can jump the queue in advance
It executes.The dma controller of the embodiment of the present application can promote the execution efficiency of immediate as a result,.
In a specific example, the dma controller of the embodiment of the present application can be supported notable (outstanding)
Efficient data receives structure.The data receiver structure can make full use of outstanding resources, in the case of smaller caching
Realize efficient data receiver.For example, the case where for 8 outstanding, data receiver structure has 8 utilizable marks
Know (IDentifier, ID) 0~7.The use of current ID is indicated with the register (such as register variable busy) of a 8bit
Situation, bit are low, indicate that the bit corresponding ID is not used;Bit are height, are indicating the bit corresponding ID just
It reads back data in waiting.Every a line of one register file of data receiver structural maintenance, register file corresponds to an ID, and storage is worked as
The corresponding buffer memory address preceding ID.Whenever dma controller reads back via external bus from external memory a bat valid data
When, according to the ID of the data, corresponding register file is inquired, obtains the buffer address of the data, then arrives the data buffer storage
In corresponding address, while the address date in the register file is added 1.If the data currently read back are its bursts
(burst) the corresponding registers of the ID are then set to 0 by the last one data, are used for other transmission.
For another example:Dma controller supports outstanding 8, if currently free ID, the ID can be used to read and write vertical
Count.The data volume of immediate is usually smaller, for example, 128bit, it is only necessary to which list (single) floating-point operation can be complete
At transmission.The dma controller of the embodiment of the present application under the premise of smaller cache resources consumption, to greatly promote
The utilization rate of oustanding resources, so as to promote the reading efficiency of dma controller.
In a specific example, the first descriptor may include the second field, and the second field is used to indicate the first number
According to the priority of corresponding task.Specifically, the description of each 1D data or the descriptor of 2D data can configure a 3bit
The second field, be used to indicate the priority of data task.In a specific example, priority can be divided into 8 grades.
Control access task of selection highest priority from descriptor caching is executed.If the priority of multiple tasks is identical,
Being pressed into descriptor caching at first of the task is then selected to be executed.
Optionally, DCU data control unit 114 may include a register, and the register is for depositing in the first descriptor
The priority of the corresponding task of first data reads control unit 112 and is used to generate reading control letter according to the priority in register
Number.In one example, a kind of concrete implementation mode of descriptor caching can be as follows.Fig. 3 is one kind of descriptor caching
The schematic diagram of realization method.As shown in figure 3, one register group of setting, totally 7 row, the often row of register correspond to this group of register
A descriptor in descriptor caching.For example, the descriptor of the corresponding task of data of the 0th row corresponding address 0~9, the 1st
The descriptor ... of the corresponding task of data of row corresponding address 10~19, and so on.The often row of register may include 3
Field (field A, field B and field C) total 7bit, field A (domains used) occupy 1bit, for indicating that the row of register is deposited
Whether storage space is described symbol, and field A values are that the memory space of the row of 1 expression register is described symbol.Field B (domains pri1)
Occupy 3bit, indicate the priority carried in the descriptor of data absolute value (i.e. the value in the domains pri1 by descriptor head pri
Domain assignment).Field C (domains pri2) occupies 3bit, for indicating that task is pressed into the priority of descriptor caching, ensures similarity priority
The task first in first out of grade.The value in the domains pri2 of the descriptor is arranged to register variable when descriptor is just pressed into
Remain, while the value in the domains pri2 subtracts 1, often a descriptor is taken away from descriptor caching, by the domains pri2 of remaining descriptor
Value plus 1.=
It should be understood that the citing of above-mentioned only priority, rather than the restriction to the embodiment of the present application.
Optionally, first descriptor of the embodiment of the present application may include third field, and third field is used to indicate first
The solution pack mode of data.
Fig. 4 is the schematic diagram of the descriptor format of the application one embodiment.The descriptor is the descriptor of 2D data.It retouches
First half-word (16bit) for stating symbol is the head dscrp_head of descriptor, indicates the mode m ode[ of the data;1:0]
(dscrp_head[15:14]), the priority pri[ of the corresponding task of data;2:0](dscrp_head[13:11]), unpack mould
Formula unpack_mode[2:0](dscrp_head[10:8]), pixel bit wide pixel_width[2:0](dscrp_head[7:
5]), the Chang Du [ of descriptor;3:0]dscrp_len
(dscrp_head[4:1]) and direction of transfer direc[0](dscrp_head[0]).Wherein, the pattern of data
Mode can be that the pattern of data in immediate, 1D data or 2D data, such as this example is 2D data.Solve pack mode
Unpack_mode can be one kind in aforementioned a variety of solution pack modes.Direction of transfer direc is reading direction or writes direction.
dscrp_id[11:0]It is used to indicate the ID of the descriptor.Ext_addr (including ext_addr[15:0]And ext_addr[31:
16]) it is used to indicate the data address of external memory.
trans_len[15:0]It is used to indicate conveying length.toggle_num[15:0]Indicate current operation need by
The number repeated.trans_width[15:0]And trans_stride[15:0]The regions 2D are used to indicate, the two parameters
Initial address for calculating next time in line feed.port_cfg1[15:0]And port_cfg2[15:0]It corresponds in two respectively
The number of portion's storage unit, most-significant byte for storing data and least-significant byte.padding_en[0],vld_data_height[6:
0]And vld_data_width[6:0]These three parameters are used for padding, need to carry out for example, padding_en is 1 expression
Padding indicates for 0 without padding, vld_data_height[6:0]And vld_data_width[6:0]For
Define the height and width of empty band.
Optionally, the dma controller of the embodiment of the present application can also include writing data path, and control access can also include
Control unit is write, control unit is write and writes data path via interior for generating write control signal, and by write control signal control
Portion's bus reads the second data from internal storage unit;It may include packaged unit to write data path, and packaged unit is used for the
Two data are packaged, and write data path and external memory is written via external bus in the second data after packing.
Optionally, it can also includes second clock processing unit to write data path, in the second data of packaged unit pair
After being packaged, the cross clock domain that the second data after packing are carried out with asynchronous FIFO is handled.
It will be unfolded in detail below about the relevant operation for writing data path.
The embodiment of the present application also provides a kind of dma controllers, have and write data function.Fig. 5 be the application another
The schematic block diagram of the dma controller 500 of embodiment.As shown in figure 5, dma controller 500 includes control access 510 and writes number
According to access 520.Control access 510 may include writing control unit 512, write control unit 512 for generating write control signal, and
Data path 520, which is write, by write control signal control reads the second data from internal storage unit 240 via internal bus 230.
It may include packaged unit 522 to write data path 520, and packaged unit 522 writes data path for being packaged to the second data
External memory 220 is written via external bus 210 in the second data after packing by 520.
It should be understood that as shown in figure 5, the embodiment of the present application specifically can be by writing the external r/w cell 526 of data path 520
External memory 220 is written into via external bus 210 in the second data after packing, the embodiment of the present application is not construed as limiting this.
It is logical to write data by the way that control access is arranged inside it and writes data path for the dma controller of the embodiment of the present application
Road toward external memory write access according to while, data are packaged by packaged unit so that dma controller is removed in data
Packaging operation is carried out while shifting, the two parallel processing can improve data processing speed, can promote the performance of chip.
Further, since dma controller is packaged data, the upstream units of dma controller need not be by initial data
It is packaged, which increase the flexibilities of the upstream units of dma controller so that the dma controller can be used in a variety of differences
Application scenarios.
Optionally, as shown in figure 5, it can also includes second clock processing unit 524 to write data path 520, for beating
After packet unit 522 is packaged the second data, at the cross clock domain of second data progress asynchronous FIFO after packing
Reason.
Optionally, packaged unit 522 specifically can be used for, according to preset packing pattern, being packaged the second data.
Corresponding with solution pack mode, the packing pattern that the embodiment of the present application is supported may include Direct Model, low level word pattern, low level half
Word pattern, parity column split mode, one-bank replication modes, high-order word pattern, high-order half word pattern and two-bank are replicated
At least one of pattern, and the embodiment of the present application is not limited to that.
The operation principle and flow of the packaged unit 522 of the embodiment of the present application can be with the unwrapper units of the embodiment of the present application
Principle it is similar, flow is on the contrary, no longer repeated herein.
Optionally, as one embodiment, as shown in figure 5, control access 510 can also include DCU data control unit 514.
DCU data control unit 514 is used to read the second descriptor of the second data, writes control unit 512 and is specifically used for according to the second description
Symbol generates write control signal.
Optionally, as one embodiment, as shown in figure 5, DCU data control unit 514 can via kernel bus 250 from
The second descriptor of the second data is read in kernel (core) 260.
Optionally, the second descriptor may include the first field, and the type that the first field is used to indicate the second data is vertical
That is number, one-dimensional 1D data or two-dimentional 2D data.Optionally, the second descriptor may include the second field, and the second field is for referring to
Show the priority of the corresponding task of the second data.Optionally, the second descriptor may include third field, and third field is for referring to
Show the packing pattern (the solution pack mode that the first data are used to indicate corresponding to the third field of the first descriptor) of the second data.
The format of second descriptor of the embodiment of the present application can be same or like with the format of the first descriptor.
It should be understood that if the existing read operation for the same data has write operation again, a descriptor can be used only
To two operations (or two tasks is claimed to carry out) description.
Optionally, as one embodiment, DCU data control unit 514 may include register, and the register is for depositing
The priority of the corresponding task of second data in second descriptor writes control unit 512 for according to the priority in register
Generate write control signal.
Optionally, as one embodiment, dma controller 500 can also include read data path, and control access can be with
Including reading control unit, reads control unit and can be used for generating read control signal, and is logical by read control signal control reading data
The first data are read from external memory in road via external bus;Read data path may include unwrapper unit, and unwrapper unit can be with
For being unpacked to the first data, storage inside list is written via internal bus in the first data after unpacking by read data path
Member.
Optionally, as one embodiment, read data path can also include the first clock processing unit, for reading
According to access read the first data carry out asynchronous FIFO cross clock domain processing, unwrapper unit be specifically used for carry out FIFO across
Treated that the first data are unpacked for clock domain.
It should be understood that including writing the dma controller of data path again for not only including read data path, in DCU data control unit
Register can not only deposit the priority of the corresponding task of data (such as first data) being read, but also deposit is to be written
The priority of the corresponding task of data (such as second data).In other words, reading data and write-in data can share same
A register.Certainly, different registers can also be respectively set by reading data and write-in data, the embodiment of the present application to this not
It is construed as limiting.
It includes read data path but also the feelings including writing data path to illustrate dma controller not only below with a specific example
Condition.Fig. 6 is the schematic block diagram of the dma controller 600 of the application another embodiment.As shown in fig. 6, dma controller 600 wraps
It includes control access 610, read data path 620 and writes data path 630.
Control access 610 may include reading control unit 612 and writing control unit 614.Control unit 612 is read for generating
Read control signal, and read data path 620 is controlled by read control signal and is read from external memory 220 via external bus 210
Data.It writes control unit 614 and writes data path 630 via interior for generating write control signal, and by write control signal control
Portion's bus 230 reads data from internal storage unit 240.Control access 610 can also include DCU data control unit 616.Data
Control unit 616 can be used for reading the descriptor of data.DCU data control unit 616 may include interface (crf_if) module,
It is the interface module of DCU data control unit 616 and kernel bus 250.Can also include reading immediately inside DCU data control unit 616
Number data buffer storage (im_cache) module, descriptor format inspection (dscrp_check) module and descriptor distribute (dscrp_
Distribute) module.Im_cache modules are the modules for caching immediate.Dscrp_check modules are for checking
The module of descriptor format.Descriptor is distributed to reading immediate by dscrp_distribute modules according to the content of descriptor
Task buffer (fifo_im_r) module writes immediate task buffer (fifo_im_w) module, reads 1D2D task buffers (pri_
1d2d_r) module and write 1D2D task buffers (pri_1d2d_w) module this four modules.Fifo_im_r modules are read for caching
Immediate task, fifo_im_w modules write immediate task for caching, pri_1d2d_r modules for cache read 1D tasks and
2D tasks, and have the function of task priority, pri_1d2d_w modules have task for caching the 1D tasks and 2D tasks write
Priority feature.Control unit 612 is read to generate according to fifo_im_r modules or pri_1d2d_r moulds descriptor in the block and read control
Signal.It writes control unit 614 and write control signal is generated according to fifo_im_w modules or pri_1d2d_w moulds descriptor in the block.
Read data path 620 may include that external unit 626 of reading reads number via external bus 210 from external memory 220
According to;Read data path 620 can also include the first clock processing unit 624, the data for reading to read data path 620 into
The cross clock domain of line asynchronous FIFO is handled;Read data path 620 further includes unwrapper unit 622, after being unpacked to data,
Internal storage unit 240 is written via internal bus 230.
It may include packaged unit 632 to write data path 630, for write data path 630 via internal bus 230 from
The data that internal storage unit 240 is read are packaged;It can also includes second clock processing unit 634 to write data path 630,
The cross clock domain that asynchronous FIFO is carried out for the data after being packaged to packaged unit 632 is handled;Writing data path 630 can also wrap
External r/w cell 626 is included, for that will be packaged and cross clock domain treated data are via the write-in external memory of external bus 210
220。
It should be understood that dma controller 600 shown in fig. 6 is only the example of the embodiment of the present application and non-limiting.
Explained above is the dma controllers of the embodiment of the present application, and corresponding data are described in detail separately below and read
Take method and method for writing data.
Fig. 7 is the schematic flow chart of the method for reading data 700 of the application one embodiment.Method 700 can be by DMA
Controller executes, which includes control access and read data path, and control access includes reading control unit, reads data
Access includes unwrapper unit.As shown in fig. 7, method 700 may comprise steps of.
S710 reads control unit and generates read control signal, and controls read data path via outside by read control signal
Bus reads the first data from external memory.
S720, the first data of unwrapper unit pair unpack.
Internal storage unit is written via internal bus in the first data after unpacking by S730, read data path.
The method for reading data of the embodiment of the present application is led to by the way that control access is arranged inside dma controller and reads data
Road, read data path unpack data by unwrapper unit while reading data from external memory so that DMA is controlled
Device processed carries out de-packaging operation while data-moving, and the two parallel processing can improve data processing speed, can promote core
The performance of piece.
Optionally, as one embodiment, the first data of S720 unwrapper units pair unpack, and may include:It unpacks single
Member unpacks the first data according to preset solution pack mode.
Optionally, as one embodiment, read data path can also include the first clock processing unit, and method 700 is also
May include:The first data that first clock processing unit reads read data path into line asynchronous first in, first out FIFO across when
Clock domain is handled;The first data of S720 unwrapper units pair unpack, and may include:Cross clock domain of the unwrapper unit to progress FIFO
Treated, and the first data are unpacked.
Optionally, as one embodiment, control access can also include DCU data control unit, and method 700 can also wrap
It includes:DCU data control unit reads the first descriptor of the first data;S710 reads control unit and generates read control signal, can wrap
It includes:Control unit is read according to the first descriptor, generates read control signal.
Optionally, as one embodiment, the first descriptor includes the first field, and the first field is used to indicate the first data
Type be immediate, one-dimensional 1D data or two-dimentional 2D data.
Optionally, as one embodiment, the first descriptor includes the second field, and the second field is used to indicate the first data
The priority of corresponding task.
Optionally, as one embodiment, the first descriptor includes third field, and third field is used to indicate the first data
Solution pack mode.
Optionally, as one embodiment, DCU data control unit may include register, and method 700 can also include:It posts
Storage deposits the priority of the corresponding task of the first data in the first descriptor;Control unit is read according to the first descriptor, is generated
Read control signal may include:Control unit is read according to the priority in register, generates read control signal.
Optionally, as one embodiment, dma controller further includes writing data path, and control access can also include writing
Control unit, it may include packaged unit to write data path, and method 700 can also include:It writes control unit generation and writes control letter
Number, and data path is write by write control signal control and reads the second data from internal storage unit via internal bus;It is packaged
The second data of unit pair are packaged, and write data path and external memory is written via external bus in the second data after packing.
Optionally, as one embodiment, it can also includes second clock processing unit to write data path, and method 700 is also
May include:Second clock processing unit after the second data of packaged unit pair are packaged, to the second data after packing into
The cross clock domain of line asynchronous first in, first out FIFO is handled.
Fig. 8 is the schematic flow chart of the method for writing data 800 of the application one embodiment.Method 800 can be by DMA
Controller executes, and dma controller includes control access and writes data path, and control access includes writing control unit, and it is logical to write data
Road includes packaged unit, and method 800 may comprise steps of.
S810 writes control unit and generates write control signal, and writes data path via inside by write control signal control
Bus reads the second data from internal storage unit.
S820, the second data of packaged unit pair are packaged.
S830 writes data path and external memory is written via external bus in the second data after packing.
The method for writing data of the embodiment of the present application is led to by the way that control access is arranged inside dma controller and writes data
Road, write data path toward external memory write access according to while, data are packaged by packaged unit so that DMA control
Device processed carries out packaging operation while data-moving, and the two parallel processing can improve data processing speed, can promote core
The performance of piece
Optionally, as one embodiment, the second data of S820 packaged units pair are packaged, and may include:Pack slip
Member is packaged the second data according to preset packing pattern.
Optionally, as one embodiment, it can also includes second clock processing unit to write data path, and method 800 is also
May include:Second clock processing unit after the second data of packaged unit pair are packaged, to the second data after packing into
The cross clock domain of line asynchronous first in, first out FIFO is handled.
Optionally, as one embodiment, control access can also include DCU data control unit, and method 800 can also wrap
It includes:DCU data control unit reads the second descriptor of the second data;S810 writes control unit and generates write control signal, can wrap
It includes:Control unit is write according to the second descriptor, generates write control signal.
Optionally, as one embodiment, the second descriptor includes the first field, and the first field is used to indicate the second data
Type be immediate, one-dimensional 1D data or two-dimentional 2D data.
Optionally, as one embodiment, the second descriptor includes the second field, and the second field is used to indicate the second data
The priority of corresponding task.
Optionally, as one embodiment, the second descriptor includes third field, and third field is used to indicate the second data
Packing pattern.
Optionally, as one embodiment, DCU data control unit may include register, and method 800 can also include:It posts
Storage deposits the priority of the corresponding task of the second data in the second descriptor;Control unit is write according to the second descriptor, is generated
Write control signal may include:It writes control unit and write control signal is generated according to the priority in register.
Optionally, as one embodiment, dma controller can also include read data path, and control access can also wrap
Reading control unit is included, read data path may include unwrapper unit, and method 800 can also include:It reads control unit and generates reading control
Signal processed, and read data path is controlled by read control signal and reads the first data from external memory via external bus;It unpacks
The first data of unit pair unpack, and storage inside list is written via internal bus in the first data after unpacking by read data path
Member.
Optionally, as one embodiment, read data path can also include the first clock processing unit, and method 800 is also
May include:The first data that first clock processing unit reads read data path into line asynchronous first in, first out FIFO across when
Clock domain is handled;The first data of unwrapper unit pair unpack, and may include:Unwrapper unit handles the cross clock domain for carrying out FIFO
The first data afterwards are unpacked.
DMA controls are being described above in the method for reading data of the embodiment of the present application and the detailed process of method for writing data
It is described in detail when device processed, details are not described herein again.
The embodiment of the present application also provides a kind of integrated circuit, which includes the dma controller of the embodiment of the present application
100, at least one of dma controller 500 and dma controller 600.
It should be understood that the integrated circuit of the embodiment of the present application can be Application-Specific Integrated Circuit (Application
Specific Integrated Circuit, ASIC) or be field programmable gate array (Field-Programmable
Gate Array, FPGA).
The embodiment of the present application also provides a kind of computing chip, which includes the dma controller of the embodiment of the present application
100, at least one of dma controller 500 and dma controller 600.
The embodiment of the present application also provides a kind of movable equipment, which includes the DMA controls of the embodiment of the present application
At least one of device 100, dma controller 500 and dma controller 600 processed.
The movable equipment of the embodiment of the present application can be aircraft, it is particularly possible to be unmanned plane.
It should be understood that the circuit, sub-circuit, the division of subelement of each embodiment of the application are only schematical.This field is general
Logical technical staff is it is to be appreciated that each exemplary circuit, sub-circuit and the subelement that the embodiments described herein describes, energy
Enough rows again are split or combination.
In the above-described embodiments, can come wholly or partly by software, hardware, firmware or its arbitrary combination real
It is existing.When implemented in software, it can entirely or partly realize in the form of a computer program product.The computer program
Product includes one or more computer instructions.It is all or part of when loading on computers and executing the computer instruction
Ground is generated according to the flow or function described in the embodiment of the present application.The computer can be all-purpose computer, special purpose computer,
Computer network or other programmable devices.The computer instruction can store in a computer-readable storage medium, or
Person is transmitted from a computer readable storage medium to another computer readable storage medium, for example, the computer instruction
Wired (such as coaxial cable, optical fiber, digital subscriber can be passed through from a web-site, computer, server or data center
Line (Digital Subscriber Line, DSL)) or wireless (such as infrared, wireless, microwave etc.) mode to another website
Website, computer, server or data center are transmitted.The computer readable storage medium, which can be computer, to be deposited
Any usable medium taken is either set comprising data storages such as one or more usable mediums integrated server, data centers
It is standby.The usable medium can be magnetic medium (for example, floppy disk, hard disk, tape), optical medium (for example, high-density digital video
CD (Digital Video Disc, DVD)) or semiconductor medium (for example, solid state disk (Solid State Disk,
SSD)) etc..
It should be understood that " one embodiment " or " embodiment " that specification is mentioned in the whole text mean it is related with embodiment
A particular feature, structure, or characteristic is included at least one embodiment of the application.Therefore, occur everywhere in the whole instruction
" in one embodiment " or " in one embodiment " not necessarily refer to identical embodiment.In addition, these specific feature, knots
Structure or characteristic can in any suitable manner combine in one or more embodiments.
It should be understood that in the various embodiments of the application, size of the sequence numbers of the above procedures is not meant to execute suitable
The execution sequence of the priority of sequence, each process should be determined by its function and internal logic, the implementation without coping with the embodiment of the present application
Process constitutes any restriction.
It should be understood that in the embodiment of the present application, " B corresponding with A " indicates that B is associated with A, and B can be determined according to A.But
It should also be understood that determining that B is not meant to determine B only according to A according to A, B can also be determined according to A and/or other information.
It should be understood that the terms "and/or", only a kind of incidence relation of description affiliated partner, expression can deposit
In three kinds of relationships, for example, A and/or B, can indicate:Individualism A exists simultaneously A and B, these three situations of individualism B.
In addition, character "/" herein, it is a kind of relationship of "or" to typically represent forward-backward correlation object.
Those of ordinary skill in the art may realize that lists described in conjunction with the examples disclosed in the embodiments of the present disclosure
Member and algorithm steps can be realized with the combination of electronic hardware or computer software and electronic hardware.These functions are actually
It is implemented in hardware or software, depends on the specific application and design constraint of technical solution.Professional technician
Each specific application can be used different methods to achieve the described function, but this realization is it is not considered that exceed
Scope of the present application.
It is apparent to those skilled in the art that for convenience and simplicity of description, the system of foregoing description,
The specific work process of device and unit, can refer to corresponding processes in the foregoing method embodiment, and details are not described herein.
In several embodiments provided herein, it should be understood that disclosed systems, devices and methods, it can be with
It realizes by another way.For example, the apparatus embodiments described above are merely exemplary, for example, the unit
It divides, only a kind of division of logic function, formula that in actual implementation, there may be another division manner, such as multiple units or component
It can be combined or can be integrated into another system, or some features can be ignored or not executed.Another point, it is shown or
The mutual coupling, direct-coupling or communication connection discussed can be the indirect coupling by some interfaces, device or unit
It closes or communicates to connect, can be electrical, machinery or other forms.
The unit illustrated as separating component may or may not be physically separated, aobvious as unit
The component shown may or may not be physical unit, you can be located at a place, or may be distributed over multiple
In network element.Some or all of unit therein can be selected according to the actual needs to realize the mesh of this embodiment scheme
's.
In addition, each functional unit in each embodiment of the application can be integrated in a processing unit, it can also
It is that each unit physically exists alone, it can also be during two or more units be integrated in one unit.
The above, the only specific implementation mode of the application, but the protection domain of the application is not limited thereto, it is any
Those familiar with the art can easily think of the change or the replacement in the technical scope that the application discloses, and should all contain
It covers within the protection domain of the application.Therefore, the protection domain of the application should be based on the protection scope of the described claims.
Claims (42)
1. a kind of direct memory access dma controller, which is characterized in that including control access and read data path,
The control access includes reading control unit, and the reading control unit passes through the reading for generating read control signal
It controls the signal control read data path and reads the first data from external memory via external bus;
The read data path includes unwrapper unit, and the unwrapper unit is for unpacking first data, the reading
Internal storage unit is written via internal bus in the first data after unpacking by data path.
2. dma controller according to claim 1, which is characterized in that the unwrapper unit is specifically used for according to preset
Pack mode is solved, first data are unpacked.
3. dma controller according to claim 1, which is characterized in that the read data path further includes at the first clock
Unit is managed, first data for reading to the read data path are at the cross clock domain of line asynchronous first in, first out FIFO
Reason, the unwrapper unit are specifically used for that treated that the first data unpack to the cross clock domain that carries out FIFO.
4. dma controller according to claim 1, which is characterized in that the control access further includes DCU data control unit,
The DCU data control unit is used to read the first descriptor of first data, and the reading control unit is specifically used for according to institute
It states the first descriptor and generates the read control signal.
5. dma controller according to claim 4, which is characterized in that first descriptor includes the first field, described
The type that first field is used to indicate first data is immediate, one-dimensional 1D data or two-dimentional 2D data.
6. dma controller according to claim 4, which is characterized in that first descriptor includes the second field, described
Second field is used to indicate the priority of the corresponding task of first data.
7. dma controller according to claim 4, which is characterized in that first descriptor includes third field, described
Third field is used to indicate the solution pack mode of first data.
8. dma controller according to claim 4, which is characterized in that the DCU data control unit includes register, described
Register is used to deposit the priority of the corresponding task of the first data described in first descriptor, and the reading control unit is used
According to the priority generation read control signal in the register.
9. dma controller according to claim 1, which is characterized in that the dma controller further includes writing data path,
The control access further includes writing control unit, and the control unit of writing passes through described for generating write control signal
Write control signal controls write data access and reads the second data from the internal storage unit via the internal bus;
Write data access includes packaged unit, and the packaged unit is described to write for being packaged to second data
The external memory is written via the external bus in the second data after packing by data path.
10. dma controller according to claim 9, which is characterized in that write data access further includes at second clock
Unit is managed, for after the packaged unit is packaged second data, being carried out to second data after packing
The cross clock domain of asynchronous first in, first out FIFO is handled.
11. a kind of direct memory access dma controller, which is characterized in that including control access and data path is write,
The control access includes writing control unit, and the control unit of writing is write for generating write control signal, and by described
It controls signal control write data access and reads the second data from internal storage unit via internal bus;
Write data access includes packaged unit, and the packaged unit is described to write for being packaged to second data
External memory is written via external bus in the second data after packing by data path.
12. dma controller according to claim 11, which is characterized in that the packaged unit is specifically used for according to default
Packing pattern, second data are packaged.
13. dma controller according to claim 11, which is characterized in that write data access further includes second clock
Processing unit, for after the packaged unit is packaged second data, to second data after packing into
The cross clock domain of line asynchronous first in, first out FIFO is handled.
14. dma controller according to claim 11, which is characterized in that the control access further includes that data control is single
Member, the DCU data control unit are used to read the second descriptor of second data, and the control unit of writing is specifically used for root
The write control signal is generated according to second descriptor.
15. dma controller according to claim 14, which is characterized in that second descriptor includes the first field, institute
It is immediate, one-dimensional 1D data or two-dimentional 2D data to state the first field and be used to indicate the type of second data.
16. dma controller according to claim 14, which is characterized in that second descriptor includes the second field, institute
State the priority that the second field is used to indicate the corresponding task of second data.
17. dma controller according to claim 14, which is characterized in that second descriptor includes third field, institute
State the packing pattern that third field is used to indicate second data.
18. dma controller according to claim 14, which is characterized in that the DCU data control unit includes register, institute
Priority of the register for depositing the corresponding task of the second data described in second descriptor is stated, it is described to write control unit
For generating the write control signal according to the priority in the register.
19. dma controller according to claim 11, which is characterized in that the dma controller further includes reading data to lead to
Road,
The control access further includes reading control unit, and the reading control unit passes through described for generating read control signal
Read control signal controls the read data path and reads the first data from the external memory via the external bus;
The read data path includes unwrapper unit, and the unwrapper unit is for unpacking first data, the reading
The internal storage unit is written via the internal bus in the first data after unpacking by data path.
20. dma controller according to claim 19, which is characterized in that the read data path further includes the first clock
Processing unit, cross clock domain of first data for being used to read the read data path into line asynchronous first in, first out FIFO
Processing, the unwrapper unit are specifically used for that treated that the first data unpack to the cross clock domain that carries out FIFO.
21. a kind of method for reading data, which is characterized in that the method is executed by direct memory access dma controller, described
Dma controller includes control access and read data path, and the control access includes reading control unit, the read data path packet
Unwrapper unit is included, the method includes:
The reading control unit generates read control signal, and controls the read data path via outer by the read control signal
Portion's bus reads the first data from external memory;
The unwrapper unit unpacks first data, and the read data path is by the first data after unpacking via interior
Internal storage unit is written in portion's bus.
22. according to the method for claim 21, which is characterized in that the unwrapper unit solves first data
Packet, including:
The unwrapper unit unpacks first data according to preset solution pack mode.
23. according to the method for claim 21, which is characterized in that the read data path further includes that the processing of the first clock is single
Member, the method further include:
First data that the first clock processing unit reads the read data path are into line asynchronous first in, first out
The cross clock domain of FIFO is handled;
The unwrapper unit unpacks first data, including:
Treated that the first data unpack to the cross clock domain that carries out FIFO for the unwrapper unit.
24. according to the method for claim 21, which is characterized in that the control access further includes DCU data control unit, institute
The method of stating further includes:
The DCU data control unit reads the first descriptor of first data;
The reading control unit generates read control signal, including:
The reading control unit generates the read control signal according to first descriptor.
25. according to the method for claim 24, which is characterized in that first descriptor includes the first field, and described the
The type that one field is used to indicate first data is immediate, one-dimensional 1D data or two-dimentional 2D data.
26. according to the method for claim 24, which is characterized in that first descriptor includes the second field, and described the
Two fields are used to indicate the priority of the corresponding task of first data.
27. according to the method for claim 24, which is characterized in that first descriptor includes third field, and described the
Three fields are used to indicate the solution pack mode of first data.
28. according to the method for claim 24, which is characterized in that the DCU data control unit includes register, the side
Method further includes:
The register deposits the priority of the corresponding task of the first data described in first descriptor;
The reading control unit generates the read control signal according to first descriptor, including:
The reading control unit generates the read control signal according to the priority in the register.
29. according to the method for claim 21, which is characterized in that the dma controller further includes writing data path, described
Control access further includes writing control unit, and write data access includes packaged unit, and the method further includes:
The control unit of writing generates write control signal, and controls write data access via institute by the write control signal
It states internal bus and reads the second data from the internal storage unit;
The packaged unit is packaged second data, and write data access is by the second data after packing via institute
It states external bus and the external memory is written.
30. according to the method for claim 29, which is characterized in that write data access further includes that second clock processing is single
Member, the method further include:
The second clock processing unit is after the packaged unit is packaged second data, described in after packing
The cross clock domain of second data into line asynchronous first in, first out FIFO are handled.
31. a kind of method for writing data, which is characterized in that the method is executed by direct memory access dma controller, described
Dma controller includes control access and writes data path, and the control access includes writing control unit, write data access packet
Packaged unit is included, the method includes:
The control unit of writing generates write control signal, and controls write data access via interior by the write control signal
Portion's bus reads the second data from internal storage unit;
The packaged unit is packaged second data, and write data access is by the second data after packing via outer
External memory is written in portion's bus.
32. according to the method for claim 31, which is characterized in that the packaged unit beats second data
Packet, including:
The packaged unit is packaged second data according to preset packing pattern.
33. according to the method for claim 31, which is characterized in that write data access further includes that second clock processing is single
Member, the method further include:
The second clock processing unit is after the packaged unit is packaged second data, described in after packing
The cross clock domain of second data into line asynchronous first in, first out FIFO are handled.
34. according to the method for claim 31, which is characterized in that the control access further includes DCU data control unit, institute
The method of stating further includes:
The DCU data control unit reads the second descriptor of second data;
The control unit of writing generates write control signal, including:
The control unit of writing generates the write control signal according to second descriptor.
35. according to the method for claim 34, which is characterized in that second descriptor includes the first field, and described the
The type that one field is used to indicate second data is immediate, one-dimensional 1D data or two-dimentional 2D data.
36. according to the method for claim 34, which is characterized in that second descriptor includes the second field, and described the
Two fields are used to indicate the priority of the corresponding task of second data.
37. according to the method for claim 34, which is characterized in that second descriptor includes third field, and described the
Three fields are used to indicate the packing pattern of second data.
38. according to the method for claim 34, which is characterized in that the DCU data control unit includes register, the side
Method further includes:
The register deposits the priority of the corresponding task of the second data described in second descriptor;
The control unit of writing generates the write control signal according to second descriptor, including:
The control unit of writing generates the write control signal according to the priority in the register.
39. according to the method for claim 31, which is characterized in that the dma controller further includes read data path, described
Control access further includes reading control unit, and the read data path includes unwrapper unit, and the method further includes:
The reading control unit generates read control signal, and controls the read data path via institute by the read control signal
It states external bus and reads the first data from the external memory;
The unwrapper unit unpacks first data, and the read data path is by the first data after unpacking via institute
It states internal bus and the internal storage unit is written.
40. according to the method for claim 39, which is characterized in that the read data path further includes that the processing of the first clock is single
Member, the method further include:
First data that the first clock processing unit reads the read data path are into line asynchronous first in, first out
The cross clock domain of FIFO is handled;
The unwrapper unit unpacks first data, including:
Treated that the first data unpack to the cross clock domain that carries out FIFO for the unwrapper unit.
41. a kind of integrated circuit, which is characterized in that including described in any one of claims 1 to 10 dma controller and/or
Dma controller described in any one of claim 11 to 20.
42. a kind of movable equipment, which is characterized in that including described in any one of claims 1 to 10 dma controller and/
Or the dma controller described in any one of claim 11 to 20.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/CN2017/108644 WO2019084789A1 (en) | 2017-10-31 | 2017-10-31 | Direct memory access controller, data reading method, and data writing method |
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| Publication Number | Publication Date |
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| CN108701102A true CN108701102A (en) | 2018-10-23 |
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| CN201780010826.8A Pending CN108701102A (en) | 2017-10-31 | 2017-10-31 | Direct memory access controller, method for reading data and method for writing data |
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| CN (1) | CN108701102A (en) |
| WO (1) | WO2019084789A1 (en) |
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| WO2019084789A1 (en) | 2019-05-09 |
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Application publication date: 20181023 |