WO2019084789A1

WO2019084789A1 - Direct memory access controller, data reading method, and data writing method

Info

Publication number: WO2019084789A1
Application number: PCT/CN2017/108644
Authority: WO
Inventors: 任子木; 韩彬
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2017-10-31
Filing date: 2017-10-31
Publication date: 2019-05-09
Also published as: CN108701102A

Abstract

A DMA controller, a data reading method, and a data writing method. The DMA controller comprises a control path and a data reading path. The control path comprises a read control unit, configured to generate a read control signal, and control the data reading path by means of the read control signal to read first data from an external memory via an external bus. The data reading path comprises an unpacking unit, configured to unpack the first data, and the data reading path writes the unpacked first data into an internal storage unit by means of an internal bus. By providing the control path and the data reading path in the DMA controller, the DMA controller performs unpacking on the data by means of the unpacking unit at the same time that the data reading path reads the data from the external memory, so that the DMA controller performs an unpacking operation during data transfer, and performs parallel processing so as to improve the data processing speed and improve the performance of chips.

Description

Direct memory access controller, data reading method, and data writing method

Copyright statement

The disclosure of this patent document contains material that is subject to copyright protection. This copyright is the property of the copyright holder. The copyright owner has no objection to the reproduction of the patent document or the patent disclosure in the official records and files of the Patent and Trademark Office.

Technical field

The present application relates to the field of data processing, and in particular, to a direct memory access (DMA) controller, a data reading method, and a data writing method.

Background technique

With the rapid development of the chip industry, the functional complexity of the chip is getting higher and higher. The chip typically includes a DMA controller and a data processing unit for data processing. Nowadays, the functions of the DMA controller on the market are relatively simple, and the main function is to complete the data movement operation. Taking read data as an example, if the chip needs to read and process image data of different bit width pixels, the chip usually sets a preprocessing module in the data processing unit to complete the unpacking operation of the image data. The unpacking operation is to unpack the compactly stored image data in the memory into a format that is easy to use by the data processing unit. For example, unpacking image data in 8-bit (bit), 10-bit, 12-bit or 16-bit bit width compact storage in DDR is Stored in regularity in 16-bit or 32-bit width. In the existing solution, the unpacking operation is performed by the preprocessing module of the data processing unit. Therefore, the DMA controller moves the data and the preprocessing module unpacks the data in series. In other words, if you want to process a piece of image data, you need the DMA controller to complete the data transfer first, and then the pre-processing module can complete the unpacking operation, which cannot be performed in parallel. This makes the chip process data very slow.

Summary of the invention

The present application provides a direct memory access controller, a data reading method, and a data writing method, which can improve data processing speed and improve chip performance.

In a first aspect, a direct memory access DMA controller is provided, comprising a control path and a read data path, the control path comprising a read control unit, the read control unit for generating a read control And generating, by the read control signal, the read data path to read first data from an external memory via an external bus; the read data path includes an unpacking unit, the unpacking unit is configured to The data is unpacked, and the read data path writes the unpacked first data to the internal storage unit via the internal bus.

The first aspect of the DMA controller sets a control path and a read data path therein, and the read data path reads data from the external memory while unpacking the data through the unpacking unit, so that the DMA controller moves the data. At the same time, the unpacking operation is performed, and the two processes in parallel can improve the data processing speed and improve the performance of the chip.

In a second aspect, a direct memory access DMA controller is provided, comprising a control path and a write data path, the control path comprising a write control unit for generating a write control signal and by the write control Signaling the write data path to read second data from an internal memory unit via an internal bus; the write data path includes a packing unit, the packing unit for packaging the second data, the write data path The packed second data is written to the external memory via the external bus.

The DMA controller of the second aspect sets the control path and the write data path therein, and writes the data path to write data to the external memory, and packs the data through the packing unit, so that the DMA controller performs data transfer simultaneously. The packaging operation, which is processed in parallel, can improve the data processing speed and improve the performance of the chip.

In a third aspect, a data reading method is provided, the method being performed by a direct memory access DMA controller, the DMA controller comprising a control path and a read data path, the control path comprising a read control unit, the reading The data path includes an unpacking unit, the method comprising: the read control unit generating a read control signal, and controlling, by the read control signal, the read data path to read first data from an external memory via an external bus; The packet unit unpacks the first data, and the read data path writes the unpacked first data to the internal storage unit via the internal bus.

In a fourth aspect, a data writing method is provided, the method being performed by a direct memory access DMA controller, the DMA controller comprising a control path and a write data path, the control path comprising a write control unit, the writing The data path includes a packing unit, the method comprising: the write control unit generating a write control signal, and controlling, by the write control signal, the write data path to read second data from an internal storage unit via an internal bus; The unit packs the second data, and the write data path writes the packaged second data to the outside via an external bus Save.

In a fifth aspect, an integrated circuit is provided, comprising the DMA controller of the first aspect of the invention and/or the DMA controller of the second aspect.

In a sixth aspect, a mobile device is provided, comprising the DMA controller of the first aspect of the invention and/or the DMA controller of the second aspect.

DRAWINGS

1 is a schematic block diagram of a DMA controller of one embodiment of the present application.

2 is a schematic diagram of a data unpacking operation of an embodiment of the present application.

3 is a schematic diagram of an implementation of a descriptor cache in accordance with an embodiment of the present application.

4 is a schematic diagram of a descriptor format of an embodiment of the present application.

FIG. 5 is a schematic block diagram of a DMA controller of another embodiment of the present application.

6 is a schematic block diagram of a DMA controller of another embodiment of the present application.

FIG. 7 is a schematic flowchart of a data reading method according to an embodiment of the present application.

FIG. 8 is a schematic flowchart of a data writing method according to an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

All technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention applies, unless otherwise defined. The terminology used herein is for the purpose of describing particular embodiments, and is not intended to be limiting.

Embodiments of the present application provide a DMA controller having a read data function. 1 is a schematic block diagram of a DMA controller 100 in accordance with one embodiment of the present application. As shown in FIG. 1, DMA controller 100 includes a control path 110 and a read data path 120. The control path 110 can include a read control unit 112 for generating a read control signal and controlling the read data path 120 to read the first data from the external memory 220 via the external bus 210 by a read control signal. The read data path 120 can include a depacketizing unit 122 for unpacking the first data, and the read data path 120 writing the unpacked first data to the internal storage unit 240 via the internal bus 230.

It should be understood that, in the embodiment of the present application, the external bus 210 may be an Advanced eXtensible Interface (AXI) bus, or may be a bus specified by other protocols. The external memory 220 can be double data rate SDRAM (Double Data Rate SDRAM, DDR SDRAM), or simply DDR memory, where SDRAM is a Synchronous Dynamic Random Access Memory. The internal bus 230 can be a crossbar switch (CROSSBAR) bus. The specific implementation forms of the external bus 210, the external memory 220, the internal bus 230, the internal storage unit 240, and the like are not limited in the embodiment of the present application.

It should be understood that, as shown in FIG. 1 , the first embodiment of the present application can read the first data from the external memory 220 through the external bus 210 through the external read unit 126 of the read data path 120 , which is not limited in this embodiment of the present application.

The DMA controller of the embodiment of the present application sets a control path and a read data path therein, and the read data path reads data from the external memory while unpacking the data through the unpacking unit, so that the DMA controller moves the data. At the same time, the unpacking operation is performed, and the two are processed in parallel, which can improve the data processing speed and improve the performance of the chip.

In addition, since the DMA controller has unpacked the data, the downstream unit of the DMA controller does not need to unpack the original data, which increases the flexibility of the downstream unit of the DMA controller, so that the DMA controller can be used in A variety of different application scenarios, such as big-end storage, small-end storage, and so on.

Optionally, as shown in FIG. 1, the read data path 120 may further include a first clock processing unit 124 for performing asynchronous first in first out (FIFO) on the first data read by the read data path 120. The cross-clock domain processing, the unpacking unit 122 is specifically configured to unpack the first data processed by the FIFO across the clock domain. The first clock processing unit 124 can use FIFO technology to synchronize data originating from different clock domains.

The first clock processing unit 124 may perform the cross-clock domain processing of the FIFO from the external memory 220 (for example, may be DDR memory), and then send it to the unpacking unit 122. It should be understood that in practical applications, in order to save the bandwidth of the DDR memory, the data, especially the pixel value of the image, is generally stored compactly in the DDR memory. Images of different bit width pixels are stored in different formats in DDR memory. In order to facilitate the data processing of the subsequent unit, the unpacking unit 122 of the embodiment of the present application adds 0 to the high bit of the original pixel value and expands the pixel bit width to 16 bit or 32 bit. That is, the unpacking unit 122 needs to perform conversion of the data format.

Optionally, the unpacking unit 122 may unpack the first data according to the unpacking mode preset by the system. The unpacking mode supported by the embodiments of the present application may include a direct mode, a low word mode, a low bit halfword mode, a parity column split mode, a one-bank copy mode, a high word mode, a high halfword mode, and two blocks ( At least one of two-bank replication modes, and the embodiment of the present application Not limited to this.

The direct mode is to output the data as it is without formatting. The low word mode uses a low word of one word (including 32 bits) to store one pixel value and a high bit to zero. In this way, 8-bit, 10-bit, 12-bit, and 16-bit wide pixels can be expanded to 32 bits. The lower halfword mode uses a lower half of the word to store one pixel value and a high bit to zero. In this way, 8-bit, 10-bit, and 12-bit wide pixels can be expanded to 16 bits. The high word mode uses a word high bit to store a pixel value and a low bit zero. The upper halfword mode uses a high word of half a word to store one pixel value and a low bit to zero. In the one-bank copy mode, each bank is a group, and the data is copied into 16 copies, and each data is placed in one bank. In the two-bank copy mode, every two banks are grouped, and the data is copied into 8 copies, and each data is placed in two banks. The parity column split mode is to divide the data into two parts, which are respectively stored in the even bank and the odd bank. For example, the lower 8 bits of data are stored in the even bank, and the upper 8 bits of data are stored in the odd bank. This is not limited.

The pixel width that can be supported by the embodiment of the present application may include 8 bits, 10 bits, 12 bits, and 16 bits, and is not limited thereto.

2 is a schematic diagram of a data unpacking operation of an embodiment of the present application. As shown in FIG. 2, the data is stored in the external memory in a 12-bit pixel format, including data of pixels 0-pixel 9. In this embodiment, the low-order half-word mode is used for unpacking. After unpacking, each pixel is 16 bits, and the high bit is inserted with 0 to fill. The Most Significant Bit (MSB) and the Least Significant Bit (LSB) of the data before and after unpacking are shown in Figure 2, respectively. Therefore, the embodiment of the present application does not need to store image data including a large amount of redundant information (for example, the data after unpacking in FIG. 2) in the external memory, but stores the data before the unpacking of FIG. 2, thereby saving memory bandwidth. .

Alternatively, the unpacking unit 122 may include a 3-stage pipeline.

The first level pipeline can unpack data of different bit width pixels (for example, the first data) into a certain bit width, for example, 16 bits. In a specific example, the input to the first level pipeline is 128 bits of data. For 8-bit pixels, one beat data includes 16 pixels; for 10-bit pixels, one beat data includes 12 pixels; for 12-bit pixels, one beat data includes 10 pixels, and the first-stage pipeline unpacks data, and the data width is wide. It is 16bit.

The second level pipeline can padding the data. The padding operation expands a tile having a width and height of less than 256×256 into a tile of 256×256, wherein the extended region complements 0 pixels.

The third-level pipeline can complete half-word to word conversion and low-to-high conversion. Because the first The data after the unpacking of the first-level pipeline is the low-order halfword mode. If the current unpacking mode requires other modes, the data format needs to be converted.

It should be understood that the unpacking unit includes a level 3 pipeline, which is merely exemplary, and is not intended to limit the embodiments of the present application.

Optionally, as shown in FIG. 1, the control path 110 may further include a data control unit 114. The data control unit 114 can be configured to read a first descriptor of the first data, and the read control unit 112 is specifically configured to generate a read control signal according to the first descriptor.

Alternatively, as shown in FIG. 1, the data control unit 114 may read the first descriptor of the first data from the core 260 via the core bus 250.

The descriptor of the embodiment of the present application may be used to indicate a priority, where there are multiple situations to be considered. For example, the first descriptor may include a first field, and the first field is used to indicate that the type of the first data is an immediate number, 1D. Data or 2D data. The immediate priority is greater than the priority of one-dimensional (1D) data and two-dimensional (2D) data. Generally, the amount of data of 1D data and 2D data transmitted by the 1D task and the 2D task are relatively large. In the course of 1D data and 2D data transmission, if an immediate number of descriptors are pushed into the data control unit 114, the task of the immediate data can be executed in advance according to the descriptor. Thus, the DMA controller of the embodiment of the present application can improve the execution efficiency of the immediate data.

In a specific example, the DMA controller of the embodiments of the present application can support an outstanding high efficiency data receiving structure. The data receiving structure can make full use of the outstanding resources to achieve efficient data reception in the case of a small cache. For example, in the case of outstanding 8, the data receiving structure has 8 IDentifiers (IDs) 0 to 7 that can be utilized. Use an 8-bit register (such as the register variable busy) to indicate the current ID usage. The bit is low, indicating that the ID corresponding to the bit is not used. The bit is high, indicating that the ID corresponding to the bit is waiting to be read back. data. The data receiving structure maintains a register file. Each row of the register file corresponds to an ID, and stores a cache storage address corresponding to the current ID. Whenever the DMA controller reads back valid data from the external memory via the external bus, according to the ID of the data, the corresponding register file is queried, the cache address of the data is obtained, and then the data is buffered to the corresponding address. At the same time, the address data in the register file is incremented by one. If the data currently read back is the last data of its burst, the corresponding register of the ID is set to 0 for use by other transmissions.

Another example: DMA controller supports outstanding 8, if there is currently an empty ID, you can make Use this ID to read and write immediate data. The amount of immediate data is usually small, for example 128 bits, and only a single floating point operation is required to complete the transfer. The DMA controller of the embodiment of the present application can greatly improve the utilization of the oustanding resource under the premise of a small cache resource consumption, thereby improving the reading efficiency of the DMA controller.

In a specific example, the first descriptor may include a second field, and the second field is used to indicate the priority of the task corresponding to the first data. Specifically, the description of each 1D data or the descriptor of the 2D data may be configured with a 3-bit second field for indicating the priority of the data task. In a specific example, the priority can be divided into 8 levels. The control path selects the task with the highest priority from the descriptor cache for execution. If multiple tasks have the same priority, the task that is first pushed into the descriptor cache is selected for execution.

Alternatively, the data control unit 114 may include a register for registering the priority of the task corresponding to the first data in the first descriptor, and the read control unit 112 is configured to generate the read control signal according to the priority in the register. In one example, a specific implementation of the descriptor cache can be as follows. 3 is a schematic diagram of one implementation of a descriptor cache. As shown in Figure 3, a register bank is set up. The set of registers has a total of 7 rows, and each row of the register corresponds to a descriptor in the descriptor cache. For example, the 0th line corresponds to the descriptor of the task corresponding to the data of the addresses 0 to 9, the 1st line corresponds to the descriptor of the task corresponding to the data of the addresses 10 to 19, and so on. Each row of the register may include 3 fields (field A, field B, and field C) total 7 bits, and field A (used field) occupies 1 bit, which is used to indicate whether the storage space of the row of the register has a descriptor, and the field A value is 1 indicates that the storage space of the row of the register has a descriptor. Field B (pri1 field) occupies 3 bits, indicating the absolute value of the priority carried in the descriptor of the data (ie, the value of the pri1 field is assigned by the pri field of the descriptor header). Field C (pri2 field) occupies 3 bits and is used to indicate the order in which tasks are pushed into the descriptor cache, ensuring that tasks of the same priority are first-in, first-out. When the descriptor is just pushed in, the value of the pri2 field of the descriptor is set to the register variable main, and the value of the pri2 field is decremented by 1. Each time a descriptor is taken from the descriptor cache, the value of the pri2 field of the remaining descriptor is set. plus 1. =

It should be understood that the above is only an example of priority, and is not intended to limit the embodiments of the present application.

Optionally, the first descriptor of the embodiment of the present application may include a third field, where the third field is used to indicate an unpacking mode of the first data.

4 is a schematic diagram of a descriptor format of an embodiment of the present application. This descriptor is a descriptor of 2D data. The first halfword (16bit) of the descriptor is the header dscrp_head of the descriptor, which indicates the mode mode[1:0] of the data (dscrp_head[15:14]), the priority of the task corresponding to the data. Pri[2:0](dscrp_head[13:11]), unpacking mode unpack_mode[2:0](dscrp_head[10:8]), pixel bit width pixel_width[2:0](dscrp_head[7:5]) The descriptor length [3:0]dscrp_len(dscrp_head[4:1]) and the transfer direction direc[0](dscrp_head[0]). The mode mode of the data may be an immediate data, 1D data, or 2D data. For example, the mode of the data in this example is 2D data. The unpacking mode unpack_mode may be one of the aforementioned various unpacking modes. The transfer direction direc is the read direction or the write direction. Dscrp_id[11:0] is used to indicate the ID of this descriptor. Ext_addr (including ext_addr[15:0] and ext_addr[31:16]) is used to indicate the data address of the external memory. Trans_len[15:0] is used to indicate the transmission length. Toggle_num[15:0] indicates the number of times the current operation needs to be repeated. Trans_width[15:0] and trans_stride[15:0] are used to indicate the 2D area. These two parameters are used to calculate the next start address when wrapping. Port_cfg1[15:0] and port_cfg2[15:0] correspond to the number of two internal memory locations, respectively, for storing the upper 8 bits and lower 8 bits of the data. The three parameters padding_en[0], vld_data_height[6:0], and vld_data_width[6:0] are used for the padding operation. For example, padding_en is 1 for padding, 0 is for padding, vld_data_height[6: 0] and vld_data_width[6:0] are used to define the height and width of the unfilled area.

Optionally, the DMA controller of the embodiment of the present application may further include a write data path, and the control path may further include a write control unit, where the write control unit is configured to generate a write control signal, and control the write data path via the internal bus through the write control signal. The second data is read from the internal storage unit; the write data path may include a packing unit, the packing unit is configured to package the second data, and the write data path writes the packed second data to the external memory via the external bus.

Optionally, the write data path may further include a second clock processing unit, configured to perform cross-clock domain processing of the asynchronous FIFO on the packed second data after the packing unit packages the second data.

The related operations on writing data paths will be detailed below.

The embodiment of the present application also provides a DMA controller having a write data function. FIG. 5 is a schematic block diagram of a DMA controller 500 of another embodiment of the present application. As shown in FIG. 5, the DMA controller 500 includes a control path 510 and a write data path 520. The control path 510 can include a write control unit 512 for generating a write control signal and controlling the write data path 520 to read the second data from the internal memory unit 240 via the internal bus 230 via a write control signal. The write data path 520 can include a packing unit 522 for packaging the second data, and the write data path 520 writing the packed second data to the external memory 220 via the external bus 210.

It should be understood that, as shown in FIG. 5, the embodiment of the present application may specifically write the packaged second data to the external memory 220 via the external bus 210 through the external write unit 526 of the write data path 520, which is not limited in this embodiment of the present application. .

The DMA controller of the embodiment of the present application sets a control path and a write data path therein, and the write data path writes data to the external memory while packing the data through the packing unit, so that the DMA controller moves the data at the same time. The packaging operation is performed in parallel, which can improve the data processing speed and improve the performance of the chip.

In addition, since the DMA controller packs the data, the upstream unit of the DMA controller does not need to pack the original data, which increases the flexibility of the upstream unit of the DMA controller, so that the DMA controller can be used in many different ways. Application scenario.

Optionally, as shown in FIG. 5, the write data path 520 may further include a second clock processing unit 524, configured to perform asynchronous FIFO on the packaged second data after the packing unit 522 packages the second data. Cross-clock domain processing.

Optionally, the packaging unit 522 is specifically configured to package the second data according to the preset packaging mode. Corresponding to the unpacking mode, the packing modes supported by the embodiments of the present application may include a direct mode, a low word mode, a low halfword mode, a parity column split mode, a one-bank copy mode, a high word mode, a high halfword mode, and At least one of the two-bank copy modes, and the embodiment of the present application is not limited thereto.

The working principle and the flow of the unpacking unit 522 of the embodiment of the present application may be similar to the principle of the unpacking unit of the embodiment of the present application, and the process is reversed, and details are not described herein.

Optionally, as an embodiment, as shown in FIG. 5, the control path 510 may further include a data control unit 514. The data control unit 514 is configured to read a second descriptor of the second data, and the write control unit 512 is specifically configured to generate a write control signal according to the second descriptor.

Alternatively, as an embodiment, as shown in FIG. 5, the data control unit 514 can read the second descriptor of the second data from the core 260 via the core bus 250.

Optionally, the second descriptor may include a first field, where the first field is used to indicate that the type of the second data is immediate, one-dimensional 1D data, or two-dimensional 2D data. Optionally, the second descriptor may include a second field, where the second field is used to indicate a priority of the task corresponding to the second data. Optionally, the second descriptor may include a third field, where the third field is used to indicate a packing mode of the second data (the third field corresponding to the first descriptor is used to indicate an unpacking mode of the first data).

The format of the second descriptor of the embodiment of the present application may be the same as or the same as the format of the first descriptor. like.

It should be understood that if there are both a read operation and a write operation for the same data, two operations (or two tasks) can be described using only one descriptor.

Optionally, as an embodiment, the data control unit 514 may include a register for registering priorities of tasks corresponding to the second data in the second descriptor, and the write control unit 512 is configured to generate according to priorities in the registers. Write control signals.

Optionally, as an embodiment, the DMA controller 500 may further include a read data path, and the control path may further include a read control unit, and the read control unit may be configured to generate a read control signal and control the read data path via the read control signal. The external bus reads the first data from the external memory; the read data path may include an unpacking unit, the unpacking unit may be configured to unpack the first data, and the read data path writes the unpacked first data via the internal bus Internal storage unit.

Optionally, as an embodiment, the read data path may further include a first clock processing unit, configured to perform cross-clock domain processing of the asynchronous FIFO on the first data read by the read data path, where the unpacking unit is specifically configured to perform The first data processed by the FIFO across the clock domain is unpacked.

It should be understood that for a DMA controller including both a read data path and a write data path, the registers in the data control unit may register the priority of the task corresponding to the read data (eg, the first data) and register the write to be written. The priority of the task corresponding to the incoming data (eg second data). In other words, the read data and the write data can share the same register. Of course, the read data and the write data may also be set differently, which is not limited in this embodiment of the present application.

The following is a specific example to illustrate the case where the DMA controller includes both a read data path and a write data path. FIG. 6 is a schematic block diagram of a DMA controller 600 of another embodiment of the present application. As shown in FIG. 6, DMA controller 600 includes control path 610, read data path 620, and write data path 630.

Control path 610 can include read control unit 612 and write control unit 614. The read control unit 612 is configured to generate a read control signal and control the read data path 620 to read data from the external memory 220 via the external bus 210 by a read control signal. The write control unit 614 is configured to generate a write control signal and control the write data path 630 to read data from the internal memory unit 240 via the internal bus 230 by a write control signal. Control path 610 can also include a data control unit 616. Data control unit 616 can be used to read descriptors of the data. The data control unit 616 can include an interface (crf_if) module, which is an interface module of the data control unit 616 and the core bus 250. The data control unit 616 may also include a read immediate data cache (im_cache) module and a descriptor format check. (dscrp_check) module and descriptor distribution (dscrp_distribute) module. The im_cache module is a module for caching immediate data. The dscrp_check module is a module for checking the descriptor format. The dscrp_distribute module distributes the descriptor to the read immediate task cache (fifo_im_r) module, the write immediate task cache (fifo_im_w) module, the read 1D2D task cache (pri_1d2d_r) module, and the write 1D2D task cache (pri_1d2d_w) module according to the contents of the descriptor. These four modules. The fifo_im_r module is used to cache read immediate tasks, the fifo_im_w module is used to cache write immediate tasks, the pri_1d2d_r module is used to cache read 1D tasks and 2D tasks, and has task priority function. The pri_1d2d_w module is used to cache write 1D tasks and 2D tasks. And has a task priority function. The read control unit 612 generates a read control signal based on the descriptors in the fifo_im_r module or the pri_1d2d_r module. The write control unit 614 generates a write control signal based on the descriptors in the fifo_im_w module or the pri_1d2d_w module.

The read data path 620 can include the external read unit 626 reading data from the external memory 220 via the external bus 210; the read data path 620 can also include a first clock processing unit 624 for asynchronously FIFOing the data read by the read data path 620. The cross-clock domain processing; the read data path 620 further includes an unpacking unit 622 for writing data to the internal storage unit 240 via the internal bus 230 after unpacking the data.

The write data path 630 can include a packing unit 632 for packaging data read from the internal storage unit 240 via the internal bus 230 by the write data path 630; the write data path 630 can also include a second clock processing unit 634 for The packed data of the packing unit 632 performs cross-clock domain processing of the asynchronous FIFO; the write data path 630 may further include an external write unit 626 for writing the packed and cross-clock domain processed data to the external memory 220 via the external bus 210.

It should be understood that the DMA controller 600 shown in FIG. 6 is only an example of the embodiment of the present application and is not limited thereto.

The DMA controller of the embodiment of the present application has been described above, and the data reading method and the data writing method corresponding thereto are respectively described in detail below.

FIG. 7 is a schematic flowchart of a data reading method 700 according to an embodiment of the present application. Method 700 can be performed by a DMA controller that includes a control path and a read data path, the control path including a read control unit, and the read data path including an unpacking unit. As shown in FIG. 7, method 700 can include the following steps.

S710. The read control unit generates a read control signal, and controls the read data path to read the first data from the external memory via the external bus through the read control signal.

S720. The unpacking unit unpacks the first data.

S730. The read data path writes the unpacked first data to the internal storage unit via the internal bus.

In the data reading method of the embodiment of the present application, by setting a control path and a read data path inside the DMA controller, the read data path reads data from the external memory and unpacks the data through the unpacking unit, so that the DMA control The device performs the unpacking operation while the data is being moved, and the two processes in parallel can improve the data processing speed and improve the performance of the chip.

Optionally, as an embodiment, the S720 unpacking unit unpacking the first data may include: the unpacking unit unpacks the first data according to the preset unpacking mode.

Optionally, as an embodiment, the read data path may further include a first clock processing unit, and the method 700 may further include: the first clock processing unit performs asynchronous first-in first-out FIFO on the first data read by the read data path. The clock domain processing; the S720 unpacking unit unpacking the first data may include: the unpacking unit unpacking the first data after performing the cross-clock domain processing of the FIFO.

Optionally, as an embodiment, the control path may further include a data control unit, and the method 700 may further include: the data control unit reads the first descriptor of the first data; S710, the read control unit generates the read control signal, which may include The read control unit generates a read control signal based on the first descriptor.

Optionally, as an embodiment, the first descriptor includes a first field, where the first field is used to indicate that the type of the first data is immediate, one-dimensional 1D data, or two-dimensional 2D data.

Optionally, as an embodiment, the first descriptor includes a second field, where the second field is used to indicate a priority of the task corresponding to the first data.

Optionally, as an embodiment, the first descriptor includes a third field, where the third field is used to indicate an unpacking mode of the first data.

Optionally, as an embodiment, the data control unit may include a register, and the method 700 may further include: registering a priority of a task corresponding to the first data in the first descriptor; and the read control unit generates a read according to the first descriptor. The control signal may include: the read control unit generates a read control signal according to a priority in the register.

Optionally, as an embodiment, the DMA controller further includes a write data path, the control path may further include a write control unit, the write data path may include a packing unit, and the method 700 may further include: the write control unit generates a write control signal, and The write data path is controlled by the write control signal to read the second data from the internal memory unit via the internal bus; the packing unit packs the second data, and the write data path writes the packed second data to the external memory via the external bus.

Optionally, as an embodiment, the write data path may further include a second clock processing unit, and the method 700 may further include: after the second clock processing unit packs the second data, the second clock processing unit performs the packaged second data. Cross-clock domain processing of asynchronous first-in, first-out FIFOs.

FIG. 8 is a schematic flowchart of a data writing method 800 according to an embodiment of the present application. Method 800 can be performed by a DMA controller that includes a control path including a write control unit and a write data path including a packing unit, and method 800 can include the following steps.

S810, the write control unit generates a write control signal, and controls the write data path to read the second data from the internal storage unit via the internal bus through the write control signal.

S820. The packaging unit packages the second data.

S830. The write data path writes the packed second data to the external memory via an external bus.

In the data writing method of the embodiment of the present application, by setting a control path and a write data path inside the DMA controller, the write data path writes data to the external memory, and packs the data through the packing unit, so that the DMA controller is The data is moved at the same time as the packaging operation, and the two are processed in parallel, which can improve the data processing speed and improve the performance of the chip.

Optionally, as an embodiment, the S820 packaging unit packing the second data may include: the packaging unit packing the second data according to the preset packaging mode.

Optionally, as an embodiment, the write data path may further include a second clock processing unit, and the method 800 may further include: after the second clock processing unit packs the second data, the second clock processing unit performs the packed second data. Cross-clock domain processing of asynchronous first-in, first-out FIFOs.

Optionally, as an embodiment, the control path may further include a data control unit, and the method 800 may further include: the data control unit reads the second descriptor of the second data; and the S810 write control unit generates the write control signal, which may include: The write control unit generates a write control signal based on the second descriptor.

Optionally, as an embodiment, the second descriptor includes a first field, where the first field is used to indicate that the type of the second data is immediate, one-dimensional 1D data, or two-dimensional 2D data.

Optionally, as an embodiment, the second descriptor includes a second field, where the second field is used to indicate a priority of the task corresponding to the second data.

Optionally, as an embodiment, the second descriptor includes a third field, where the third field is used to indicate a packing mode of the second data.

Optionally, as an embodiment, the data control unit may include a register, and the method 800 may further include: registering a priority of a task corresponding to the second data in the second descriptor; and writing control The unit generates a write control signal according to the second descriptor, and may include: the write control unit generates a write control signal according to the priority in the register.

Optionally, as an embodiment, the DMA controller may further include a read data path, the control path may further include a read control unit, the read data path may include a unpacking unit, and the method 800 may further include: the read control unit generates a read control signal And controlling the read data path to read the first data from the external memory via the external bus through the read control signal; the unpacking unit unpacks the first data, and the read data path writes the unpacked first data to the internal via the internal bus Storage unit.

Optionally, as an embodiment, the read data path may further include a first clock processing unit, and the method 800 may further include: the first clock processing unit performs asynchronous first-in first-out FIFO on the first data read by the read data path. The clock domain processing; the unpacking unit unpacking the first data may include: the unpacking unit unpacking the first data after performing the cross-clock domain processing of the FIFO.

The specific flow of the data reading method and the data writing method in the embodiment of the present application has been described in detail in the foregoing description of the DMA controller, and details are not described herein again.

The embodiment of the present application further provides an integrated circuit including at least one of the DMA controller 100, the DMA controller 500, and the DMA controller 600 of the embodiment of the present application.

It should be understood that the integrated circuit of the embodiment of the present application may be an Application Specific Integrated Circuit (ASIC) or a Field-Programmable Gate Array (FPGA).

The embodiment of the present application further provides a computing chip, which includes at least one of the DMA controller 100, the DMA controller 500, and the DMA controller 600 of the embodiment of the present application.

The embodiment of the present application further provides a mobile device, which includes at least one of the DMA controller 100, the DMA controller 500, and the DMA controller 600 of the embodiment of the present application.

The mobile device of the embodiment of the present application may be an aircraft, and in particular may be a drone.

It should be understood that the division of circuits, sub-circuits, and sub-units of various embodiments of the present application is merely illustrative. Those of ordinary skill in the art will appreciate that the circuits, sub-circuits, and sub-units of the various examples described in the embodiments disclosed herein can be further separated or combined.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented in software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, the processes or functions described in accordance with embodiments of the present application are generated in whole or in part. The computer can be a general purpose computer, a special purpose computer, or a computer network Network, or other programmable device. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be from a website site, computer, server or data center Transmission to another website site, computer, server, or data center by wire (eg, coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (eg, infrared, wireless, microwave, etc.). The computer readable storage medium can be any available media that can be accessed by a computer or a data storage device such as a server, data center, or the like that includes one or more available media. The usable medium may be a magnetic medium (for example, a floppy disk, a hard disk, a magnetic tape), an optical medium (for example, a high-density digital video disc (DVD)), or a semiconductor medium (for example, a solid state hard disk (Solid State Disk, SSD)) and so on.

It is to be understood that the phrase "one embodiment" or "an embodiment" or "an embodiment" or "an embodiment" means that the particular features, structures, or characteristics relating to the embodiments are included in at least one embodiment of the present application. Thus, "in one embodiment" or "in an embodiment" or "an" In addition, these particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

It should be understood that, in the various embodiments of the present application, the size of the sequence numbers of the foregoing processes does not mean the order of execution sequence, and the order of execution of each process should be determined by its function and internal logic, and should not be applied to the embodiment of the present application. The implementation process constitutes any limitation.

It should be understood that in the embodiment of the present application, "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B from A does not mean that B is only determined based on A, and that B can also be determined based on A and/or other information.

It should be understood that the term "and/or" herein is merely an association relationship describing an associated object, indicating that there may be three relationships, for example, A and/or B, which may indicate that A exists separately, and A and B exist simultaneously. There are three cases of B alone. In addition, the character "/" in this article generally indicates that the contextual object is an "or" relationship.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps of the various examples described in connection with the embodiments disclosed herein can be implemented in electronic hardware or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the solution. A person skilled in the art can use different methods to implement the described functions for each particular application, but such implementation should not be considered to be beyond the scope of the present application.

A person skilled in the art can clearly understand that for the convenience and brevity of the description, the specific working process of the system, the device and the unit described above can refer to the corresponding process in the foregoing method embodiment, and details are not described herein again.

In the several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the device embodiments described above are merely illustrative. For example, the division of the unit is only a logical function division. In actual implementation, there may be another division manner, for example, multiple units or components may be combined or Can be integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or discussed may be an indirect coupling or communication connection through some interface, device or unit, and may be in an electrical, mechanical or other form.

The units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed to multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

The foregoing is only a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto, and any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application. It should be covered by the scope of protection of this application. Therefore, the scope of protection of the present application should be determined by the scope of the claims.

Claims

A direct memory access DMA controller characterized by including a control path and a read data path,

The control path includes a read control unit for generating a read control signal, and controlling, by the read control signal, the read data path to read first data from an external memory via an external bus;

The read data path includes a depacket unit for unpacking the first data, and the read data path writes the unpacked first data to an internal storage unit via an internal bus.
The DMA controller according to claim 1, wherein the unpacking unit is specifically configured to unpack the first data according to a preset unpacking mode.
The DMA controller according to claim 1, wherein said read data path further comprises a first clock processing unit for performing asynchronous first-in first-out FIFO on said first data read by said read data path The cross-clock domain processing is used to unpack the first data processed by the cross-clock domain of the FIFO.
The DMA controller according to claim 1, wherein said control path further comprises a data control unit, said data control unit is operative to read a first descriptor of said first data, said read control unit Specifically, the read control signal is generated according to the first descriptor.
The DMA controller according to claim 4, wherein the first descriptor comprises a first field, the first field is used to indicate that the type of the first data is an immediate number, one-dimensional 1D data or 2D 2D data.
The DMA controller according to claim 4, wherein the first descriptor comprises a second field, and the second field is used to indicate a priority of a task corresponding to the first data.
The DMA controller according to claim 4, wherein said first descriptor comprises a third field, said third field being for indicating an unpacking mode of said first data.
The DMA controller according to claim 4, wherein said data control unit includes a register for registering a priority of a task corresponding to said first data in said first descriptor, said A read control unit is operative to generate the read control signal based on a priority in the register.
The DMA controller of claim 1 wherein said DMA control The device also includes a write data path.

The control path further includes a write control unit for generating a write control signal, and controlling, by the write control signal, the write data path to read a second from the internal storage unit via the internal bus data;

The write data path includes a packing unit for packaging the second data, the write data path writing the packaged second data to the external memory via the external bus.
The DMA controller according to claim 9, wherein the write data path further comprises a second clock processing unit, configured to: after the packing unit packs the second data, the packaged device The second data is processed across the clock domain of the asynchronous first in first out FIFO.
A direct memory access DMA controller characterized by including a control path and a write data path,

The control path includes a write control unit for generating a write control signal, and controlling, by the write control signal, the write data path to read second data from an internal storage unit via an internal bus;

The write data path includes a packing unit, and the packing unit is configured to package the second data, and the write data path writes the packaged second data to the external memory via an external bus.
The DMA controller according to claim 11, wherein the packaging unit is specifically configured to package the second data according to a preset packing mode.
The DMA controller according to claim 11, wherein the write data path further comprises a second clock processing unit, configured to: after the packing unit packs the second data, the packaged device The second data is processed across the clock domain of the asynchronous first in first out FIFO.
The DMA controller according to claim 11, wherein said control path further comprises a data control unit, said data control unit is operative to read a second descriptor of said second data, said write control unit Specifically, the generating the write control signal is generated according to the second descriptor.
The DMA controller according to claim 14, wherein the second descriptor comprises a first field, the first field is used to indicate that the type of the second data is an immediate number, one-dimensional 1D data or 2D 2D data.
The DMA controller according to claim 14, wherein the second descriptor comprises a second field, the second field being used to indicate a priority of a task corresponding to the second data.
The DMA controller according to claim 14, wherein said second descriptor comprises a third field, said third field being for indicating a packing mode of said second data.
The DMA controller according to claim 14, wherein said data control unit includes a register for registering a priority of a task corresponding to said second data in said second descriptor, said A write control unit is operative to generate the write control signal based on a priority in the register.
The DMA controller of claim 11 wherein said DMA controller further comprises a read data path.

The control path further includes a read control unit for generating a read control signal, and controlling, by the read control signal, the read data path to read the first data from the external memory via the external bus ;

The read data path includes a depacket unit for unpacking the first data, the read data path writing the unpacked first data to the internal via the internal bus Storage unit.
The DMA controller according to claim 19, wherein said read data path further comprises a first clock processing unit for performing asynchronous first-in first-out FIFO on said first data read by said read data path The cross-clock domain processing is used to unpack the first data processed by the cross-clock domain of the FIFO.
A data reading method, characterized in that the method is performed by a direct memory access DMA controller, the DMA controller comprising a control path and a read data path, the control path comprising a read control unit, the read data path The unpacking unit is included, and the method includes:

The read control unit generates a read control signal, and controls the read data path to read the first data from the external memory via the external bus through the read control signal;

The unpacking unit unpacks the first data, and the read data path writes the unpacked first data to an internal storage unit via an internal bus.
The method according to claim 21, wherein the unpacking unit unpacks the first data, including:

The unpacking unit unpacks the first data according to a preset unpacking mode.
The method of claim 21, wherein the read data path further comprises a first clock processing unit, the method further comprising:

The first clock processing unit differentiating the first data read by the read data path Step-by-clock domain processing of the first-in first-out FIFO;

Unpacking the first data by the unpacking unit includes:

The unpacking unit unpacks the first data after the cross-clock domain processing of the FIFO.
The method of claim 21, wherein the control path further comprises a data control unit, the method further comprising:

The data control unit reads a first descriptor of the first data;

The read control unit generates a read control signal, including:

The read control unit generates the read control signal based on the first descriptor.
The method according to claim 24, wherein the first descriptor comprises a first field, the first field is used to indicate that the type of the first data is an immediate number, one-dimensional 1D data or two-dimensional 2D data.
The method according to claim 24, wherein the first descriptor comprises a second field, and the second field is used to indicate a priority of a task corresponding to the first data.
The method of claim 24, wherein the first descriptor comprises a third field, the third field being used to indicate an unpacking mode of the first data.
The method of claim 24, wherein the data control unit comprises a register, the method further comprising:

The register registers a priority of a task corresponding to the first data in the first descriptor;

The read control unit generates the read control signal according to the first descriptor, including:

The read control unit generates the read control signal based on a priority in the register.
The method of claim 21, wherein the DMA controller further comprises a write data path, the control path further comprising a write control unit, the write data path comprising a packaging unit, the method further comprising:

The write control unit generates a write control signal, and controls, by the write control signal, the write data path to read second data from the internal storage unit via the internal bus;

The packing unit packs the second data, and the write data path writes the packaged second data to the external memory via the external bus.
The method of claim 29, wherein the write data path further comprises a second clock processing unit, the method further comprising:

After the packetizing unit packs the second data, the second clock processing unit performs cross-clock domain processing of the asynchronous first-in first-out FIFO on the packed second data.
A data writing method, characterized in that the method is performed by a direct memory access DMA controller, the DMA controller comprising a control path and a write data path, the control path comprising a write control unit, the write data path Including a packaging unit, the method includes:

The write control unit generates a write control signal, and controls the write data path to read the second data from the internal storage unit via the internal bus through the write control signal;

The packing unit packs the second data, and the write data path writes the packed second data to the external memory via an external bus.
The method according to claim 31, wherein the packaging unit packages the second data, including:

The packaging unit packages the second data according to a preset packing mode.
The method of claim 31, wherein the write data path further comprises a second clock processing unit, the method further comprising:

After the packetizing unit packs the second data, the second clock processing unit performs cross-clock domain processing of the asynchronous first-in first-out FIFO on the packed second data.
The method of claim 31, wherein the control path further comprises a data control unit, the method further comprising:

The data control unit reads a second descriptor of the second data;

The write control unit generates a write control signal, including:

The write control unit generates the write control signal according to the second descriptor.
The method according to claim 34, wherein the second descriptor comprises a first field, the first field is used to indicate that the type of the second data is immediate, one-dimensional 1D data or two-dimensional 2D data.
The method according to claim 34, wherein the second descriptor comprises a second field, the second field being used to indicate a priority of a task corresponding to the second data.
The method of claim 34, wherein the second descriptor comprises a third field, the third field being used to indicate a packing mode of the second data.
The method of claim 34, wherein the data control unit comprises a register, the method further comprising:

The register registers a priority of a task corresponding to the second data in the second descriptor;

The write control unit generates the write control signal according to the second descriptor, including:

The write control unit generates the write control signal according to a priority in the register.
The method of claim 31, wherein the DMA controller further comprises a read data path, the control path further comprising a read control unit, the read data path comprising an unpacking unit, the method further comprising:

The read control unit generates a read control signal, and controls, by the read control signal, the read data path to read first data from the external memory via the external bus;

The unpacking unit unpacks the first data, and the read data path writes the unpacked first data to the internal storage unit via the internal bus.
The method of claim 39, wherein the read data path further comprises a first clock processing unit, the method further comprising:

Performing, by the first clock processing unit, the cross-clock domain processing of the asynchronous first-in first-out FIFO on the first data read by the read data path;

Unpacking the first data by the unpacking unit includes:

The unpacking unit unpacks the first data after the cross-clock domain processing of the FIFO.
An integrated circuit comprising the DMA controller according to any one of claims 1 to 10 and/or the DMA controller according to any one of claims 11 to 20.
A mobile device, comprising the DMA controller according to any one of claims 1 to 10 and/or the DMA controller according to any one of claims 11 to 20.