CN117971746A

CN117971746A - Method and computing device for controlling direct memory access controller

Info

Publication number: CN117971746A
Application number: CN202410362494.1A
Authority: CN
Inventors: 胡杰; 蔡权雄; 牛昕宇
Original assignee: Shenzhen Corerain Technologies Co Ltd
Current assignee: Shenzhen Corerain Technologies Co Ltd
Priority date: 2024-03-28
Filing date: 2024-03-28
Publication date: 2024-05-03

Abstract

The invention provides a method and a computing device for controlling a direct memory access controller, wherein the method comprises the following steps: configuring header information for each descriptor of the direct memory access controller and configuring register information to each descriptor, the header information declaring whether the descriptor contains each register information; for the header information of the first descriptor, setting all bits corresponding to all register information as a first flag; comparing the N descriptor except the first descriptor with corresponding register information of the previous descriptor, and setting bit positions corresponding to the header information and the corresponding register information of the N descriptor as a second mark if the comparison results are the same; sequentially storing each descriptor to a descriptor memory of the direct memory access controller; triggering the direct memory access controller to work and starting the DMA function. The method can reduce the storage space required by the register information of the descriptor and improve the data transmission efficiency.

Description

Method and computing device for controlling direct memory access controller

Technical Field

The present invention relates to the field of computer technology, and in particular, to a method for controlling a direct memory access controller, and a computing device.

Background

In modern computer systems, direct Memory Access (DMA) is a common function of a chip bus architecture, and is widely applied to high-speed data transmission scenarios, such as hard disk reading and writing, network data packet transceiving, graphic display data updating, and the like. Through the DMA controller, data can be efficiently transmitted in the form of blocks, so that the burden of a CPU is greatly reduced, and delay is reduced.

The most straightforward way to control a Direct Memory Access Controller (DMAC) is to configure its registers, which typically have multiple registers, as with other IPs. And the Host writes configuration values into required registers according to the requirements, and then enables the DMAC to operate. However, the method can only use one DMA function once, and for huge data transmission application, the process obviously needs to be configured for many times, so that a Host (Host) is frequently occupied, and the system efficiency is reduced.

Therefore, there is a need for a method for DMAC that reduces the memory space required for register information and improves DMA efficiency.

Disclosure of Invention

The invention aims to provide a method for a direct memory access controller, which reduces the storage space required by register information of descriptors, increases the number of descriptors in a limited storage space and improves DMA efficiency.

According to an aspect of the present invention, there is provided a method for controlling a direct memory access controller, comprising:

Configuring header information for each descriptor of the direct memory access controller and configuring register information to each descriptor, comprising:

Setting bits corresponding to all register information to a first flag for the header information of a first descriptor, and the first descriptor contains all register information;

comparing the N-th descriptor except the first descriptor with corresponding register information of a previous descriptor, if the comparison result is the same, setting a bit corresponding to the header information of the N-th descriptor and the corresponding register information as a second mark, and not configuring the corresponding register information to the N-th descriptor, wherein N is a natural number larger than 1;

Sequentially storing each descriptor to a descriptor memory of the direct memory access controller;

triggering the direct memory access controller to operate, thereby enabling the DMA function,

Wherein the header information declares whether the descriptor contains register information.

According to some embodiments, before configuring header information of each descriptor for the direct memory access controller and configuring register information to each descriptor, further comprising:

the descriptor header information enable flag is configured.

According to some embodiments, if the descriptor header information enable flag is false, configuring the register information contained in each descriptor in a constrained fixed format, the number of register information of each descriptor being the same, and no more operations are performed to configure header information and register information for each descriptor of the direct memory access controller.

According to some embodiments, the descriptor header information enable flag is stored in a corresponding register, or a predetermined bit in the header information of the descriptor.

According to some embodiments, there is provided a method for a direct memory access controller, comprising:

Reading out the descriptor from the descriptor memory;

Configuring a register using the descriptor, comprising: analyzing the header information of the descriptor, wherein the header information declares whether the descriptor contains each register information, if the bit of the corresponding register information is a second mark, the corresponding register is not updated, otherwise, the corresponding register information configures the corresponding register;

After completing the configuration of the register by using the descriptor, starting DMA transmission;

the foregoing operations are repeated until all descriptors in the descriptor store have been read.

According to some embodiments, the direct memory access controller includes a descriptor count register, in which the number of descriptors to be read continuously is set;

The internal counter will automatically increment by 1 whenever the direct memory access controller completes the operation on one descriptor and begins processing the next descriptor;

and when the counter value reaches the number of descriptors set in the descriptor counting register, indicating that all the scheduled descriptors are processed completely, and stopping the current working cycle.

According to some embodiments, before parsing the header information of the descriptor, further comprising:

Reading a descriptor header information enable flag;

if the descriptor header information enable flag is false, the corresponding register is configured with all register information in a constrained fixed format.

According to another aspect of the present invention, there is provided a computer program product comprising:

Computer program which, when executed by a processor, implements a method as claimed in any one of the preceding claims.

According to another aspect of the invention there is provided a computing device comprising a processor, and a memory storing a computer program which, when executed by the processor, implements a method as in any of the above.

According to another aspect of the invention there is provided a non-transitory computer readable storage medium having stored thereon computer readable instructions which, when executed by a processor, implement a method as claimed in any preceding claim.

According to the method of the embodiment of the invention, by adding the descriptor header information, the system can only store changed register information in the descriptor, and the register information which is kept unchanged can indicate whether updating is needed or not through the flag bit in the header information. Even though descriptors contain a large number of registers, the register information actually stored in the FIFO can be significantly reduced, thereby storing more descriptors in a limited memory space. According to the method provided by the embodiment of the invention, the descriptor can occupy less space, the system efficiency can be obviously improved, the time for transmitting the descriptor can be reduced, and the storage space required by the register information of the descriptor is reduced.

According to some embodiments, the introduction of descriptor header information enables the overall efficiency of the system while also being compatible with conventional designs.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention as claimed.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are required to be used in the description of the embodiments will be briefly described below.

Fig. 1 illustrates a schematic diagram of a chip bus architecture according to some embodiments.

FIG. 2 illustrates a composition schematic of a register descriptor, according to some embodiments.

Fig. 3 illustrates a schematic diagram of a conventional descriptor-based direct memory access controller configuration in accordance with some embodiments.

Fig. 4 shows a schematic diagram of a direct memory access controller configuration with descriptors according to an example embodiment.

Fig. 5 shows a practical application map of a descriptor head according to an example embodiment.

Fig. 6 shows a flow chart of a method for controlling a direct memory access controller according to an example embodiment.

Fig. 7 shows a method flow diagram for a direct memory access controller in accordance with an example embodiment.

Fig. 8A and 8B illustrate a method flow diagram for controlling a memory access controller configuration in accordance with an example embodiment.

FIG. 9 illustrates a block diagram of a computing device according to an example embodiment.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments can be embodied in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the invention. One skilled in the relevant art will recognize, however, that the invention may be practiced without one or more of the specific details, or with other methods, components, devices, steps, etc. In other instances, well-known methods, devices, implementations, or operations are not shown or described in detail to avoid obscuring aspects of the invention.

The block diagrams depicted in the figures are merely functional entities and do not necessarily correspond to physically separate entities. That is, the functional entities may be implemented in software, or in one or more hardware modules or integrated circuits, or in different networks and/or processor devices and/or microcontroller devices.

The flow diagrams depicted in the figures are exemplary only, and do not necessarily include all of the elements and operations/steps, nor must they be performed in the order described. For example, some operations/steps may be decomposed, and some operations/steps may be combined or partially combined, so that the order of actual execution may be changed according to actual situations.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another element. Accordingly, a first component discussed below could be termed a second component without departing from the teachings of the present inventive concept. As used herein, the term "and/or" includes any one of the associated listed items and all combinations of one or more.

The user information (including but not limited to user equipment information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, presented data, etc.) related to the present invention are information and data authorized by the user or fully authorized by each party, and the collection, use and processing of related data is required to comply with the relevant laws and regulations and standards of the relevant country and region, and is provided with corresponding operation entries for the user to select authorization or rejection.

Those skilled in the art will appreciate that the drawings are schematic representations of example embodiments and that the modules or flows in the drawings are not necessarily required to practice the invention and therefore should not be taken to limit the scope of the invention.

DMA is a common function of a chip bus architecture, and can directly access the memory and the peripheral without intervention of a CPU or by using a small amount of CPU service, so that the CPU can be released to process other transactions, the data throughput can be obviously improved, and the system efficiency is improved. To implement the DMA function, a dedicated DMA controller is required, and the Host controls the DMAC to transfer data between the various memories or peripherals.

Before describing embodiments of the present invention, some terms or concepts related to the embodiments of the present invention are explained.

DMA (Direct Memory Access ) is a computer hardware technology that allows external devices (e.g., disk controllers, network cards, sound cards, etc.) to directly exchange data with the system memory without the need for full intervention of the CPU. Before there is no DMA, the CPU needs to read each data byte in person and write it to the target location during the data transfer process, which takes up a large number of CPU cycles, especially when processing a large amount of continuous data.

The DMAC (Direct Memory Access Controller ) is the core hardware component in the computer system responsible for managing DMA operations. The DMAC serves as a bridge between the CPU and the memory as well as between the CPU and the peripheral, and allows the peripheral to directly read and write the memory under the assistance of the CPU, so that the participation degree of the CPU in the data transmission process is greatly reduced, and the data transmission efficiency and the overall performance of the system are improved.

FIFO (First-In-First-Out) is a data storage structure commonly used In hardware and software designs. In the DMAC, a FIFO is used to temporarily store DMA descriptors that are about to be executed or are being executed.

Host: referring to a CPU or system controller responsible for setting and loading descriptors, a series of descriptors are pre-filled into the DMA controller's FIFO buffer as required by the transfer task so that the DMA controller can continuously and efficiently perform multiple data transfer operations.

Exemplary embodiments of the present invention are described below with reference to the accompanying drawings.

According to some embodiments, DMA is a common function of a chip bus architecture, and a dedicated DMA controller is required to implement DMA functions, where the DMAC is controlled by an on-chip CPU or an external control interface, such as PCIe, to transfer data between memories or peripherals.

Referring to fig. 1, there is shown an architecture diagram of a chip bus, wherein the chip contains a CPU, an IP a, a DDR IP and an on-chip bus, the IP a contains a DMAC inside, and DDR particles outside the chip. The process of DMA reading data comprises a configuration stage and a data transmission stage, wherein an on-chip bus interacts with the CPU and DMAC in the IP A through a configuration path, and interacts with the DMAC in the DDR IP and the IP A through a data path.

The CPU, i.e. the control bus, writes relevant configuration information to the DMAC of IP a, including the source address, e.g. the start address in the DDR granule; a target address, such as a target storage area address of an IP a internal or on-chip RAM; the amount of data transferred, such as the number of bytes or the size of the data block, and other control parameters such as the transmission mode, priority, whether to initiate an interrupt, etc.

According to some embodiments, if the IP A is to read data from the DDR particle, the CPU may be first instructed to configure the DMAC of the IP A, which under control of this configuration uses the data transfer path to retrieve the data from the DDR particle through the on-chip bus and DDR IP, and the DMA read process is completed.

The DMA technology can furthest reduce the direct participation of the CPU in the data carrying process, thereby releasing the CPU resource to execute other calculation tasks.

The most direct method for controlling the DMAC is to configure its register, write configuration values into the required register by the Host according to the requirements, then make the DMAC operate, and enable the DMA function. However, the conventional method of controlling DMA transfer by directly configuring DMAC registers has efficiency limitations for the case where individual configuration is required for each transfer, especially for those application scenarios where a large number of data transfers need to be performed continuously and repeatedly. After each DMA transfer is completed, the Host needs to reconfigure the DMAC registers, including but not limited to setting the source address, destination address, transfer size, transfer mode, transfer direction, etc., which definitely increases the load on the CPU and results in a decrease in system efficiency.

In order to improve efficiency, descriptors are introduced as a common control scheme, and as a data structure, all control information required for one DMA transfer is encapsulated. According to some embodiments, a descriptor represents a set of register information including, but not limited to, a source address register, a destination address register, and a data volume register. Compared with a Host direct configuration register, the descriptor occupies less CPU, and the system efficiency can be remarkably improved. Many DMA designs currently use descriptors.

Referring to fig. 2, 3 different descriptors are shown, together with a descriptor fifo buffer for storage of a plurality of descriptors, where each descriptor corresponds to a set of register information, including source address information, destination address information, and data volume information.

In DMA transmission, the Host will write the descriptors in advance according to the transmission task requirements and store them in the descriptor FIFO of the DMA controller. The descriptor is used to direct the DMA controller to perform a data transfer operation.

According to some embodiments, assuming that the Host first stores 3 descriptors into the descriptor FIFO, each descriptor contains 3 register information, the Host needs to store 9 register information into the FIFO. When the DMAC starts to work, the descriptors are sequentially read according to the sequence of the FIFO, and corresponding hardware registers are configured according to the register information in the descriptors so as to execute the data transmission task.

The DMAC reads the descriptor 1 from the descriptor FIFO, i.e., reads out the first 3 register information, the source address A1, the destination address A2, and the data amount A3. The first 3 register information is used to configure the DMAC to perform the first DMA transfer. Completing the first DMA transmission according to the carried source address A1, destination address A2 and data volume A3 information; after completion, the DMAC then reads descriptor 2, also configures the hardware with the register information therein, and performs a second DMA transfer; finally, the DMAC reads descriptor 3, completing the third and last DMA transfer.

After the third DMA transfer is completed, the DMAC stops working and notifies the Host. At this point, the Host may begin preparing new descriptors and store them in the descriptor FIFO for use by the DMAC next time it is needed.

When all of the pre-placed descriptors of the FIFO have been processed, the DMAC typically notifies the Host via an interrupt or other mechanism, indicating that the FIFO is empty, waiting for a new descriptor to be stored. Therefore, the Host can continue to configure and submit new data transmission tasks, and the DMAC can continuously execute DMA transmission operation, so that the data transmission efficiency is greatly improved, and simultaneously, CPU resources are released to do other calculation tasks.

In this way, the Host can utilize the descriptor FIFO to control the DMAC to perform multiple DMA transfers without requiring manual configuration of the DMAC each time. This automated approach increases the efficiency and convenience of data transmission.

Fig. 3 illustrates a schematic diagram of a direct memory access controller configuration with descriptors according to some embodiments.

Fig. 4 shows a schematic diagram of adding descriptor header information for a direct memory access controller configuration in accordance with an example embodiment.

According to the control mode of the descriptors in the above figure 2, if the capacity of the descriptor FIFO is enlarged, more descriptors can be stored, which is more beneficial to improving the efficiency. But the memory space available for the chip is very limited from an implementation point of view. If a descriptor contains a large number of registers, the number of descriptors that can be stored in the FIFO becomes small, and DMA is efficient in terms of the number of descriptors, which obviously decreases.

In order to improve DMA efficiency, a method of storing descriptors as much as possible in a limited memory space, that is, reducing the number of registers included in the descriptors as much as possible, is required. The present exemplary embodiment adds descriptor header information based on the direct memory access controller configuration of the descriptor of fig. 3, see fig. 4.

As shown in fig. 3, each descriptor contains 8 register information, corresponding in turn to 8 registers of the DMAC. The arrows in the figure indicate the correspondence, that is, the register information read out from the FIFO is written into the corresponding register, completing the DMAC configuration process.

According to an example embodiment, the descriptor proceeds with a direct memory access controller configuration process of:

Host stores descriptors containing 8 register information into descriptor FIFO; when the DMAC needs to configure registers, a descriptor is read from the descriptor FIFO, and the register information in the read descriptor is written into 8 registers of the DMAC, so that the configuration process is completed. Repeating the steps until all descriptors in the descriptor FIFO are read and configured, stopping the DMAC when the descriptor FIFO is empty, and waiting for a Host to store a new descriptor.

As shown in fig. 4, descriptor header information is added to the descriptor FIFO, which functions to declare whether this descriptor contains certain register information, and if not, the DMAC register uses the register information of the previous descriptor, otherwise uses the register information of the present descriptor.

According to an example embodiment, the adding of the descriptor header information is followed by a direct memory access controller configuration process of:

The descriptor FIFO also contains 8 register information, which in turn corresponds to the 8 registers of the DMAC; if the descriptor header information indicates that certain register information does not exist, the DMAC will use the register information of the previous descriptor to configure the corresponding register. If the descriptor header information indicates that certain register information is present, the DMAC will use the register information of the current descriptor to configure the corresponding register.

According to some embodiments, the descriptor header information width is equal to the register bit width, but the invention is not limited thereto, and the descriptor header information and the register information have corresponding parsing logic. Assuming that the register information bit width is 32-bits, the following table is defined for the descriptor header information:

according to the information in the table, bit is 0, which indicates that old register information is used; the bit is 1, indicating register information using the current descriptor. If part of the register information of the latter descriptor is consistent with the former descriptor, the corresponding bit of the descriptor header information may be set to 0 and these register information are not stored into the FIFO, otherwise 1 is set and all register information is normally stored. Obviously, if it is the first descriptor after power-up, the valid bits of the descriptor header information must all be 1.

By means of the descriptor header information, the Host can use the descriptor header information to control how the DMAC uses register information in the descriptor, so that more flexible data transmission configuration is achieved. The mechanism enables the Host to choose whether to update a certain register according to actual requirements, and improves the efficiency and flexibility of data transmission.

Referring to fig. 5, the first descriptor stored after power-up contains 8 pieces of register information, the descriptor header information is 32' hxxxxxff, x represents an arbitrary value, and the low-order ff is 11111111.

Assuming that the register information 3, the register information 5 and the register information 6 of the second descriptor are consistent with those of the first descriptor, the second descriptor has only 5 pieces of register information in the figure, the descriptor head information of the second descriptor is 32' hxxxxcb, and the lower cb is 11001011 when the lower cb is changed to 2, which means that the descriptor does not contain the register information 3, the register information 5 and the register information 6, that is, the register 3, the register 5 and the register 6 of the DMAC are not updated, and the register information of the last descriptor is kept.

In conventional designs, two descriptors must contain 16 register information, occupying 16 address spaces of the FIFO. In this exemplary embodiment, descriptor header information is introduced, the same register information is removed, and two descriptors contain 2 descriptor header information and 13 register information in total, and occupy 15 address spaces of FIFO. Although there is more descriptor header information, the total memory space is less consumed. When the descriptors contain a large amount of register information and part of register information of adjacent descriptors is consistent, the memory consumption can be obviously reduced, the number of the descriptors is increased, and the time for transmitting the descriptors to the descriptor FIFO by the Host can also be reduced.

This design reduces the occupation of storage space while meeting transmission requirements. In conventional designs, even if some register information of adjacent descriptors is the same, it is necessary to store the information in each descriptor in its entirety, resulting in a waste of memory space. By adopting the design of the descriptor head of the selectable register information, repeated register information can be shared among descriptors, so that more descriptors are stored in the FIFO, the time required by Host for transmitting the descriptors to the FIFO is reduced, and the efficiency of the whole system is improved.

The present example embodiment demonstrates how the optimized DMA descriptor design improves memory utilization and system efficiency, and the system can flexibly update or skip certain register information as needed to optimize the data transfer process.

In the AI field, especially machine learning and deep learning applications, the data transmission is extremely large and generally exhibits a high degree of regularity and repeatability. For example, when training a neural network model, a data set is typically divided into a plurality of batches for iterative training, and the operations such as data loading and model weight updating of each batch have high similarity. The register configuration information for many DMACs may remain unchanged or vary only slightly between consecutive training batches.

By adopting the optimized DMA descriptor design, the data transmission efficiency in the scene can be remarkably improved. By multiplexing the invariable register information, not only can the occupation of FIFO space be reduced, but also the time and effort required by the Host when configuring the DMA controller can be reduced, thereby ensuring that the CPU has more resources to concentrate on the core computing task and accelerating the execution speed of the whole training process. In addition, the optimized DMA descriptor design is also beneficial to reducing the system power consumption and improving the memory bandwidth utilization rate, which is particularly important for AI application deployed in the edge equipment or resource limited environment, and can effectively improve the instantaneity, the stability and the energy efficiency ratio of the whole system.

To be compatible with conventional designs, a register may be added to the DMAC, such as a descriptor header enable "desc_head_en" that identifies predetermined bits stored in the corresponding register, or in the header of the descriptor. When the desc_head_en is 0, the descriptor does not contain descriptor header information, that is, each descriptor has no header information, and only 8 register information, that is, corresponds to the conventional design. When the desc_head_en is 1, the descriptor contains descriptor header information, that is, the first information of each descriptor in the above example is the descriptor header information, that is, corresponds to a new design.

Referring to fig. 6, header information of each descriptor for the direct memory access controller is configured and register information is configured to the descriptor configuration register information to each descriptor at S103 and S105.

At S103, for the header information of the first descriptor, all the bits of the corresponding all register information are set to the first flag, and the first descriptor contains all the register information.

According to some embodiments, for the first descriptor, all register information bits in the header information are set to a first flag, set to active or 1, indicating that the descriptor contains all required register information. The system initializes a first descriptor that contains all necessary register information, such as source address registers, destination address registers, transfer count registers, etc.

To ensure that at the beginning of a DMA transfer, the DMAC controller is able to obtain complete register configuration information to perform the first data transfer accurately. The following descriptors can use the flag bit in the header information to determine whether the register information needs to be updated according to specific conditions, so as to save storage space and improve data transmission efficiency.

At S105, for an nth descriptor other than the first descriptor, comparing with corresponding register information of a previous descriptor, if the comparison result is the same, setting a bit corresponding to the header information of the nth descriptor and the corresponding register information to a second flag, and not configuring the corresponding register information to the nth descriptor.

According to some embodiments, for an nth descriptor following the first descriptor, the system compares the descriptor with corresponding register information for a previous descriptor. If both are found to be identical, in the header information of the nth descriptor, bits corresponding to these identical register information are set to a second flag indicating that no update or 0 is required and these identical register information are not repeatedly configured in the descriptor.

When there are a large number of repeated register configurations in successive descriptors, memory space can be greatly saved and the overhead of the CPU in configuring the descriptors can be reduced, thereby improving the efficiency of the overall DMA transfer.

In S107, the descriptors are sequentially stored to the descriptor memory of the DMAC.

According to some embodiments, these sequentially processed descriptors are sequentially stored to the descriptor memory of the DMAC for subsequent reading and execution by the DMA controller of data transfer tasks.

The descriptors stored therein are sequentially read by the DMAC controller on a first-in first-out basis and used to perform DMA data transfer tasks. Since the effective register information comparison and flag bit setting have been performed in the foregoing, the DMAC can efficiently utilize the storage space, and automatically determine whether the register configuration needs to be updated according to the flag bit in the descriptor header information when processing continuous data transmission, thereby greatly improving the data transmission efficiency and the overall system performance.

In S109, DMAC operation is triggered, and the DMA function is started.

According to some embodiments, after all descriptors have been properly configured and stored in place, the DMAC is triggered to start working, starting the DMA data transfer function.

After starting the DMA function, the DMAC will perform the data transfer tasks independently from the information stored in the descriptor queue, read the data from the specified source address, and then write the data to the destination address without the continued intervention of the CPU. In this way, the CPU can be vacated to handle other tasks, thereby improving the overall performance and efficiency of the system.

In the whole DMA transmission process, the DMAC intelligently decides whether register configuration needs to be updated according to the flag bit in the descriptor head information, so that efficient data transmission is realized. By the optimization mode, the storage of repeated data among descriptors can be effectively reduced, so that the storage space is saved, and the processing efficiency of the DMA controller is improved.

According to some embodiments, referring to the foregoing description, before configuring header information of each descriptor for the direct memory access controller and configuring register information to each descriptor, a descriptor header information enable flag may also be configured. If the descriptor header information enabling flag is false, configuring the register information contained in each descriptor according to a constrained fixed format, wherein the number of the register information of each descriptor is the same, and no operation of configuring the header information of each descriptor for the direct memory access controller and configuring the register information to each descriptor is performed. In this way, conventional designs may be compatible.

Fig. 7 shows a flow chart of a method for a memory access controller to configure a parse descriptor in accordance with an example embodiment.

Referring to fig. 7, in S201, a descriptor is read out from a descriptor memory.

According to some embodiments, the DMA controller reads a descriptor from the descriptor memory. The descriptor memory may be a FIFO buffer or a linked list in which a plurality of descriptor structures are stored, each containing all the necessary information for the DMA transfer.

In S203, the register is configured by using the descriptor, and header information of the descriptor is parsed, where the header information declares whether the descriptor includes each register information, if the bit of the corresponding register information is the first flag, the corresponding register is not updated, otherwise, the corresponding register information configures the corresponding register.

According to some embodiments, the controller parses a header information portion of the descriptor. This header information contains a flag bit that indicates whether the descriptor contains new configuration information for a particular register.

For each register, the controller looks at the corresponding bit in the descriptor header information. If the bit of a certain register information is set to the second flag, this means that the value of the register is not changed in the current descriptor, so the DMA controller does not update this register, but maintains the previous state or uses the value in the previous descriptor. Conversely, if the bit is not the second flag, then a new configuration value for the register is provided in the description descriptor, at which point the DMA controller will use the information provided in the descriptor to update the corresponding internal register.

According to some embodiments, before parsing the header information of the descriptor, a descriptor header enable flag may also be read, and if the descriptor header enable flag is false, the corresponding register is configured with all register information in a constrained fixed format.

After completing the configuration of the register using the descriptor, the direct memory access transfer starts at S205.

According to some embodiments, the DMA controller formally initiates the data transfer process after confirming that all relevant registers have been properly configured. At this time, the controller will directly read data from the source memory area through the bus according to the source address, the target address and the data amount specified in the descriptor, and write the data into the target memory area, and the whole process does not need the intervention of the CPU.

At S207, the foregoing operations are repeated until all descriptors in the descriptor memory have been read.

According to some embodiments, the DMA controller loops processing the next descriptor in the descriptor memory in the same flow path until all descriptors are read and processed.

For example, the direct memory access controller includes a descriptor count register in which the number of descriptors to be read continuously is set; the internal counter will automatically increment by 1 whenever the direct memory access controller completes the operation on one descriptor and begins processing the next descriptor; and when the counter value reaches the number of descriptors set in the descriptor counting register, indicating that all the scheduled descriptors are processed completely, and stopping the current working cycle.

By analyzing the descriptor header information, the DMA controller can intelligently decide which registers need to be updated and which can be kept as they are, thereby saving unnecessary register reconfiguration operations and improving data transmission efficiency. Particularly in continuous data transmission tasks, if some registers of two transmissions are configured identically, duplicate configurations can be avoided. The DMA controller can automatically and continuously execute a plurality of data transmission tasks, so that the work load of a CPU is greatly reduced, and the overall data transmission efficiency and throughput of the system are improved.

Fig. 8A, 8B illustrate a method flow diagram for controlling a memory access controller configuration in accordance with an example embodiment.

Referring to fig. 8A, in S301, the Host configures desc_head_en.

According to some embodiments, host may select a flexible or fixed format descriptor design by setting desc_head_en. In flexible design mode, the first used descriptor will contain all possible register information, and subsequent descriptors can multiplex part of the register information as needed; in the fixed format design mode, each descriptor contains complete register information equal to the number of DMAC registers. Host first decides whether to enable flexible descriptor designs, which descriptor design to use is decided by setting desc_head_en.

If the desc_head_en is 1 in S302, S303 is performed to determine whether the descriptor is a first-time descriptor, if the descriptor is a first-time descriptor, S305 is performed, and the Host configures all valid bits of header information of the first descriptor to be 1, where the descriptor includes all register information.

According to an exemplary embodiment, for the header information of the first descriptor, the Host needs to set all bits of bits corresponding to all register information to 1, and this descriptor contains all register information in order to initialize the DMA transfer.

If the desc_head_en is not 1 at S302, then S304 is performed, and the Host configures the register information contained in each descriptor according to the constrained fixed format. The number of register information for each descriptor is the same as the number of DMAC registers.

If it is determined in S303 that the descriptor is not the first time descriptor, S306 is performed to configure other descriptors, which may not include all the register information, based on the register information comparison with the previous descriptor.

According to some embodiments, if there is identical register information, the descriptor header information corresponds to bit position 0, and this register information may not be configured to the descriptor. In this way, host can effectively use the descriptor header information to indicate which register information remains unchanged in the continuous DMA transfer, thereby reducing duplicate configuration, saving memory space, and improving DMA data transfer efficiency.

In S307, the Host stores all descriptors in the descriptor FIFO in sequence.

According to an exemplary embodiment, regardless of the descriptor design employed, the Host stores all configured descriptors sequentially one by one into the descriptor FIFO of the DMA controller.

The difference is that for flexible descriptor designs, since possible descriptors do not contain all register information, represented by bit marked 0 in the header information, the space occupied by descriptors stored in the FIFO is reduced, so that more descriptors can be stored in a limited FIFO capacity, improving the continuity and efficiency of DMA data transfer. For conventional fixed format descriptor designs, each descriptor contains the same amount of register information, and the process of storing it into the FIFO is relatively straightforward, but may require more memory space.

Descriptors in the descriptor FIFO are read one by the DMA controller and corresponding data transfer tasks are performed in accordance with a first-in first-out principle. When all descriptors in the FIFO have been executed, the Host may reconfigure new descriptors as needed and store them in the FIFO to continue data transfer.

Referring to FIG. 8B, at S308, the Host triggers the DMAC to operate, starting the DMA function.

According to an exemplary embodiment, after the Host completes the filling of the descriptor FIFO, the DMAC will be triggered to start working by a specific control signal or written into a specific control register, starting the DMA function. The DMAC will take over the task of data transfer, fetch the descriptors from the descriptor FIFO, automatically read data from the source address and write the destination address based on the information in the descriptors, without frequent intervention by the CPU.

In S309, the DMAC reads out a descriptor, i.e., a set of register information, from the FIFO.

According to an exemplary embodiment, the DMAC begins performing data transfer tasks and reads the next descriptor to be processed from the descriptor FIFO, which is pre-filled by the Host.

When a descriptor is read by the DMAC, a set of register information associated with the descriptor is actually obtained. The register information contains the various key parameters required for the DMA transfer, including the source address, destination address, amount of data transferred, and possible transfer control options.

In S310, it is determined whether the desc_head_en is 1, and if the desc_head_en is 1, S311 is performed, and the DMAC parses the header information of the descriptor and configures the corresponding register.

According to an example embodiment, the DMAC begins parsing the header information of the read descriptor. Based on each bit state in the header information, the DMAC decides whether to update or configure the corresponding register, which means that the corresponding register information is the same as in the previous descriptor if a bit in the header information is 0, so the DMAC does not need to update this register, but continues to use the value set in the previous descriptor. Conversely, if a bit in the header information is 1, this means that new register information is included in the descriptor, and the DMAC configures the register with the corresponding register information included in the descriptor.

If it is determined at S310 that the desc_head_en is not 1, the process proceeds to S312, where the corresponding register is configured with the full register information in the constrained fixed format.

According to an example embodiment, if the DMAC detects that the desc_head_en is not 1, this means that a conventional fixed format descriptor design is currently employed, rather than a flexible descriptor design.

The DMAC will be configured exactly as all register information contained in the descriptor, whether or not this information is identical to the information in the previous descriptor. This means that for each descriptor, the DMAC will use all of the register information provided in the descriptor to configure the corresponding internal registers in a fixed format, without the register information multiplexing.

At S313, after completion of one DMA transfer, it is queried whether descriptors remain in the FIFO. If so, turning to S309, the DMAC proceeds to read the descriptor from the FIFO.

According to an exemplary embodiment, after the DMAC completes one DMA transfer, it checks if there are more unprocessed descriptors in the FIFO. If there are remaining descriptors in the FIFO, the DMAC returns to S309, proceeds to read the next pending descriptor from the FIFO, and configures and performs a new DMA transfer task based on the previously parsed register information.

This process loops until all descriptors in the FIFO have been read and processed by the DMAC.

After the completion of one DMA transfer in S313, if no descriptors remain in the enquiry FIFO, S314 is performed, and all DMA transfers are completed, waiting for the Host to start the DMAC again or to store new descriptors.

According to an exemplary embodiment, when the DMAC completes one DMA transfer, it queries the descriptor FIFO for no pending descriptors remaining, meaning that all of the currently scheduled data transfer tasks have been performed, the DMAC suspends the DMA transfer function, enters a wait state, and either starts the DMAC again by the Host or stores new descriptors into the descriptor FIFO.

After the end of the previous round of DMA transfer, the DMAC waits for further instructions from the Host to begin the next round of data transfer tasks. Therefore, the system can dynamically manage and schedule the DMA transmission process according to actual demands, and ensure that data flows between the memory and the computing chip efficiently and orderly.

The method for controlling the configuration of the memory access controller according to the present exemplary embodiment, the descriptor header information enables the reference, and the DMAC greatly reduces direct intervention of the CPU on data transmission, improves the overall efficiency of the system, and is compatible with conventional designs.

In the embodiment of the present example, when the time for transmitting the descriptor in the Host is reduced, the storage space required by the register information of the descriptor is reduced, the number of descriptors in the limited storage space is increased, the DMA efficiency is improved, and efficient and continuous data transmission from the DDR to the internal buffer area of the computing chip is realized.

FIG. 9 illustrates a block diagram of a computing device according to an example embodiment of the invention.

As shown in fig. 9, computing device 30 includes processor 12 and memory 14. Computing device 30 may also include a bus 22, a network interface 16, and an I/O interface 18. The processor 12, memory 14, network interface 16, and I/O interface 18 may communicate with each other via a bus 22.

The processor 12 may include one or more general purpose CPUs (Central Processing Unit, processors), microprocessors, or application specific integrated circuits, etc. for executing associated program instructions. According to some embodiments, computing device 30 may also include a high performance display adapter (GPU) 20 that accelerates processor 12.

Memory 14 may include machine-system-readable media in the form of volatile memory, such as Random Access Memory (RAM), read Only Memory (ROM), and/or cache memory. Memory 14 is used to store one or more programs including instructions as well as data. The processor 12 may read instructions stored in the memory 14 to perform the methods according to embodiments of the invention described above.

Computing device 30 may also communicate with one or more networks through network interface 16. The network interface 16 may be a wireless network interface.

Bus 22 may be a bus including an address bus, a data bus, a control bus, etc. Bus 22 provides a path for exchanging information between the components.

It should be noted that, in the implementation, the computing device 30 may further include other components necessary to achieve normal operation. Furthermore, it will be understood by those skilled in the art that the above-described apparatus may include only the components necessary to implement the embodiments of the present description, and not all the components shown in the drawings.

The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above method. The computer readable storage medium may include, but is not limited to, any type of disk including floppy disks, optical disks, DVDs, CD-ROMs, micro-drives, and magneto-optical disks, ROM, RAM, EPROM, EEPROM, DRAM, VRAM, flash memory devices, magnetic or optical cards, nanosystems (including molecular memory ICs), network storage devices, cloud storage devices, or any type of media or device suitable for storing instructions and/or data.

Embodiments of the present invention also provide a computer program product comprising a non-transitory computer readable storage medium storing a computer program operable to cause a computer to perform part or all of the steps of any one of the methods described in the method embodiments above.

It will be clear to a person skilled in the art that the solution according to the invention can be implemented by means of software and/or hardware. "Unit" and "module" in this specification refer to software and/or hardware capable of performing a specific function, either alone or in combination with other components, where the hardware may be, for example, a field programmable gate array, an integrated circuit, or the like.

It should be noted that, for simplicity of description, the foregoing method embodiments are all described as a series of acts, but it should be understood by those skilled in the art that the present invention is not limited by the order of acts described, as some steps may be performed in other orders or concurrently in accordance with the present invention. Further, those skilled in the art will also appreciate that the embodiments described in the specification are all preferred embodiments, and that the acts and modules referred to are not necessarily required for the present invention.

In the foregoing embodiments, the descriptions of the embodiments are emphasized, and for parts of one embodiment that are not described in detail, reference may be made to related descriptions of other embodiments.

In the several embodiments provided by the present invention, it should be understood that the disclosed apparatus may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, such as a division of units, merely a division of logic functions, and there may be additional divisions in actual implementation, such as multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be through some service interface, device or unit indirect coupling or communication connection, electrical or otherwise.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable memory. Based on this understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art or in whole or in part in the form of a software product stored in a memory, comprising several instructions for causing a computer device (which may be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method of the various embodiments of the present invention.

The exemplary embodiments of the present invention have been particularly shown and described above. It is to be understood that this invention is not limited to the precise arrangements, instrumentalities and instrumentalities described herein; on the contrary, the invention is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method for controlling a direct memory access controller, comprising:

2. The method of claim 1, further comprising, prior to configuring header information for each descriptor of the direct memory access controller and configuring register information to each descriptor:

the descriptor header information enable flag is configured.

3. The method as recited in claim 2, further comprising:

If the descriptor header information enabling flag is false, configuring the register information contained in each descriptor according to a constrained fixed format, wherein the number of the register information of each descriptor is the same, and no operation of configuring the header information of each descriptor for the direct memory access controller and configuring the register information to each descriptor is performed.

4. The method of claim 2, wherein the descriptor header information enable flag is stored in a corresponding register or a predetermined bit in the header information of the descriptor.

5. A method for a direct memory access controller, comprising:

Reading out the descriptor from the descriptor memory;

repeating the steps until all descriptors in the descriptor memory are read.

6. The method according to claim 5, comprising:

the direct memory access controller comprises a descriptor counting register, and the number of descriptors to be continuously read is set in the descriptor counting register;

And when the counter reaches the number of descriptors set in the descriptor counting register, indicating that all the scheduled descriptors are processed completely, and stopping the current working cycle.

7. The method of claim 5, further comprising, prior to parsing the header information of the descriptor:

Reading a descriptor header information enable flag;

8. The method of claim 7, wherein the descriptor header information enable flag is stored in a corresponding register or a predetermined bit in the header information of the descriptor.

9. A computer program product comprising a computer program which, when executed by a processor, implements the method according to any of claims 1-8.

10. A computing device, comprising:

A processor; and

Memory storing a computer program which, when executed by the processor, implements the method according to any of claims 1-8.