CN117373508A - Multiport memory, read-write method and device of multiport memory - Google Patents
Multiport memory, read-write method and device of multiport memory Download PDFInfo
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
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- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
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- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
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- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1063—Control signal output circuits, e.g. status or busy flags, feedback command signals
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- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1069—I/O lines read out arrangements
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- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G11C7/1096—Write circuits, e.g. I/O line write drivers
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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Abstract
The embodiment of the invention provides a multiport memory, a read-write method and a read-write device of the multiport memory. The multiport memory includes: n write ports, a write controller, K write buffers and a memory block group, wherein the memory block group comprises K memory blocks, and K is larger than N; the write port is used for receiving an externally input write command and write data and outputting the write command and the write data to the write controller; a write controller for scheduling write commands and write data to corresponding write buffers; and the write buffers are used for caching write data to be written into the storage blocks, wherein one write buffer corresponds to one storage block. The invention solves the problem of exponential increase of storage overhead caused by the increase of access ports, and achieves the effect of reducing the overhead of storage resources required by the multi-port memory cache.
Description
Technical Field
The embodiment of the invention relates to the field of network communication, in particular to a multiport memory, a read-write method and a read-write device of the multiport memory.
Background
The memory is a component for storing programs and data, and has very wide application in the fields of computers, communications, artificial intelligence, and the like. Almost all chips or devices with high technology content are equipped with dedicated internal or external memory, the performance of which is often one of the key factors in determining the performance of the whole chip or device. Among the various memories, SRAM is currently the most common on-chip memory in the field of large-scale integrated circuits. Compared to the memory forms such as latch arrays and registers, the memory cost of SRAM is minimal, so existing caches are mainly SRAM based. The original SRAM IP is basically formed by a single read or write port, and related chips in the fields of computer, communication and artificial intelligence often need memories with more ports to ensure high-parallelism processing performance and high-bandwidth interface performance.
The existing multiport cache mainly has the following design schemes: the first is time-sharing reading through an arbitration mechanism, but the cache speed of the type is often limited by the interface speed of a memory, and parallel access cannot be provided; the second is to divide the memory area with multiple granularities, but this solution does not provide a solution to the access conflict, but only waits when the access conflict occurs, and the access rate cannot be guaranteed; and thirdly, a mode of copying storage resources and copying storage contents is adopted to realize parallel read-write port expansion, but the memory overhead required by the scheme can increase exponentially along with the increase of the number of ports, and the overhead of area and power consumption is overlarge.
Disclosure of Invention
The embodiment of the invention provides a multiport memory, a read-write method and a read-write device of the multiport memory, which at least solve the problem of overlarge multi-port parallel read-write cache cost in the related technology.
According to one embodiment of the present invention, there is provided a multi-port memory including: n write ports, a write controller, K write buffers and a memory block group, wherein the memory block group comprises K memory blocks, and K is larger than N; the write port is used for receiving an externally input write command and write data and outputting the write command and the write data to the write controller; the write controller is used for dispatching the write command and the write data to the corresponding write buffer; the write buffers are used for caching write data to be written into the storage blocks, wherein one write buffer corresponds to one storage block.
In an exemplary embodiment, the system further includes N read ports, a read controller, K read command buffers, and N read data buffers, where the read ports are configured to receive externally input read commands and output the read commands to the read controller; the read controller is used for dispatching the read command to a corresponding read command buffer; a read command buffer for buffering a read command for reading a corresponding memory block, wherein one read command buffer corresponds to one memory block; and the read data buffers are used for buffering the data which is read out from the storage block and is to be output to the corresponding read ports, wherein one read data buffer corresponds to one read port.
According to an embodiment of the present invention, there is provided a read-write method of a multiport memory, including: under the condition that write commands are received through a plurality of write ports, determining storage blocks corresponding to the write commands respectively; when there is a free buffer space in the write buffer of the memory block, the write command is scheduled to the corresponding write buffer so that the write data indicated by the write command is written into the memory block through the write buffer.
In an exemplary embodiment, after determining the memory blocks corresponding to the respective write commands, the method further includes: and under the condition that the cache space in the write buffer of the storage block is occupied, blocking a write port for receiving the write command, and initiating the write command again in the next period.
In one exemplary embodiment, in the case that a read command is received through a plurality of read ports, a memory block corresponding to each read command is determined; and under the condition that an idle buffer space exists in the read command buffer of the storage block, the read command is scheduled to the corresponding read command buffer, and a buffer grade is marked for the read command, so that the read data buffer feeds back read data indicated by the read command to the corresponding read port according to the buffer grade, wherein the buffer grade indicates the delay beat number of the read data in the read data buffer.
In one exemplary embodiment, after determining the memory block corresponding to each read command, the method further includes: under the condition that the buffer memory space in the read command buffer of the storage block is occupied, the read port for receiving the read command is blocked, and the read command is initiated again in the next period.
In one exemplary embodiment, scheduling the read command into the corresponding read command buffer and marking the buffer level for the read command includes: under the condition that at least two read commands correspond to the same storage block, caching the at least two read commands into a read command buffer corresponding to the storage block according to priority, and marking a buffer level for each read command according to the caching order, wherein the buffer levels of the read commands are different.
In one exemplary embodiment, marking the buffer level for each read command in turn in buffer order includes: determining the buffer position of the read command in the read command buffer according to the buffer sequence of the read command buffer; and marking the read command with buffer levels corresponding to the buffer positions in the read command buffer, wherein the total number of levels of the buffer levels is consistent with the number of the buffer positions in the read command buffer, and the number of levels of the buffer levels is positively correlated with the ordering of the buffer positions.
According to another embodiment of the present invention, there is provided a read-write apparatus of a multiport memory, including: and the write controller is used for determining the storage block corresponding to each write command when the write command is received through a plurality of write ports, and scheduling the write command to the corresponding write buffer when free buffer space exists in the write buffer of the storage block so as to write the write data indicated by the write command into the storage block through the write buffer.
In one exemplary embodiment, further comprising: and a read controller for determining a memory block corresponding to each read command when the read command is received through a plurality of read ports, scheduling the read command to the corresponding read command buffer when a free buffer space exists in the read command buffer of the memory block, and marking a buffer level for the read command so that the read data buffer feeds back the read data to the corresponding read port when the read data is received, wherein each memory block is provided with the corresponding read command buffer, and the buffer level indicates a delay beat number of the read data indicated by the read command in the read data buffer.
According to a further embodiment of the invention, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
According to a further embodiment of the invention, there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
According to the invention, the multi-port memory is divided into K memories, and each memory speed is provided with an independent write buffer, so that the design of the multi-port cache with order preservation is realized, the problem of exponential increase of memory overhead caused by the increase of access ports is solved, and the overhead effect of reducing the memory resources required by the multi-port memory cache is achieved.
Drawings
FIG. 1 is a block diagram of a hardware architecture of a read-write method of operating a multi-port memory according to an embodiment of the present invention;
FIG. 2 is an application diagram of a multiport memory according to an embodiment of the present invention;
FIG. 3 is a block diagram of a multiport memory according to an embodiment of the present invention;
FIG. 4 is a flow chart of a method for reading and writing a multi-port memory according to an embodiment of the invention;
FIG. 5 is a schematic diagram of the operation of a write controller of a multiport memory according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the operation of a read controller of a multiport memory according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating the operation of the buffer level of a multi-port memory according to an embodiment of the invention;
fig. 8 is a block diagram of a read-write apparatus of a multiport memory according to an embodiment of the present invention.
Detailed Description
Embodiments of the present invention will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.
It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.
The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of a mobile terminal of a method for reading and writing a multiport memory according to an embodiment of the present invention. As shown in fig. 1, a mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor (Central Processing Unit, MCU) or a processing device such as a programmable logic device (Field Programmable Gate Array, FPGA)) and a memory 104 for storing data, where the mobile terminal may further include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.
The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a read/write method of a multiport memory in an embodiment of the present invention, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
The transmission means 106 is arranged to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is used to communicate with the internet wirelessly.
In this embodiment, there is provided a multi-port memory including: n write ports, a write controller, K write buffers and a memory block group, wherein the memory block group comprises K memory blocks, and K is larger than N; the write port is used for receiving an externally input write command and write data and outputting the write command and the write data to the write controller; a write controller for scheduling write commands and write data to corresponding write buffers; and the write buffers are used for caching write data to be written into the storage blocks, wherein one write buffer corresponds to one storage block.
The multiport memory is not limited to be applied to large-scale integrated circuits, is used for caching and storing data, and needs to realize the functions of each module in the chip design stage, is embedded into various large chips as a whole through IP, and provides multiport read-write caching functions.
When the multiport memory is used for providing the multiport read-write buffer function, the system is not limited to the system shown in fig. 2, and the multiport memory (multiport buffer) is connected to n processors (or n core processors) for the n processors (or n core processors) to perform read-write access and data buffer. The n processors (or n core processors) may share the entire address space of the cache and perform the reading and writing at the same time. The multi-port cache provides two independent access ports for 1 read and 1 write for each processor.
It should be noted that: the multiport memory is not limited to the application system shown in fig. 2, but can be used in other devices and systems with multiport access requirements, and is only one possible application implementation environment, and the multiport memory in the present embodiment is not limited to use in any system requiring multiport buffering.
As an optional implementation manner, the multi-port memory further includes N read ports, a read controller, K read command buffers, and N read command buffers, where the read ports are configured to receive externally input read commands and output the externally input read commands to the read controller; a read controller for scheduling read commands to corresponding read command buffers; a read command buffer for buffering a read command for reading a corresponding memory block, wherein one read command buffer corresponds to one memory block; and the read data buffers are used for buffering the data which is read out from the storage block and is to be output to the corresponding read ports, wherein one read data buffer corresponds to one read port.
The structure of the multiport memory is not limited to that shown in fig. 3. The write port group mainly provides N write ports on the write side, receives externally input write data and write commands, and sends the write data and the write commands to the write controller. The write controller judges and schedules the write command, then sends the write command and the write data into a write buffer of the corresponding memory block, and then writes the write command and the write data into the corresponding memory block one by the write buffer.
The storage block group comprises N storage blocks and is a main cache carrier.
The read port group mainly provides N read ports on the read side, receives an externally input read command, and sends the read command to the read command buffer through the read controller. And according to the read command in the read command buffer, sequentially executing read operation on the storage blocks, delaying the read data in the read data buffer and sending the read data to the read port group, wherein the read port group receives the read data returned by the read data buffer and finally returns the read data to the read command initiator.
In this embodiment, a read-write method for the multi-port memory is provided, and fig. 4 is a flowchart according to an embodiment of the present invention, as shown in fig. 4, where the flowchart includes the following steps:
step S402, under the condition that write commands are received through a plurality of write ports, determining storage blocks corresponding to the write commands respectively;
in step S404, when there is a free buffer space in the write buffer of the memory block, the write command is scheduled to the corresponding write buffer to write the write data indicated by the write command into the memory block through the write buffer.
Before writing data into the multiport memory, the multiport memory is divided into K storage blocks in average according to the buffer capacity of the multiport memory, a write buffer and a read command buffer are configured for each storage block, and a read data buffer is configured for each read port.
The read method of the multi-port memory described above is not limited to being performed as a write controller of the multi-port memory. The relationship between the write controller and write port, memory block is not limited to that shown in fig. 5. Taking the port number n=2 and the storage block number k=4 as an example, two write ports are connected with a write controller, write commands and write data of the two write ports are distributed to write data buffers of four storage blocks in a scheduling manner among the write controllers, and each write data buffer is directly connected with the corresponding storage block.
After the write command and the write data reach the write ports, the write controller determines the storage blocks corresponding to the access addresses indicated by the write command, and judges whether conflicts exist among the write commands received by the current write ports. Whether there is a conflict between write commands received by the plurality of write ports is not limited to indicating whether the memory blocks corresponding to the access addresses indicated by the write commands received by the plurality of write ports are identical. In the case where the memory blocks indicated by at least two write commands are identical, it is not limited to queuing a plurality of write commands in the write buffers corresponding to the memory blocks to sequentially write the write data into the indicated memory blocks.
The write controller, after determining the memory blocks indicated by the respective write commands, is not limited to determining whether memory space in the write data buffer corresponding to the memory blocks is occupied. And when unoccupied buffer space exists in the write data buffer, sequentially dispatching write data corresponding to the write command into the corresponding write data buffer.
As an alternative embodiment, after determining the memory blocks corresponding to the respective write commands, the method further includes: and under the condition that the cache space in the write buffer of the storage block is occupied, blocking a write port for receiving the write command, and initiating the write command again in the next period.
If the write command fails because the current buffer space of the write data buffer of the storage block is occupied, the write port receiving the write command is blocked, and the write command is waited to be initiated again until the next period. If the write data is successfully written into the write data buffer, the write data is sequentially queued for writing into the memory block.
As an optional implementation manner, in the case that a read command is received through a plurality of read ports, determining a storage block corresponding to each read command; under the condition that an idle cache space exists in a read command buffer of a storage block, the read command is scheduled to the corresponding read command buffer, and a buffer grade is marked for the read command, so that the read data buffer feeds back read data indicated by the read command to the corresponding read port according to the buffer grade, wherein the buffer grade indicates the delay beat number of the read data in the read data buffer.
The read method of the multi-port memory is not limited to a read controller of the multi-port memory. When the read command reaches the read port, the read controller determines the storage block corresponding to the access address indicated by the read command, and judges whether conflict exists among the read commands received by the current plurality of read ports. Whether there is a conflict between the read commands received by the plurality of read ports is not limited to whether the memory blocks corresponding to the access addresses indicated by the read commands received by the plurality of read ports are identical. In the case where at least two read commands indicate the same memory block, it is not limited to queuing a plurality of read commands in the read command buffer corresponding to the memory block to sequentially read data from the indicated memory block.
The read controller, after determining the memory blocks indicated by the respective read commands, is not limited to determining whether the memory space of the read command buffer corresponding to the memory block is occupied. And when unoccupied buffer space exists in the read command buffer, sequentially scheduling the read commands to the corresponding read command buffer. The read commands are queued in sequence for execution of the read memory block during a read command buffer period.
As an optional implementation manner, after determining the memory blocks corresponding to the respective read commands, the method further includes: under the condition that the buffer space of the read command buffer of the storage block is occupied, the read port for receiving the read command is blocked, and the read command is initiated again in the next period.
If the current buffer space of the read command buffer of the storage block is occupied, the read port receiving the read command is blocked, and the read command is waited for the next period to be initiated again. If the read command is successfully written into the read command buffer, the buffer level is marked for the read command for controlling the delay beat number of the read data in the read data buffer.
As an alternative embodiment, scheduling the read command into the corresponding read command buffer and marking the buffer level for the read command includes: under the condition that at least two read commands correspond to the same storage block, caching the at least two read commands into a read command buffer corresponding to the storage block in sequence according to the priority, and marking a buffer level for each read command in sequence according to the caching sequence, wherein the buffer levels of the read commands are different.
The buffer level of each read command written into the same read command buffer is different, so that the delay level of read data in the read data buffer is controlled by the buffer level, and the output sequence of the read data is consistent with the sequence of the read commands received by the read port.
The relationship between the read controller and the read port, memory block is not limited to that shown in fig. 6. Taking the port number n=2 and the storage block number k=4 as an example, two read ports are connected with a read controller, and the read controller distributes two read port command schedules to the read command buffers corresponding to the four storage blocks respectively. The read commands in each read command buffer are sequentially waiting to be executed according to the queuing sequence, and the data read by the memory block are respectively stored in the read data buffers of the two read ports after being interleaved. By the marked different buffer levels, the delay levels of different read data outputs can be controlled in the read data buffer to ensure that the output sequence of the read data is consistent with the sequence of the read commands received by the read port.
As an alternative embodiment, marking the buffer level for each read command in turn in the buffer order includes: according to the buffer sequence of the read command buffer, determining the buffer position of the read command in the read command buffer; the buffer levels corresponding to the buffer positions in the read command buffer are marked for the read command, wherein the total number of levels of the buffer levels is consistent with the number of buffer positions in the read command buffer, and the number of levels of the buffer levels is positively correlated with the ordering of the buffer positions.
The marking method of the buffer grade marks the corresponding buffer grade of the read command according to the expected waiting time of the read command in the read command buffer, the buffer grade marks can reach the read data buffer along with the corresponding read data, and the buffer grade marks are stored into registers with different delay grades in the read data buffer according to different buffer grades.
Taking buffer level as an example, the buffer level marking and the indication of the read command and the read data processing method are carried out, and the buffer level is equal to the number of buffer positions in the read command buffer, so that the total number of storage positions in the read command buffer is 3. Taking two ports receiving a read command at the same time as an example, as shown in fig. 7, a read command 1 received through a read port 1 and a read command 2 received through a read port 2 simultaneously indicate the same memory block, after the read controller judges that the two ports collide, the two read commands are queued according to priority, and the command 1 is assumed to be queued before the command 2. Before commands 1 and 2 are stored in the read command buffer corresponding to the memory block, the read command buffer is empty. This means that command 1 does not need to wait, and can directly perform data reading, and command 2 needs to wait 1 cycle before performing data reading. The number of periods that a read command waits in line is counted as a buffer level, then the buffer level of command 1 is 0 and the buffer level of command 2 is 1. If there are other read commands scheduled to the read command buffer at this time, then the buffer level is 2, arranged after command 2.
The corresponding respective register changes in the read data buffer over the corresponding consecutive 3 cycles are shown in fig. 7.
At time 0, data read out by command 1: data 1 is read from the memory block and placed into a register with a buffer level of 0 according to the buffer level. Thereafter, the data is transferred to the register of the next buffer level every cycle.
At time 1, data 1 arrives at the register with buffer level 1. Data read out by command 2 at this time: and 2, after being read out by the storage block, the data is directly stored into a register with the buffer level of 1 according to the buffer level mark.
At time 2, data 1 and data 2 are transferred to the register with buffer level 2, respectively, and will be sent out to port 1 and port 2 simultaneously in the next cycle.
It is clear that by marking the buffer level, the plurality of read ports indicate that the read data does not collide in the read data buffer, and the register in the buffer level receives the data of the last buffer level or the data of the corresponding buffer level read by the storage block, and the read data do not arrive at the same time. Since the same port only receives at most one read command at the same time, corresponding read data will not collide in the read data buffer as long as the read command can correctly enter the read command buffer through the multi-port memory in the embodiment.
From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. Read-Only Memory/Random Access Memory, ROM/RAM), magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present invention.
The embodiment also provides a read-write device of the multiport memory, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
Fig. 8 is a block diagram of a read-write apparatus of a multiport memory according to an embodiment of the present invention, as shown in fig. 8, the apparatus includes: and a write controller 82 for determining, in the case of receiving write commands through the plurality of write ports, respective corresponding memory blocks of the write commands, and, in the case of a free buffer space in a write buffer of the memory blocks, scheduling the write commands to the corresponding write buffers to write the write data indicated by the write commands into the memory blocks through the write buffers.
Optionally, the above-mentioned controllable device 82 is further configured to block a write port that receives a write command and initiate the write command again in a next cycle, where the buffer space in the write buffer of the memory block is occupied after determining the memory block corresponding to each write command.
Optionally, the read-write device of the multiport memory further includes: and the read controller is used for determining a storage block corresponding to each read command when the read command is received through the plurality of read ports, scheduling the read command to the corresponding read command buffer when an idle buffer space exists in the read command buffer of the storage block, marking a buffer level for the read command, and enabling the read data buffer to feed back read data to the corresponding read port when the read data is received, wherein each storage block is provided with the corresponding read command buffer, and the buffer level indicates the time delay beat number of the read data indicated by the read command in the read data buffer.
Optionally, the above-mentioned read controller is further configured to block a read port for receiving a read command and initiate the read command again in a next cycle when the buffer space in the read command buffer of the memory block is occupied after determining the memory block corresponding to each read command.
Optionally, the reading controller schedules the reading command to a corresponding reading command buffer, marks a buffer level for the reading command, and includes: under the condition that at least two read commands correspond to the same storage block, caching the at least two read commands into a read command buffer corresponding to the storage block in sequence according to the priority, and marking a buffer level for each read command in sequence according to the caching sequence, wherein the buffer levels of the read commands are different.
Optionally, the reading controller marks the buffer level for each reading command in sequence according to the buffer sequence, including: according to the buffer sequence of the read command buffer, determining the buffer position of the read command in the read command buffer; the buffer levels corresponding to the buffer positions in the read command buffer are marked for the read command, wherein the total number of levels of the buffer levels is consistent with the number of buffer positions in the read command buffer, and the number of levels of the buffer levels is positively correlated with the ordering of the buffer positions.
It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; alternatively, the above modules may be located in different processors in any combination.
In order to facilitate understanding of the technical solutions provided by the present invention, the following details will be described in connection with embodiments of specific scenarios.
Embodiments of the present invention also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.
In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.
An embodiment of the invention also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.
In an exemplary embodiment, the electronic apparatus may further include a transmission device connected to the processor, and an input/output device connected to the processor.
Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.
It will be appreciated by those skilled in the art that the modules or steps of the invention described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The above description is only of the preferred embodiments of the present invention and is not intended to limit the present invention, but various modifications and variations can be made to the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present invention should be included in the protection scope of the present invention.
Claims (12)
1. A multi-port memory, comprising: n write ports, a write controller, K write buffers and a memory block group, wherein,
the storage block group comprises K storage blocks, wherein K is greater than N;
the write port is used for receiving an externally input write command and write data and outputting the write command and the write data to the write controller;
the write controller is used for dispatching the write command and the write data to the corresponding write buffer;
the write buffers are used for caching write data to be written into the storage blocks, wherein one write buffer corresponds to one storage block.
2. The multi-port memory of claim 1 further comprising N read ports, a read controller, K read command buffers, and N read data buffers, wherein,
the read port is used for receiving an externally input read command and outputting the read command to the read controller;
the read controller is used for dispatching the read command to a corresponding read command buffer;
a read command buffer for buffering a read command for reading a corresponding memory block, wherein one read command buffer corresponds to one memory block;
and the read data buffers are used for buffering the data which is read out from the storage block and is to be output to the corresponding read ports, wherein one read data buffer corresponds to one read port.
3. A method for reading from and writing to a multi-port memory according to any of claims 1-2, the method comprising:
under the condition that write commands are received through a plurality of write ports, determining storage blocks corresponding to the write commands respectively;
and under the condition that free cache space exists in a write buffer of the storage block, scheduling the write command into the corresponding write buffer so as to write the write data indicated by the write command into the storage block through the write buffer.
4. The method of claim 3, further comprising, after determining the respective memory block for each write command:
and under the condition that the cache space in the write buffer of the storage block is occupied, blocking a write port for receiving the write command, and initiating the write command again in the next period.
5. A method according to claim 3, characterized in that the method further comprises:
under the condition that read commands are received through a plurality of read ports, determining storage blocks corresponding to the read commands respectively;
and under the condition that an idle cache space exists in a read command buffer of the storage block, scheduling the read command into the corresponding read command buffer, and marking a buffer level for the read command so that a read data buffer feeds back read data indicated by the read command to a corresponding read port according to the buffer level, wherein the buffer level indicates the delay beat number of the read data in the read data buffer.
6. The method of claim 5, further comprising, after determining the respective memory block for each read command:
and under the condition that the buffer memory space in the read command buffer of the storage block is occupied, blocking a read port for receiving the read command, and initiating the read command again in the next period.
7. The method of claim 5, wherein scheduling the read command into the corresponding read command buffer and marking the read command with a buffer level comprises:
and under the condition that at least two read commands correspond to the same storage block, caching the at least two read commands into a read command buffer corresponding to the storage block in sequence according to the priority, and marking a buffer level for each read command in sequence according to the caching sequence, wherein the buffer levels of the read commands are different.
8. The method of claim 7, wherein marking the buffer level for each read command in turn in the buffer order comprises:
determining a buffer position of the read command in the read command buffer according to the buffer sequence of the read command buffer;
marking the buffer level corresponding to the buffer position in the read command buffer for the read command, wherein the total level of the buffer level is consistent with the number of the buffer positions in the read command buffer, and the level of the buffer level is positively correlated with the ordering of the buffer positions.
9. A read-write apparatus for a multiport memory, comprising:
and the write controller is used for determining a storage block corresponding to each write command when the write commands are received through a plurality of write ports, and scheduling the write commands to the corresponding write buffers when free buffer spaces exist in the write buffers of the storage blocks so as to write the write data indicated by the write commands into the storage blocks through the write buffers.
10. The apparatus as recited in claim 9, further comprising:
and the read controller is used for determining a storage block corresponding to each read command when the read command is received through a plurality of read ports, scheduling the read command into the corresponding read command buffer when an idle buffer space exists in the read command buffer of the storage block, and marking a buffer level for the read command so that the read data buffer feeds back read data to the corresponding read port when the read data is received, wherein each storage block is provided with the corresponding read command buffer, and the buffer level indicates the delay beat number of the read data indicated by the read command in the read data buffer.
11. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method according to any of the claims 3 to 8.
12. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method as claimed in any one of claims 3 to 8 when the computer program is executed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210765522.5A CN117373508A (en) | 2022-06-30 | 2022-06-30 | Multiport memory, read-write method and device of multiport memory |
| PCT/CN2023/083179 WO2024001332A1 (en) | 2022-06-30 | 2023-03-22 | Multi-port memory, and reading and writing method and apparatus for multi-port memory |
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| CN202210765522.5A CN117373508A (en) | 2022-06-30 | 2022-06-30 | Multiport memory, read-write method and device of multiport memory |
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| KR100546331B1 (en) * | 2003-06-03 | 2006-01-26 | 삼성전자주식회사 | Multi-Port memory device with stacked banks |
| US9128850B2 (en) * | 2012-08-16 | 2015-09-08 | Broadcom Corporation | Multi-ported memory with multiple access support |
| US10089018B2 (en) * | 2015-05-07 | 2018-10-02 | Marvell Israel (M.I.S.L) Ltd. | Multi-bank memory with multiple read ports and multiple write ports per cycle |
| US10360952B2 (en) * | 2016-12-20 | 2019-07-23 | Omnivision Technologies, Inc. | Multiport memory architecture for simultaneous transfer |
| CN112052206B (en) * | 2020-08-31 | 2023-03-28 | 浙江双成电气有限公司 | Multi-port data storage system based on arbitration |
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