CN110109626A - A kind of NVMe SSD command handling method based on FPGA - Google Patents
A kind of NVMe SSD command handling method based on FPGA Download PDFInfo
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- CN110109626A CN110109626A CN201910420004.8A CN201910420004A CN110109626A CN 110109626 A CN110109626 A CN 110109626A CN 201910420004 A CN201910420004 A CN 201910420004A CN 110109626 A CN110109626 A CN 110109626A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
A kind of NVMe SSD command handling method based on FPGA, it belongs to technical field of data storage.The problem of present invention is solved as the order increase or order type of NVMe SSD read-write operation increase, and the complexity of flow control state machine increases.The present invention is designed NVMe SSD command process process control module, and a variety of orders execution process is combined, all orders can be realized using a simple flow control state machine and execute process, convenient for exploitation and maintenance；And while assurance function is complete, optimize the number of states and state jump condition of flow control state machine, reduce the time overhead of judgment step in flow control state machine, improve development efficiency, it is compared with the traditional method, 43% trigger resources and 65% look-up table resource inside FPGA can be saved using the method for the present invention.Present invention could apply to technical field of data storage.
Description
Technical field
The invention belongs to technical field of data storage, and in particular to a kind of NVMe SSD command handling method.
Background technique
High-speed data storage apparatus is widely used in fields such as high-speed data acquisition, cloud storages.In order to improve storage equipment
Read or write speed, reduce the volume and power consumption of equipment, adapt to the development trend of miniaturization, densification, can use field of storage
Emerging NVMe SSD stores equipment to construct portable high-speed.Equipment utilization FPGA may be implemented to be up to as control chip
1GByte/s's or more is continuously written into speed.
It realizes that the key of FPGA control NVMe SSD function is to control the design of software FPGA, Verilog can be used
Language writes a flow control state machine to realize NVMe command process process.According to the content of NVMe agreement, NVMe SSD
Eight big steps can be divided by executing read write command, and each step includes the transmission of several PCIe data packets.Work as read write command
When the data volume for needing to transmit is very big, the PCIe data packet transmitted in a corresponding order process is also more；When realizing
NVMe order increase or order type is when increasing, the state of flow control state machine can also increase, so as to cause Row control
The problems such as complexity of state machine increases, consumption fpga logic resource increases.
Summary of the invention
The purpose of the present invention is to solve to increase with the order increase or order type of NVMe SSD read-write operation, process
The problem of complexity of state of a control machine increases.
The technical solution adopted by the present invention to solve the above technical problem is: at a kind of NVMe SSD order based on FPGA
Reason method, method includes the following steps:
Step A1, FPGA receives more newer command after user command and submits queue, and to NVMe (Non-Volatile
Memory express, Nonvolatile memory host controller interface specification) SSD (solid state hard disk) transmission write register request,
Rear of queue doorbell register (SQ Tail DB register, Submission Queue are submitted in the order updated in NVMe SSD
Tail Doorbell), go to step A2；
Step A2, FPGA enters wait state, and judges whether to receive data packet, when FPGA receives data packet,
Go to step A3；
Step A3, judge whether received data packet is to write memory request, if writing memory request, is then gone to step
A4；Otherwise, go to step A8；
Step A4, judge whether received data packet is write data requests；If write data requests, then FPGA receive from
The data that NVMe SSD is read, go to step A2；Otherwise, go to step A5；
Step A5, judge whether received data packet is that write order completes queue request, if write order is completed queue and asked
It asks, then go to step A6；Otherwise, go to step A12；
Step A6, judge order whether successful execution, if successful execution, more newer command complete queue, go to step
A7；Otherwise, go to step A12；
Step A7, FPGA writes memory request to NVMe SSD transmission, and queue heads door is completed in the order updated in NVMe SSD
Bell register (CQ Head DB register, Completion Queue Head Doorbell), go to step A13；
Step A8, judge whether received data packet is that rdma read request then gos to step if rdma read is requested
A9；Otherwise, go to step A12；
Step A9, judge whether received data packet is that queue request is submitted in read command, if read command submits queue to ask
It asks, then FPGA is sent completely message, returns to NVMe command information, go to step A2；Otherwise, go to step A10；
Step A10, judge whether received data packet is read address list request, if read address list request, then
FPGA is sent completely message, and return address list information, go to step A2；Otherwise, go to step A11；
Step A11, judge whether received data packet is read data request, if read data request, then FPGA has been sent
At message, the data to be stored are returned to, go to step A2；Otherwise, go to step A12；
Step A12, it reports an error, go to step A13；
Step A13, terminate.
The beneficial effects of the present invention are: a kind of NVMe SSD command handling method based on FPGA of the invention, the present invention
NVMe SSD command process process control module is designed, a variety of orders execution process is combined, it is simple using one
Flow control state machine all orders can be realized execute processes, convenient for exploitation and maintenance；And it is complete in assurance function
Meanwhile the number of states and state jump condition of flow control state machine are optimized, reduce in flow control state machine and judges
The time overhead of step, improves development efficiency, is compared with the traditional method, and can be saved inside FPGA using the method for the present invention
43% trigger resources and 65% look-up table resource.
Detailed description of the invention
Fig. 1 is a kind of flow chart of NVMe SSD command handling method based on FPGA of the invention；
Fig. 2 is the order control flow chart of existing NVMe SSD；
Fig. 3 is the process flow diagram of existing NVMe SSD read write command；
Fig. 4 is the process flow diagram that existing NVMe SSD obtains status information order；
Fig. 5 is the process flow diagram of existing NVMe SSD queue management, clear command；
Fig. 6 is the flow chart that step A4 of the invention judges data packet corresponding function；
Fig. 7 is the flow chart that the present invention updates that queue doorbell register is submitted in order in NVMe SSD；
Fig. 8 is the flow chart that the present invention updates that queue doorbell register is completed in order in NVMe SSD；
Fig. 9 is that FPGA of the present invention returns to the flow chart for completing message.
Specific embodiment
Specific embodiment 1: as shown in Figure 1, at a kind of NVMe SSD order based on FPGA described in present embodiment
Reason method, method includes the following steps:
Step A1, queue is submitted in more newer command after FPGA receives user command, and writes register to NVMe SSD transmission
Rear of queue doorbell register is submitted in request, the order updated in NVMe SSD, and go to step A2；
Step A2, FPGA enters wait state, and judges whether to receive data packet, when FPGA receives data packet,
Go to step A3；
Step A3, judge whether received data packet is to write memory request, if writing memory request, is then gone to step
A4；Otherwise, go to step A8；
Step A4, judge whether received data packet is write data requests；If write data requests, then FPGA receive from
The data that NVMe SSD is read, go to step A2；Otherwise, go to step A5；
Step A5, judge whether received data packet is that write order completes queue request, if write order is completed queue and asked
It asks, then go to step A6；Otherwise, go to step A12；
Step A6, judge order whether successful execution, if successful execution, more newer command complete queue, go to step
A7；Otherwise, go to step A12；
Step A7, FPGA writes memory request to NVMe SSD transmission, and queue heads door is completed in the order updated in NVMe SSD
Bell register, go to step A13；
Step A8, judge whether received data packet is that rdma read request then gos to step if rdma read is requested
A9；Otherwise, go to step A12；
Step A9, judge whether received data packet is that queue request is submitted in read command, if read command submits queue to ask
It asks, then FPGA is sent completely message, returns to NVMe command information, go to step A2；Otherwise, go to step A10；
Step A10, judge whether received data packet is read address list request, if read address list request, then
FPGA is sent completely message, and return address list information, go to step A2；Otherwise, go to step A11；
Step A11, judge whether received data packet is read data request, if read data request, then FPGA has been sent
At message, the data to be stored are returned to, go to step A2；Otherwise, go to step A12；
Step A12, it reports an error, go to step A13；
Step A13, terminate.
NVMe SSD command process process is by NVMe host (being FPGA in the present invention) and NVMe equipment (NVMe SSD) is altogether
With participation.FPGA host sends read write command to NVMe SSD, sends data to be stored and receives the number read from NVMe SSD
According to.Register relevant to NVMe SSD order control includes the doorbell in command queue's register and NVMe SSD in FPGA
Register.The order control flow of NVMe SSD is as shown in Figure 2 in existing method.
Step 1, host submit the order that write-in is new in queue (Submission Queue) to order；
Rear of queue doorbell register (SQ Tail Doorbell) is submitted in the order of step 2, host more new equipment, and notice is set
Have newer command；
Step 3, equipment send rdma read request to host, and the order of corresponding address in queue is returned to equipment by host；
Step 4, equipment execute order；
Step 5, equipment write memory request to host transmission, and queue (Completion is completed in the order updated in host
Queue)；
Step 6, equipment send MSI-X to host and interrupt, and host inspection order is reminded to complete queue；
Step 7, host complete the case pointer in queue according to order and judge whether order is completed；
Queue heads doorbell register (CQ Head Doorbell) is completed in the order of step 8, host more new equipment, and notice is set
Standby order is completed；
Wherein step 4 includes that processing reads address list request, reads the data transmission such as request of data, write-in request of data
Process, specific as follows:
(1) address of equipment address list according to defined in order sends rdma read request to host；
(2) host returns to the completion message comprising address list to equipment；If equipment executes write order, go to step
(3)；If equipment executes read command, go to step (5)；
(3) equipment sends rdma read request to host according to the address information in address list；
(4) host returns to the completion message comprising data to be written to equipment；
(5) equipment writes memory request to host transmission according to the address information in address list, and the data of reading are sent
To host；
Order using the FPGA control NVMe SSD realization for being written and read needs includes: queue management order, reads
Write order, obtains status information order at clear command.
The process flow of NVMe SSD read write command is as shown in figure 3, NVMe SSD obtains the processing stream of status information order
Journey is as shown in figure 4, NVMe SSD queue management, the process flow of clear command are as shown in Figure 5.
Comprehensively consider the execution process of above several orders, order as shown in connection with fig. 2 executes process frame and can be found that
Following rule:
1, in NVMe SSD command process process, in addition to step 4, it is identical that others order executes process；
2, in NVMe SSD command process process, step 1 and 7 is completed inside FPGA, does not generate the number with NVMe SSD
According to interaction；
3, when executing step 2 and 8, FPGA initiates data transmission as the main equipment of PCIe bus, in NVMe SSD
Doorbell register is configured；
4, when executing step 3~5, NVMe SSD initiates data transmission as the main equipment of PCIe bus, in access FPGA
Command queue and memory headroom etc.；
5, the MSI-X of step 6 is interrupted for reminding host inspection order to complete queue.Since the parallel characteristics of FPGA allow
Its real-time monitoring order completes queue and does not influence the execution of other control flows, therefore can close the MSI-X of NVMe SSD
Interrupt function omits the step.
In brief, NVMe order control flow can be divided into the order of FPGA processing locality, FPGA configuration NVMe SSD is posted
Storage and NVMe SSD initiate data and transmit three parts.According to the above rule, the present invention provides control flow as shown in Figure 1.
In the judgment step of process shown in Fig. 1, for indicating data packet " class in the data packet head that FPGA parsing receives
The field of type " (Format+Type), judge data packet is to read or write to the operation of memory headroom；FPGA parsing is received
" address " (Address) information in data packet head obtains the memory headroom address to be accessed, and corresponding according to the memory headroom
Function judge the concrete function of data packet.NVMe SSD is written in the address of the corresponding memory headroom of different function by the present invention
Control register in, when NVMe SSD want obtain certain information or realize a certain item function when, it is only necessary to send include phase
After answering the data packet of " type " and " address ", FPGA to receive the request from NVMe SSD, corresponding data packet is returned
Realize the data interaction between NVMe SSD and FPGA.
Memory headroom address, corresponding function in the FPGA that the present invention defines and the NVMe for storing these addresses
The address of SSD register is as shown in table 1 below:
The address of memory headroom and corresponding effect in 1 FPGA of table
| The address of memory headroom in FPGA | The corresponding function of memory headroom |
| 0x08005000~0x08005100 | Storage address list |
| 0x00000000~0x00001000 | Store command submits queue |
| 0x00001000~0x00002000 | Store command completes queue |
| 0x01000000~0x07000000 | Store the data to be read and write |
Specific embodiment 2: as shown in fig. 6, the present embodiment is different from the first embodiment in that: the step
Judge whether received data packet is write data requests, detailed process in A4 are as follows:
Step B1, FPGA parses address information from the data packet head received, and the B2 that gos to step；
Step B2, whether the address information that judgment step B1 is parsed within the scope of 0x01000000~0x07000000,
If so, the B4 that gos to step, otherwise, go to step B3；
Step B3, go to step A5, terminates；
Step B4, the function of judging the data packet that FPGA is received is that FPGA is written in the data read from NVMe SSD
In, and the B5 that gos to step；
Step B5, go to step A2, terminates.
Step A5, A9, A10, A11 of the invention is similar with above-mentioned step A4 deterministic process.
One NVMe SSD corresponds to multiple command queues and doorbell register.Specifically, a NVMe SSD is corresponding
Queue is submitted in one administration order, and queue is completed in an administration order, and multiple I/O orders submit queue and multiple I/O orders complete
At queue.There is the corresponding doorbell register of these command queues in NVMe SSD, for storing the information end to end of respective queue.
Register address of these doorbell registers in NVMe SSD is as shown in table 2 below:
Doorbell register address in 2 NVMe SSD of table
| Doorbell register type | Address in NVMe SSD |
| Rear of queue doorbell register is submitted in administration order | 0x28~0x2f |
| Queue heads doorbell register is completed in administration order | 0x30~0x37 |
| Rear of queue doorbell register (n-th) is submitted in I/O order | 0x1000+4* (2n-2)~0x1003+4* (2n-2) |
| Queue heads doorbell register (n-th) is completed in I/O order | 0x1000+4* (2n-1)~0x1003+4* (2n-1) |
Specific embodiment 3: as shown in fig. 7, the present embodiment is different from the first embodiment in that: the step
Rear of queue doorbell register, detailed process are submitted in the order of A1 updated in NVMe SSD are as follows:
Step C1, judge that the number of queue (Submission Queue) is submitted in the order updated inside FPGA；
Step C2, it submits the value of the tail doorbell register to be updated in queue to add 1 the order updated inside FPGA, obtains
The value for the tail doorbell register to be updated；
Step C3, according to the address of the number determination of the step C1 tail doorbell register to be updated；
Step C4, the value that the address obtained step C3 and step C2 obtain is packaged, and the order class in supplementary data packet header
Type (format+type) information, length (length) information, number (Tag) information and request device identification (requester
ID) information；
Step C5, PCIe (peripheral component interconnect express, high speed serialization meter are sent
Calculation machine expansion bus) data packet；
Step C6, terminate.
Specific embodiment 4: as shown in figure 8, the present embodiment is different from the first embodiment in that: the step
Queue heads doorbell register, detailed process are completed in the order of A7 updated in NVMe SSD are as follows:
Step D1, FPGA parse the completion queue identity in received order completion entry；
Step D2, according to the address of the completion queue identity determination head doorbell register to be updated parsed；
Entry, the value of the determination head doorbell register to be updated are completed in step D3, FPGA processing order；
Step D4, the address for the head doorbell register that will be updated and value are packaged, and the command type in supplementary data packet header
(format+type) information, length (length) information, number (Tag) information and request device identification (requester ID)
Information；
Step D5 sends PCIe data packet；
Step D6 terminates.
Specific embodiment 5: as shown in figure 9, the present embodiment is different from the first embodiment in that: the step
FPGA in A9, A10 and A11 is sent completely message, detailed process are as follows:
Step E1, FPGA parses the address in received rdma read request data packet header, records the volume in current data packet header
Number field；
Step E2, FPGA reads data from the memory for the address that step E1 is parsed；
The data that the number field of step E1 and step E2 are read are packaged by step E3, and the order in supplementary data packet header
Type (format+type) information, length (length) information, number (Tag) information and request device identification (requester
ID) information；
Step E4 sends PCIe data packet；
Step E5 terminates.
Specific embodiment 6: the present embodiment is different from the first embodiment in that: the FPGA receives data
For indicating the field of type of data packet in the data packet head that receives of Bao Shi, FPGA parsing, judge data packet to memory
The operation in space is to read or write；The address information in data packet head that FPGA parsing receives, obtains the memory headroom to be accessed
Address, and judge according to the corresponding function in the memory headroom address concrete function of data packet.
A wait state is arranged in the present invention, in wait state scanning FIFO caching.It is new when being read from FIFO caching
When data packet, FPGA judges the type of data packet, and executes corresponding operation.Multiple orders execution process is merged by the design
As soon as total order executes process, it can control multiple orders using a flow control state machine and execute process, convenient for exploitation
And maintenance, and save the logical resource inside FPGA.Simultaneously for the continuous judgment step in Fig. 1 dotted line frame, use
" if-else if-else " sentence can judge these in 1 clock cycle (8ns) by the parallel characteristics of FPGA
Journey is finished, to keep time overhead caused by FPGA execution judgment step very small, accelerates FPGA control indirectly
The speed of NVMe SSD execution read write command.In addition, the present invention closes MSI-X by configuring the control register of NVMe SSD
Interrupt function is interrupted so NVMe SSD will not send MSI-X to FPGA, this also further simplifies the design work of related software
Make, the state for waiting and judging that MSI-X is interrupted in flow control state machine is omitted.
In order to embody the advantage of design method proposed by the present invention, respectively to this in the control flow and Fig. 1 in Fig. 3,4,5
The control flow of invention is realized, and other functional modules are omitted to protrude process control module during realization
Logical resource Expenditure Levels.Traditional Row control scheme occupies 14 triggers and 46 look-up tables, this hair as the result is shown
The scheme of bright proposition has only taken up 8 triggers and 16 look-up tables, i.e., scheme proposed by the present invention is divided compared with traditional scheme
43% and 65% trigger and look-up table resource are not saved.
Above-mentioned example of the invention only explains computation model and calculation process of the invention in detail, and is not to this
The restriction of the embodiment of invention.It for those of ordinary skill in the art, on the basis of the above description can be with
It makes other variations or changes in different ways, all embodiments can not be exhaustive here, it is all to belong to the present invention
The obvious changes or variations extended out of technical solution still in the scope of protection of the present invention.
Claims (6)
1. a kind of NVMe SSD command handling method based on FPGA, which is characterized in that method includes the following steps:
Step A1, queue is submitted in more newer command after FPGA receives user command, and writes register request to NVMe SSD transmission,
Rear of queue doorbell register is submitted in the order updated in NVMe SSD, and go to step A2；
Step A2, FPGA enters wait state, and judges whether to receive data packet, when FPGA receives data packet, jumps
To step A3；
Step A3, judge whether received data packet is to write memory request, if writing memory request, then go to step A4；It is no
Then, go to step A8；
Step A4, judge whether received data packet is write data requests；If write data requests, then FPGA is received from NVMe
The data that SSD is read, go to step A2；Otherwise, go to step A5；
Step A5, judge whether received data packet is that write order completes queue request, if write order completes queue request, then
Go to step A6；Otherwise, go to step A12；
Step A6, judge order whether successful execution, if successful execution, more newer command complete queue, go to step A7；It is no
Then, go to step A12；
Step A7, FPGA writes memory request to NVMe SSD transmission, and the order completion queue heads doorbell updated in NVMe SSD is posted
Storage, go to step A13；
Step A8, judge whether received data packet is rdma read request, if rdma read is requested, then go to step A9；It is no
Then, go to step A12；
Step A9, judge whether received data packet is that queue request is submitted in read command, if queue request is submitted in read command, then
FPGA is sent completely message, returns to NVMe command information, go to step A2；Otherwise, go to step A10；
Step A10, judge whether received data packet is read address list request, if read address list request, then FPGA is sent out
It send and completes message, return address list information, go to step A2；Otherwise, go to step A11；
Step A11, judge whether received data packet is read data request, if read data request, then FPGA is sent completely report
Text returns to the data to be stored, and go to step A2；Otherwise, go to step A12；
Step A12, it reports an error, go to step A13；
Step A13, terminate.
2. a kind of NVMe SSD command handling method based on FPGA according to claim 1, which is characterized in that the step
Judge whether received data packet is write data requests, detailed process in rapid A4 are as follows:
Step B1, FPGA parses address information from the data packet head received, and the B2 that gos to step；
Step B2, whether the address information that judgment step B1 is parsed within the scope of 0x01000000~0x07000000, if so,
Then go to step B4, and otherwise, go to step B3；
Step B3, go to step A5, terminates；
Step B4, the function of judging the data packet that FPGA is received is will to be written in FPGA from the data that NVMe SSD is read,
And the B5 that gos to step；
Step B5, go to step A2, terminates.
3. a kind of NVMe SSD command handling method based on FPGA according to claim 1, which is characterized in that the step
Rear of queue doorbell register, detailed process are submitted in the order of rapid A1 updated in NVMe SSD are as follows:
Step C1, judge that the number of queue is submitted in the order updated inside FPGA；
Step C2, the value of the tail doorbell register to be updated in queue is submitted to add 1 the order updated inside FPGA, acquisition will be more
The value of new tail doorbell register；
Step C3, according to the address of the number determination of the step C1 tail doorbell register to be updated；
Step C4, the value that the address obtained step C3 and step C2 obtain is packaged, and the command type letter in supplementary data packet header
Breath, length information, number information and request equipment identification information；
Step C5, PCIe data packet is sent；
Step C6, terminate.
4. a kind of NVMe SSD command handling method based on FPGA according to claim 1, which is characterized in that the step
Queue heads doorbell register, detailed process are completed in the order of rapid A7 updated in NVMe SSD are as follows:
Step D1, FPGA parse the completion queue identity in received order completion entry；
Step D2, according to the address of the completion queue identity determination head doorbell register to be updated parsed；
Entry, the value of the determination head doorbell register to be updated are completed in step D3, FPGA processing order；
Step D4, the address for the head doorbell register that will be updated and value are packaged, and the command type information in supplementary data packet header,
Length information, number information and request equipment identification information；
Step D5 sends PCIe data packet；
Step D6 terminates.
5. a kind of NVMe SSD command handling method based on FPGA according to claim 1, which is characterized in that the step
FPGA in rapid A9, A10 and A11 is sent completely message, detailed process are as follows:
Step E1, FPGA parses the address in received rdma read request data packet header, records the number word in current data packet header
Section；
Step E2, FPGA reads data from the memory for the address that step E1 is parsed；
The data that the number field of step E1 and step E2 are read are packaged by step E3, and the command type in supplementary data packet header
Information, length information, number information and request equipment identification information；
Step E4 sends PCIe data packet；
Step E5 terminates.
6. a kind of NVMe SSD command handling method based on FPGA according to claim 1, which is characterized in that described
When FPGA receives data packet, for indicating the field of type of data packet in the data packet head that FPGA parsing receives, judge
Data packet is to read or write to the operation of memory headroom；The address information in data packet head that FPGA parsing receives,
The memory headroom address of access, and judge according to the corresponding function in the memory headroom address concrete function of data packet.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111124959A (en) * | 2019-12-12 | 2020-05-08 | 北京计算机技术及应用研究所 | Hardware unloading method for processing NVMe protocol management command |
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| CN111124959A (en) * | 2019-12-12 | 2020-05-08 | 北京计算机技术及应用研究所 | Hardware unloading method for processing NVMe protocol management command |
| CN111221476A (en) * | 2020-01-08 | 2020-06-02 | 深圳忆联信息系统有限公司 | Front-end command processing method and device for improving SSD performance, computer equipment and storage medium |
| CN111221476B (en) * | 2020-01-08 | 2022-03-29 | 深圳忆联信息系统有限公司 | Front-end command processing method and device for improving SSD performance, computer equipment and storage medium |
| CN111966303A (en) * | 2020-09-02 | 2020-11-20 | 深圳大普微电子科技有限公司 | Data processing method, system, equipment and readable storage medium |
| CN111966303B (en) * | 2020-09-02 | 2024-03-19 | 深圳大普微电子科技有限公司 | Data processing method, system, equipment and readable storage medium |
| CN112256601A (en) * | 2020-10-19 | 2021-01-22 | 凌云光技术股份有限公司 | Data access control method, embedded storage system and embedded equipment |
| CN112732176A (en) * | 2020-12-28 | 2021-04-30 | 武汉船舶通信研究所（中国船舶重工集团公司第七二二研究所） | SSD (solid State disk) access method and device based on FPGA (field programmable Gate array), storage system and storage medium |
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| CN114968856A (en) * | 2021-02-18 | 2022-08-30 | 爱思开海力士有限公司 | Memory system and operating method thereof |
| CN114968856B (en) * | 2021-02-18 | 2024-05-28 | 爱思开海力士有限公司 | Memory system and method of operating the same |
| CN115586867A (en) * | 2022-09-27 | 2023-01-10 | 中科驭数（北京）科技有限公司 | NVMe controller |
| CN115586867B (en) * | 2022-09-27 | 2023-08-22 | 中科驭数（北京）科技有限公司 | NVMe controller |
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