CN110322979A - Nuclear power station digital control computer system core processing unit based on FPGA - Google Patents
Nuclear power station digital control computer system core processing unit based on FPGA Download PDFInfo
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- CN110322979A CN110322979A CN201910677721.9A CN201910677721A CN110322979A CN 110322979 A CN110322979 A CN 110322979A CN 201910677721 A CN201910677721 A CN 201910677721A CN 110322979 A CN110322979 A CN 110322979A
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- 238000012545 processing Methods 0.000 title claims abstract description 40
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- 230000003993 interaction Effects 0.000 claims abstract description 17
- 230000002452 interceptive effect Effects 0.000 claims description 44
- 238000013507 mapping Methods 0.000 claims description 40
- 238000012937 correction Methods 0.000 claims description 24
- 238000012795 verification Methods 0.000 claims description 16
- 230000005540 biological transmission Effects 0.000 claims description 7
- 238000004458 analytical method Methods 0.000 claims description 6
- 238000005516 engineering process Methods 0.000 claims description 6
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- 238000004364 calculation method Methods 0.000 claims description 3
- 230000006870 function Effects 0.000 description 7
- 238000005457 optimization Methods 0.000 description 7
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- 238000013461 design Methods 0.000 description 5
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- 230000008901 benefit Effects 0.000 description 2
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Classifications
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- G—PHYSICS
- G21—NUCLEAR PHYSICS; NUCLEAR ENGINEERING
- G21D—NUCLEAR POWER PLANT
- G21D3/00—Control of nuclear power plant
- G21D3/001—Computer implemented control
- G21D3/002—Core design; core simulations; core optimisation
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E30/00—Energy generation of nuclear origin
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Abstract
Nuclear power station digital control computer system core processing unit based on FPGA, including processor board, mapped cache board, memory board and preferential Read Controller board, it is connected between the processor board and mapped cache board by data/address bus and address bus, pass through interaction bus and storage bus connection between the mapped cache board and memory board, pass through storage bus connection between the memory board and preferential Read Controller board, the processor board, the framework that mapped cache board and memory board are all made of non-volatile FPGA and SRAM cooperation is constituted, the preferential reading Control card is constituted using non-volatile fpga chip, lower power consumption, reduce the probability of error, improve the speed of service of system.
Description
Technical field
It is specifically exactly a kind of based on FPGA the present invention relates to nuclear power station digital control computer systems technology field
Nuclear power station digital control computer system core processing unit, i.e., a kind of digital control computer system CPU core processing unit
Board design, using non-volatile fpga chip add SRAM framework realize core processing unit hardware design.
Background technique
The digital control computer system of domestic nuclear power at present, CPU are based on PAL+ logic device architecture, using big
The PAL logic chip and logic chip of amount, which are built, realizes SSCI-890 core processing unit.At current SSCI-890 core
Reason unit is made of the big main board of core processing board, caching function board, memory board and preferential Read Controller four.
The PAL chip and logical device being related to are large number of, and over time, the development speed of logical device is very rapid,
The producer of PAL component stops production substantially, being seriously unable to satisfy nuclear power station and run steadily in the long term with aging.So needs pair
The control system of nuclear power station carries out stablizing transformation, during transformation, selects non-volatile FPGA to PAL device and logic device
Part improves.
The processor board of SSCI-890 core processing unit is by 60 multi-disc PAL chips, 40 multi-disc logic chips and lacks
The designs such as sram chip are measured to complete；Mapped cache board is by 40 multi-disc PAL chips, 40 multi-disc logic chips and a small amount of SRAM core
The designs such as piece are completed；Memory board has been designed by 10 multi-disc PAL chips, 20 multi-disc logic chips and a small amount of sram chip etc.
At；The preferential Control card that reads is completed by designs such as multi-disc PAL chip, 20 multi-disc logic chips, and raw sheet card composition power consumption is big, device
Number of packages amount is more, and maintenance difficulties are high.
Summary of the invention
The nuclear power station digital control computer system core based on FPGA that the purpose of the present invention is to provide a kind of handles single
Member adds the structure of SRAM to be designed improvement the core processing unit on hardware configuration using non-volatile fpga chip,
Finally realize its basic function.
The technical scheme adopted by the invention to solve the technical problem is that: the nuclear power station digital control computer based on FPGA
System core processing unit, including processor board, mapped cache board, memory board and preferential Read Controller board,
It is connected between the processor board and mapped cache board by data/address bus and address bus, the mapped cache plate
It is connected between card and memory board by interaction bus and storage bus, the memory board and preferential Read Controller
By storage bus connection between board, the processor board, mapped cache board and memory board are all made of non-easy
The framework of the property lost FPGA and SRAM cooperation is constituted, and the preferential reading Control card is constituted using non-volatile fpga chip.
As optimization, the processor board includes non-volatile FPGA module and SRAM module, and described is non-volatile
Property FPGA module include command analysis module, data calculate and memory module, the control of virtual terminal and interactive module, power down weight
Open module and initialization module.
As optimization, the command analysis module includes: instruction cache module, microcommand decoder module, microcommand meter
Number device blocks, microinstruction address memory module, address jump module, storing data decoder module I, storing data decoder module II,
Dedicated decoder module；
The data calculate and memory module includes: that data calculate and logic processing module, program counter module, register
File storage module, accumulator module, flag register module, write make can control memory module, control memory module；
The control of the virtual terminal and interactive module include: terminal interaction module, serial bus module, BYTE MASK mould
Block, cache bus module, lteral data drive module；
The cache bus module and instruction cache module is connect with caching board bus, and the cache bus module passes through
BYTE MASK module and data calculate and logic processing module connect, the data calculating and logic processing module respectively with tire out
Device module, flag register module, program counter module is added to connect with register file memory module, the data calculate
Also pass through with logic processing module mathematical logic output module with caching board bus connect, the accumulator module respectively with
Terminal interaction module is connected with microcommand decoder module, and the terminal interaction module is also by BYTE MASK module and data meter
Calculation is connected with logic processing module；The microcommand decoder module respectively with control memory module and write and make can control storage mould
Block connection, the subsequence counter module are connect with microinstruction address memory module, and the microinstruction address stores mould
Block is connect with address jump module, and described writing makes to can control memory module and also connect with caching board bus, the storage
Data decoder module I, storing data decoder module II and dedicated decoder module are connect with lteral data drive module, described
Lteral data drive module is connect with caching board bus.
As optimization, the mapped cache board includes non-volatile FPGA module and SRAM module, and described is non-easy
The property lost FPGA module includes memory mapping block, real-time clock generation module, input and output sorting module, memory interactive module
With program instruction memory module.
As optimization, the memory mapping block includes: physical address drive module, mapping array module, mapping number
Group counter module, storage read-write protection module, mapping status module, mapping control module, virtual address counting module, key
Logic module, accidentally address memory module, Mapping and Converting technology modules；
The input and output sorting module includes: bus data interactive module, inputoutput data interactive module, buffer tag
Module, data cached module, mapping data reception module, storage error checking module；
The program instruction memory module includes: Read-write Catrol initialization module, Read-write Catrol module；
The physical address drive module respectively with memory interactive module, buffer tag module, data cached module and reflect
Penetrate data reception module connection, the mapping array module respectively with memory interactive module, buffer tag module, caching number
It is connected according to module with mapping data reception module, the memory interactive module and rambus and preferential Read Controller plate
Card connection, the data cached module respectively with storage error checking module, bus data interactive module, inputoutput data
Interactive module connection, the mapping data reception module respectively with storage error checking module, bus data interactive module, defeated
Enter the connection of output data interactive module, the real-time clock module is counted with storage read-write protection module, virtual address respectively
Module, mapping control module, Mapping and Converting technology modules are connected with Read-write Catrol module.
As optimization, the memory board includes non-volatile FPGA module and SRAM module, and described is non-volatile
Property FPGA module include SRAM module for reading and writing and storage error checking and correction module.
As optimization, the SRAM module for reading and writing includes: storage control module, address latch module, at board address
Manage module, data transmit-receive module, block data transmit-receive module；
The storage error checking and correction module include: storage interactive module, verification block of state, correction module, synchronous
Module, correction verification module；
The data transmit-receive module and address latch module with caching board connect, the data transmit-receive module respectively with
Block data transmit-receive module is connected with correction verification module, and the address latch module is respectively and at storage control module and board address
Manage module connection, the block data transmit-receive module respectively with correction module, correction verification module, synchronization module and data transmit-receive module
Connection, the correction verification module are connect with synchronization module, correction module and verification block of state respectively, the verification state mould
Block is connect with storage interactive module, and the storage interactive module and the bus data interactive module in mapped cache board are mutual
Connection.
As optimization, the preferential reading Control card is constituted using non-volatile fpga chip, preferential to read control
The non-volatile fpga chip of board realizes the high speed interaction logic with block transmission control unit (TCU).
The beneficial effects of the present invention are: compared with prior art, it is of the invention by the nuclear power station of FPGA it is digital control based on
Calculation machine system core processing unit, for entire cpu system, PAL chip and logic chip are large number of, lead to board function
Consumption increases, and is changed to lower power consumption after non-volatile FPGA and SRAM framework, improves system reboot using non-volatile FPGA
Stability and reliability do not need to start from external storage reading program after restarting, reduce the probability of error, use is non-volatile
Property FPGA add the structure of SRAM compared to the board of PAL chip and logical device framework before, be more conducive on hardware and software
Maintenance, the advantage for having used FPGA to run parallel improve the speed of service of system.
Detailed description of the invention
Fig. 1 is functional framework total figure of the present invention；
Fig. 2 is processor board functional framework figure of the present invention；
Fig. 3 is processor board working principle diagram of the present invention；
Fig. 4 is mapped cache board functional framework figure of the present invention；
Fig. 5 is mapped cache board working principle diagram of the present invention；
Fig. 6 is memory board functional framework figure of the present invention；
Fig. 7 is memory board working principle diagram of the present invention.
Specific embodiment
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.The present invention being usually described and illustrated herein in the accompanying drawings is implemented
The component of example can be arranged and be designed with a variety of different configurations.Therefore, below to the reality of the invention provided in the accompanying drawings
The detailed description for applying example is not intended to limit the range of claimed invention, but is merely representative of selected implementation of the invention
Example.Based on the embodiments of the present invention, obtained by those of ordinary skill in the art without making creative efforts
Every other embodiment, shall fall within the protection scope of the present invention.
It should also be noted that similar label and letter indicate similar terms in following attached drawing, therefore, once a certain Xiang Yi
It is defined in a attached drawing, does not then need that it is further defined and explained in subsequent attached drawing.
In the description of the present invention, it should be noted that term " center ", "upper", "lower", "left", "right", "vertical",
The orientation or positional relationship of the instructions such as "horizontal", "inner", "outside" is to be based on the orientation or positional relationship shown in the drawings, or be somebody's turn to do
Invention product using when the orientation or positional relationship usually put, be merely for convenience of description of the present invention and simplification of the description, without
It is that the device of indication or suggestion meaning or element must have a particular orientation, be constructed and operated in a specific orientation, therefore not
It can be interpreted as limitation of the present invention.In addition, term " first ", " second ", " third " etc. are only used for distinguishing description, and cannot manage
Solution is indication or suggestion relative importance.
Embodiment as shown in Figure 1, the nuclear power station digital control computer system core processing unit based on FPGA, including place
Device board, mapped cache board, memory board and preferential Read Controller board are managed, the processor board and mapping are slow
It deposits and is connected by data/address bus with address bus between board, pass through friendship between the mapped cache board and memory board
Mutual bus is connected with storage bus, is connected between the memory board and preferential Read Controller board by storage bus
It connects, the processor board, mapped cache board and memory board are all made of the structure of non-volatile FPGA and SRAM cooperation
Frame is constituted, and the preferential reading Control card is constituted using non-volatile fpga chip.
By the processor board of core processing unit, mapped cache board, memory board and preferential Read Controller plate
The function of PAL chip and logical device carries out hardware description language programming using non-volatile FPGA and realizes that board uses on card
The framework of non-volatile FPGA and SRAM cooperation is realized using single non-volatile FPGA framework.
Embodiment as shown in Figures 2 and 3, the processor board include non-volatile FPGA module and SRAM module,
The non-volatile FPGA module includes command analysis module, data calculate and the control and friendship of memory module, virtual terminal
Mutual module, power-down rebooting module and initialization module.
The command analysis module includes: instruction cache module, microcommand decoder module, subsequence counter block, micro-
IA memory module, address jump module, storing data decoder module I, storing data decoder module II, dedicated decoding mould
Block；
The data calculate and memory module includes: that data calculate and logic processing module, program counter module, register
File storage module, accumulator module, flag register module, write make can control memory module, control memory module；
The control of the virtual terminal and interactive module include: terminal interaction module, serial bus module, BYTE MASK mould
Block, cache bus module, lteral data drive module.
The processor board of SSCI-890 core processing unit is completed using the framework that non-volatile FPGA and SRAM cooperates.
The non-volatile FPGA of processor board is responsible for completing instruction resolution logic, and data calculate and storage logic, with virtual terminal
Control and interaction logic, power-down rebooting, the functions such as initialization.Inside the processor board FPGA of SSCI-890 core processing unit
Realization principle figure such as Fig. 3, FPGA are respectively received and are passed by caching board bus by instruction cache module and caching bus module
Defeated next microcommand and data.The data that cache bus module receives enter data calculating and logic processing module counts
And logical operation, operation result feed back to accumulator module, flag register module, program counter module and register file
Memory module, while operational data is sent to by caching board bus by mathematical logic output module；The number of accumulator module
Data interaction is realized to microcommand decoder module and terminal interaction module, terminal interaction module and terminating machine according to output；Terminal is handed over
The POS data that mutual module receives is also fed to data calculating and logic processing module is counted and logical operation.
Microcommand is admitted to microcommand decoder module and is decoded, and the required microcommand executed is stored in control after decoding
In memory module processed；Next microinstruction address is transferred to microinstruction address memory module, micro- finger by subsequence counter module
Address memory module is enabled to send an instruction to address jump module；The instruction that receives of caching board and microcommand decoder module
Instruction, which is fed to write, makes can control the storage instructed in memory module, drives storing data decoder module I, storing data
Decoder module II and dedicated decoder module carry out the decoding that data are completed in work, and three tunnel decoding datas are then sent to text number
According to drive module, instruction is completed to the conversion of character and is sent to caching board bus.
Embodiment as shown in Figure 4 and Figure 5, the mapped cache board include non-volatile FPGA module and SRAM mould
Block, the non-volatile FPGA module include memory mapping block, real-time clock generation module, input and output sorting module,
Memory interactive module and program instruction memory module.
The memory mapping block includes: physical address drive module, mapping array module, mapping array counter mould
Block, storage read-write protection module, mapping status module, mapping control module, virtual address counting module, cipher key logic module,
Accidentally address memory module, Mapping and Converting technology modules；
The input and output sorting module includes: bus data interactive module, inputoutput data interactive module, buffer tag
Module, data cached module, mapping data reception module, storage error checking module；
The program instruction memory module includes: Read-write Catrol initialization module, Read-write Catrol module.
Mapped cache board is completed using the framework that non-volatile FPGA and SRAM cooperate, mapped cache board it is non-volatile
Property FPGA be responsible for completing mapping logic, real-time clock generates logic, memory mapping logic, input and output sequence logic, with storage
Functions, the memory such as device interaction logic and program instruction storage logic map realization principle figure such as Fig. 5 inside board FPGA, physics
Virtual address VA in mapping process is converted to physical address PA and is sent in memory interactive module by address drive module,
Memory interactive module sends memory address on rambus and preferential Read Controller board, while being intended to the number of write-in
According to the internal storage data being put on rambus and caching is read from rambus；Real-time clock module is microcommand program
Operation provides time clock feature；Bus data interactive module receives the data from processor board and generates cache bus data
CB, and it is sent to mapping data reception module, realize the control of memory mapping；Inputoutput data interactive module is in I/O timing
The lower logic control for realizing input and output of control.
Embodiment as shown in Figure 6 and Figure 7, the memory board include non-volatile FPGA module and SRAM module,
The non-volatile FPGA module includes SRAM module for reading and writing and storage error checking and correction module.
The SRAM module for reading and writing includes: storage control module, address latch module, board address processing module, number
According to transceiver module, block data transmit-receive module；
The storage error checking and correction module include: storage interactive module, verification block of state, correction module, synchronous
Module, correction verification module.
Memory board is completed using the framework that non-volatile FPGA and SRAM cooperate, memory board it is non-volatile
FPGA is responsible for completing to read and write logic to SRAM, stores the functions such as error checking and error correction logic, and the inside memory board FPGA is real
Existing schematic diagram such as Fig. 7, data transmit-receive module receives the address sent by caching board, while being stored in address latch module,
Storage control module processing receives the request of internal storage data transmission, and differentiates whether the request contains the address of request equipment, together
When initialization internal storage data transmission, and issue corresponding signal upon completion of the transmission；Memory board internal block data transmit-receive mould
Data in block are synchronized, are sent to storage interactive module after error correction, store the number of buses of interactive module and mapped cache board
Data interaction is carried out according to interactive module.
The preferential Control card that reads is completed using non-volatile fpga chip, to realize that memory board is set with Peripheral storage
High speed data transfer between standby controls data-transmission mode using preferential read.When peripheral storage device and peripheral block transmit
After board establishes connection, according to the number of control signal control peripheral block the transmission board and peripheral storage device of peripheral storage device
Control card is preferentially read according to transmission direction, and by control signal write-in, is started between memory board and peripheral storage device
Data exchange.
Above-mentioned specific embodiment is only specific case of the invention, and scope of patent protection of the invention includes but is not limited to
The product form and style of above-mentioned specific embodiment, any ordinary skill people for meeting the present invention and any technical field
The appropriate changes or modifications that member does it, all shall fall within the protection scope of the present invention.
Claims (8)
1. the nuclear power station digital control computer system core processing unit based on FPGA, it is characterised in that: including processor plate
Card, mapped cache board, memory board and preferential Read Controller board, the processor board and mapped cache board
Between connected with address bus by data/address bus, pass through interaction bus between the mapped cache board and memory board
It is connected with storage bus, it is described by storage bus connection between the memory board and preferential Read Controller board
Processor board, mapped cache board and memory board be all made of non-volatile FPGA and SRAM cooperation framework constitute,
The preferential reading Control card is constituted using non-volatile fpga chip.
2. the nuclear power station digital control computer system core processing unit according to claim 1 based on FPGA, special
Sign is: the processor board includes non-volatile FPGA module and SRAM module, the non-volatile FPGA module
Including command analysis module, data calculate and memory module, the control of virtual terminal and interactive module, power-down rebooting module and just
Beginningization module.
3. the nuclear power station digital control computer system core processing unit according to claim 2 based on FPGA, special
Sign is: the command analysis module includes: instruction cache module, microcommand decoder module, subsequence counter block, micro- finger
Enable address memory module, address jump module, storing data decoder module I, storing data decoder module II, dedicated decoding mould
Block；
The data calculate and memory module includes: that data calculate and logic processing module, program counter module, register
File storage module, accumulator module, flag register module, write make can control memory module, control memory module；
The control of the virtual terminal and interactive module include: terminal interaction module, serial bus module, BYTE MASK mould
Block, cache bus module, lteral data drive module；
The cache bus module and instruction cache module is connect with caching board bus, and the cache bus module passes through
BYTE MASK module and data calculate and logic processing module connect, the data calculating and logic processing module respectively with tire out
Device module, flag register module, program counter module is added to connect with register file memory module, the data calculate
Also pass through with logic processing module mathematical logic output module with caching board bus connect, the accumulator module respectively with
Terminal interaction module is connected with microcommand decoder module, and the terminal interaction module is also by BYTE MASK module and data meter
Calculation is connected with logic processing module；The microcommand decoder module respectively with control memory module and write and make can control storage mould
Block connection, the subsequence counter module are connect with microinstruction address memory module, and the microinstruction address stores mould
Block is connect with address jump module, and described writing makes to can control memory module and also connect with caching board bus, the storage
Data decoder module I, storing data decoder module II and dedicated decoder module are connect with lteral data drive module, described
Lteral data drive module is connect with caching board bus.
4. the nuclear power station digital control computer system core processing unit according to claim 1 based on FPGA, special
Sign is: the mapped cache board includes non-volatile FPGA module and SRAM module, the non-volatile FPGA mould
Block includes memory mapping block, real-time clock generation module, input and output sorting module, memory interactive module and program instruction
Memory module.
5. the nuclear power station digital control computer system core processing unit according to claim 4 based on FPGA, special
Sign is: the memory mapping block includes: physical address drive module, mapping array module, mapping array counter mould
Block, storage read-write protection module, mapping status module, mapping control module, virtual address counting module, cipher key logic module,
Accidentally address memory module, Mapping and Converting technology modules；
The input and output sorting module includes: bus data interactive module, inputoutput data interactive module, buffer tag
Module, data cached module, mapping data reception module, storage error checking module；
The program instruction memory module includes: Read-write Catrol initialization module, Read-write Catrol module；
The physical address drive module respectively with memory interactive module, buffer tag module, data cached module and reflect
Penetrate data reception module connection, the mapping array module respectively with memory interactive module, buffer tag module, caching number
It is connected according to module with mapping data reception module, the memory interactive module and rambus and preferential Read Controller plate
Card connection, the data cached module respectively with storage error checking module, bus data interactive module, inputoutput data
Interactive module connection, the mapping data reception module respectively with storage error checking module, bus data interactive module, defeated
Enter the connection of output data interactive module, the real-time clock module is counted with storage read-write protection module, virtual address respectively
Module, mapping control module, Mapping and Converting technology modules are connected with Read-write Catrol module.
6. the nuclear power station digital control computer system core processing unit according to claim 1 based on FPGA, special
Sign is: the memory board includes non-volatile FPGA module and SRAM module, the non-volatile FPGA module
Including SRAM module for reading and writing and storage error checking and correction module.
7. the nuclear power station digital control computer system core processing unit according to claim 6 based on FPGA, special
Sign is: the SRAM module for reading and writing includes: storage control module, address latch module, board address processing module, data
Transceiver module, block data transmit-receive module；
The storage error checking and correction module include: storage interactive module, verification block of state, correction module, synchronous
Module, correction verification module；
The data transmit-receive module and address latch module with caching board connect, the data transmit-receive module respectively with
Block data transmit-receive module is connected with correction verification module, and the address latch module is respectively and at storage control module and board address
Manage module connection, the block data transmit-receive module respectively with correction module, correction verification module, synchronization module and data transmit-receive module
Connection, the correction verification module are connect with synchronization module, correction module and verification block of state respectively, the verification state mould
Block is connect with storage interactive module, and the storage interactive module and the bus data interactive module in mapped cache board are mutual
Connection.
8. the nuclear power station digital control computer system core processing unit according to claim 1 based on FPGA, special
Sign is: the preferential reading Control card is constituted using non-volatile fpga chip, preferential to read the non-easy of Control card
The property lost fpga chip realizes the high speed interaction logic with block transmission control unit (TCU).
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