CN101546185A - Programmable multi-axis controller based on IEEE-1394 serial bus - Google Patents
Programmable multi-axis controller based on IEEE-1394 serial bus Download PDFInfo
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Abstract
The invention relates to a programmable multi-axis controller based on an IEEE-1394 serial bus in the technical field of numerical control. The programmable multi-axis controller comprises an IEEE-1394 serial communication interface module, a DSP module, an FPGA module, a differential motion reception module, a DA and operation amplification module, a photoelectric isolation module, a power supply and clock module and an auxiliary module, wherein the DSP module receives motion control information transmitted from the IEEE-1394 serial communication interface module and transmits a generated multi-axis motor pulse instruction to the FPGA module; and the FPGA module outputs the multi-axis motor pulse instruction to the DA and operation amplification module after the storage and frequency division treatment of the instruction so as to complete digital-analog conversion and operation amplification treatment and further control the operation of a multi-axis motor. The programmable multi-axis controller reduces the number of controller elements and the volume of an integrated circuit card, improves the flexibility and the expansibility of a system, and meets the requirements of the multi-axis real-time, high-speed and high-accuracy control in the technical field of numerical control.
Description
Technical field
What the present invention relates to is a kind of motion control card of fields of numeric control technique, specifically is a kind of multi-axis motion control card based on the IEEE-1394 universal serial bus.
Background technology
In fields of numeric control technique, motion control card is the core component that digitizing is made.Nowadays, the pattern of Fieldbus Based " PC+ motion control card " is widely adopted in medium-to-high grade digital control system, this pattern is fully with the high speed transmission abilities of fieldbus, the movement locus control ability of the open and motion control card of PC combines, it is strong to have information processing capability, the degree of opening height, TRAJECTORY CONTROL is accurate, the characteristics that versatility is good.Thereby have motion control of multiaxis synchronous coordination and complicated track planning, and real-time interpolation, the bus-type motion controller of servo filtering algorithm is being widely used and digitizing manufacturing field.
Find through retrieval the prior art document, China's application number is 200410017112.4, publication number is CN1564095A, and name is called the patent of " based on the multi-axis motion control card of RS-232 universal serial bus ", has provided a kind of motion control card by single-chip microcomputer and RS-232 bus.But in should inventing, resource-constrained on single-chip microcomputer computing and data-handling capacity and the sheet can not well satisfy the high-performance servo control algorithm, implement the requirement of interpolation to speed and resource use; RS-232 is the universal serial bus of low speed, can not well satisfy the requirement of high-grade numerical control field to speed, reliability and real-time.
Summary of the invention
The objective of the invention is to overcome deficiency of the prior art, a kind of multi-axis motion control card based on the IEEE-1394 universal serial bus is provided, its characteristic in conjunction with the IEEE-1394 bus is guaranteed in real time and synchronous communication, give full play to DSP (Digital Signal Processing, digital signal processing) high-speed computation ability is finished real-time interpolation, speed planning and the control of open and close ring, utilize the mechanism of FPGA (Field-Programmable GateArray, field programmable gate array) parallel processing to solve the integrated of complex logic circuit and reshuffle.
The present invention is achieved through the following technical solutions, the present invention includes: IEEE-1394 serial communication interface module, DSP module, the FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, power supply and clock module and supplementary module, wherein:
IEEE-1394 serial communication interface module receives the motion control information of PC by the IEEE-1394 bus, finishes functions such as the unpacking of data, verification, storage, control information is transferred to the DSP module to be for further processing again;
The DSP module receives the upper strata motion control information that IEEE-1394 serial communication interface module sends, and finishes data parsing and servocontrol, and the feedback information of handling is postbacked IEEE-1394 serial communication interface module; And multi-axle motor pulse command and the self-defined output signal that produces be transferred to the FPGA module.
The FPGA module receives the photoelectric encoder feedback signal that differential receiver module was handled on the one hand, carry out processing such as frequency multiplication, phase demodulation, gather the self-defined input signals such as Home (initial point) signal, limit switch of photoelectric isolation module output, and the feedback signal that will handle and self-defined input signal are transferred to the DSP module; Receive the multi-axle motor pulse command of DSP module on the other hand, storage, frequency division output to DA and computing amplification module after handling, and are transferred to photoelectric isolation module after the self-defined output signal processing with the output of DSP module;
Differential receiver module receives the photoelectric encoder differential wave of outside servo-driver module feedback, and the photoelectric encoder feedback signal of differential reception is transferred to the FPGA module; Differential receiver module is made up of the differential linear receiver chip of special use.
DA and computing amplification module receive the multi-axle motor pulse command that the FPGA module sends, and amplify the operation of the outside servo-driver module controls of rear drive motor through digital-to-analog conversion and computing;
Photoelectric isolation module is received from the definition input signal from outer input interface, is transferred to the FPGA module after photoelectricity is isolated, and outputs to outside output interface after the self-defined output signal isolation with the output of FPGA module;
The power supply signal that supplementary module receives power supply and clock module carries out the power supply detection, receives control signal wire and address wire from DSP module and FPGA module, and reset signal is transferred to DSP module and FPGA module;
Power supply and clock module provide stable voltage and power for IEEE-1394 serial communication interface module of the present invention, DSP module, FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, supplementary module, and unified system clock.Wherein, power supply comprises+12V ,-12V ,+5V ,+3.3V ,+1.8V and+1.2V; System clock provides clock reference for DSP module and FPGA module operate as normal, adopts the quartz crystal oscillator device of a 30MHz, and maximum provides the clock frequency of 150MHz.
Described IEEE-1394 serial communication interface module, specifically comprise: two-way IEEE-1394 bus interface and IEEE-1394 chip, wherein: two-way IEEE-1394 bus interface realizes half-duplex operation, article one, path receives the control command information of host computer, or forward command information is to next node, another path feedback motor information is given host computer, or the motor information of forwarding next stage node is to the upper level node; Described IEEE-1394 chip, be meant that the special use that meets the IEEE-1394 international standard connects chip, be responsible for communicating by the IEEE-1394 bus with host computer, finish the Physical layer and the data Layer agreement of IEEE-1394 bus protocol, and in module, realize at a high speed, real-time synchronous communications protocol, set the interrupt response pattern, set up configuration, monitor network mechanism, reliability of data transmission, synchronism and high speed in bonding node or the multinode communication;
Described DSP module is the servocontrol module, has rich data, resource on signal processing function and the sheet, specifically comprise: 1394 controller units, the servo controller unit, McBSP (Mutil-channelBuffered Serial Port, the multichannel buffer serial port) unit, AD unit and memory-mapped unit, wherein: 1394 controller units read the upper strata motion control information from IEEE-1394 serial communication interface module, through being transferred to the servo controller unit after the data decode, receive the feedback information after the servo controller cell processing on the other hand; The AD unit receives external analog signal to carry out outputing to the servo controller unit after the analog to digital conversion, and the memory-mapped unit reads the motion feedback information of FPGA module to servo control unit by memory-mapped mechanism; The servo controller unit receives the numerical information of the feedback information and the AD unit of the decoded motion control information of 1394 controller units, memory-mapped unit, finishes servo closed loop, and the motor pulses instruction that simultaneously closed loop is produced outputs to the McBSP unit; The McBSP unit receives the motor pulses instruction that servo control unit produces, and outputs to the FPGA module after treatment.
Described FPGA module is the hardware programmable processor module, have abundant circuit logic and parallel processing capability, specifically comprise: the memory-mapped unit, the hardware sampling unit, DA pretreatment unit and I/O (input and output) processing unit, wherein, the hardware sampling unit receives the self-defined input signal that photoelectric encoder signal that differential receiver module handled and I/O processing unit transmit, after carrying out processing such as frequency multiplication, phase demodulation, collection, output to the memory-mapped unit; The memory-mapped unit receives the feedback signal after the hardware sampling unit is handled, and feedback signal is transferred to the DSP module; The DA pretreatment unit receives the motor pulses instruction of memory-mapped unit, finish storage and preprocessing function after, motor pulses instructed output to DA and computing amplification module; The I/O processing unit is transferred to the hardware sampling unit after being received from the definition input signal, and the self-defined output signal that the memory-mapped unit transmits is transferred to the output interface of photoelectric isolation module.
Described DA and computing amplification module, specifically comprise: DA circuit and operational amplifier, wherein: by the DA circuit finish digital signal to the conversion of simulating signal-1V～+ 1V, by operational amplifier provide analog voltage range-10V that general servo-driver is fit to～+ 10V;
Described photoelectric isolation module is made up of the photoisolator chip, the motion control card that realization is invented and the Signal Spacing of external circuit and interface;
Described supplementary module realization system detects, and the internal memory expansion resets and artificial debugging, specifically comprise, and house dog and reset circuit unit, canned data unit and JTAG (Joint Test Action Group, joint test working group) unit, wherein:
House dog and reset circuit unit receive the power supply signal of power supply and clock module, be responsible for power supply and whether the clock module power work is normal by watchdog circuit, the reset signal of reset circuit unit outputs to the FPGA module when the system failure, DSP module and canned data unit, realization is to the DSP module, the zero clearing that resets of FPGA module and canned data unit;
The data line of canned data unit is realized in the canned data unit, address wire and control signal wire and DSP module and FPGA module interconnected, reception is from the control signal wire and the address wire of DSP module and FPGA module, judge that data message is write the canned data unit by data line still to be read, realization is to the program of DSP module and FPGA module, the expansion of data space, the system program that comprises FALSH storage DSP module, SRAM (Static Random Access Memory, static RAM) data message of storage DSP module, the system program of configuration ROM storage FPGA module, SDRAM (Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) as standby, the data acquisition information of storage FPGA module, and the internal memory zero clearing order that receives house dog and reset circuit unit;
The JTAG unit meets the IEEE1149.1 standard, be boundary scan interface, this scan interface links to each other with the debugging pin of DSP module and FPGA module respectively, by host computer and special-purpose developing software, realize the debugging of DSP module and FPGA module real-time online, artificial circuit, realize that PC is to modular unit internal register or spatial access and monitoring;
1394 controller units of described DSP module, cooperate servo controller unit and IEEE-1394 bus interface to set up the communication mechanism of the timing/Event triggered of motion control card, finish initial work, interrupt response mechanism and real time data access the IEEE-1394 chip;
The servo controller unit of described DSP module, the key of realization high speed, high-precision control is responsible for the motion control kernel program, realizes the high performance control to motor, specifically comprises real-time track interpolation, speed planning and the control of open and close ring;
Described memory-mapped unit is the mechanism of the information interaction of DSP module and FPGA module, design is based on the decoding scheme of address and control signal in FPGA module memory map unit, the DSP module realizes FPGA inside modules storage area according to the mapping mechanism of definition, the visit of register or buffer latch, fully with FPGA and DSP two big nucleus modules effective " isolation ", successfully realize the modular design thinking by described mechanism;
Described hardware sampling unit adopts the function of enriching logical circuit and hardware fast processing of FPGA, comprise: to high-speed sampling, frequency multiplication and the phase demodulation of code device signal, realize that sample frequency reaches nanosecond, finish captured in real time switching value signals such as machine origin, limit switches; SDRAM with expansion is used simultaneously, can finish the function of data collecting card;
Described I/O processing unit, comprise 28 road input signals and 28 tunnel output signals, be responsible for handling motor special signal, switching value signal or lathe I/O signal in the motion control, 56 path switching signals are realized by the design of FPGA internal logic circuit, the a large amount of uses of impact damper and latch in the custom circuit design have been saved, for isolating the signal coupling of integrated circuit board and external data, the interface of described I/O processing unit digital signal and outside is all by the photoelectric isolation module photoelectric coupler isolation;
When the present invention worked, host computer at first carried out being electrically connected of IEEE-1394 bus, configuration and communication time test, the quantity of bus node in the traversal communication network, and set up traversal list and read separately configuration info in order to the control integrated circuit board; During the operation of control motor, motion control information is electrically connected by IEEE-1394 serial communication interface module, receive the host computer order, bus communication protocol according to definition, command information stores the IEEE-1394 chip into, notify 1394 controller units by the mechanism that event interrupt triggers, 1394 controller units are finished synchronously according to other control cards on configuration info table information and the bus, be transported to the servo controller unit with movable information behind the step calibration, the servo controller unit calls the pulse control information that corresponding servocontrol module produces motor movement according to command information, the pulse steering order is carried out works of treatment such as multiaxis frequency division via the McBSP unit by using memory-mapped mechanism of DSP module with the pretreatment unit that steering order is transferred to the DA module of FPGA module, after the DA of FPGA module pretreatment unit was handled, the pulse steering order outputed to general servo-driver unit controls multi-axle motor operation through the digital-to-analogue conversion and the computing processing and amplifying of DA module again; Another path, the photoelectric encoder signal of the actual implementation status of reaction motor is finished sampling by differential receiver module feedback network to the hardware sampling unit, and carries out closed loop calibration by memory-mapped mechanism for the servo controller unit; Meanwhile 1394 controllers can be transferred to the IEEE-1394 bus interface module by bus communication protocol with the actual motion information of motor and upload to host computer and show in real time for user interface.By in the said process as seen, among the present invention the division of labor of each module clear and definite, collaborative work has demonstrated fully the thinking of modular design.
The present invention has following beneficial effect compared with prior art:
(1), the present invention adopts the transmission ature of coal of high-speed bus IEEE-1394 as host computer and motion control card, reached the characteristic of high-speed real-time transmission, and the constraint by bus protocol, reach the synchro control of do more physical exercises control panel or multi-axle motor, more reliable, more real-time than RS232-bus transfer, more can meet the requirement of high-grade numerical control;
(2), the present invention adopts DSP as signal processing chip, have resource and faster data calculation process ability on the abundanter sheet than traditional single-chip microcomputer, and AD module that inside is integrated and the Electric Machine Control interface that enriches, greatly reduced the expanded circuit module, compare with traditional single-chip microcomputer, DSP of the present invention has the JTAG function of in-circuit emulation and debugging, and has the potential with the supporting hardware-in-loop simulation of MATLAB/Simulink;
(3), the present invention adopts field programmable gate array FPGA technology, can realize the hardware online programming and reshuffle function, increased the convenience of system debug, more flexible than traditional special integrated chip, dwindled volume, be easier to debugging and in-circuit emulation than CPLD circuit, but increased the performance of modular design and online reconfiguration, increased the paces of the updating and upgrading of a product;
(4), the present invention makes full use of IEEE1394 bus, DSP and FPGA advantage and characteristics separately, adopt modularization, open by design thinking, with each module as System Design independently, can be with various microprocessors or PC interface, as long as the communication mechanism that adopts the present invention to set is beneficial to the performance and the upgrading that improve integrated circuit board, greatly shortened product development cycle, reduce cost, reduced power consumption.
Description of drawings
Fig. 1 is a system architecture diagram of the present invention;
Fig. 2 is the structure schematic flow sheet of DA among the present invention and computing amplification module;
Fig. 3 is the structure schematic flow sheet of hardware sampling unit in the FPGA module among the present invention;
Fig. 4 is the structure schematic flow sheet of I/O processing of circuit unit in the FPGA module among the present invention;
Fig. 5 is motion control schematic flow sheet among the present invention.
Embodiment
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is to be that prerequisite is implemented with technical scheme of the present invention; below provided detailed embodiment and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 1, present embodiment comprises with lower module: IEEE-1394 serial communication interface module, and the DSP module, the FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, power supply and clock module, and supplementary module, wherein:
IEEE-1394 serial communication interface module provides the hardware interface circuit of the bus of communicating by letter with host computer, realize PC and remote connection of controlling between integrated circuit board and control panel, IEEE-1394 serial communication interface module receives the motion control information of PC on the one hand by the IEEE-1394 bus, finish data storage, unpack, function such as verification, again control information is transferred to the DSP module and is for further processing, perhaps by transmitting the IEEE-1394 serial communication interface module that motion control information is forwarded to next node of cascade by 1394 buses; Receive the motion feedback information of DSP module on the other hand, finish packing data, transmission, confirm functions such as bag reception, perhaps receive the motion feedback information of the IEEE-1394 serial communication interface module transmission of next node, with motion feedback information via the IEEE-1394 bus transfer to PC, thereby realize PC with control between integrated circuit board and control panel long-distance transmissions be connected;
The DSP module receives the upper strata motion control information that IEEE-1394 serial communication interface module sends on the one hand, finishes data parsing and servocontrol, and the feedback information of handling is postbacked IEEE-1394 serial communication interface module; Receive simultaneously and finish servo closed-loop control after handling from the feedback information of FPGA module, produce motor pulses and instruct the FPGA module,
The FPGA module receives differential receiver module on the one hand and handled the photoelectric encoder feedback signal, carry out processing such as frequency multiplication, phase demodulation, and gather the self-defined input signals such as Home (initial point) signal, limit switch of photoelectric isolation module output, and the feedback signal and the self-defined input signal of sampling is transferred to the DSP module; Receive the multi-axle motor pulse command of DSP module on the other hand, storage, frequency division output to DA and computing amplification module after handling, and pass through the self-defined output signal that the memory-mapped unit receives the DSP module, are transferred to photoelectric isolation module after the processing;
Differential receiver module receives the photoelectric encoder differential wave of outside servo-driver module feedback, and the photoelectric encoder signal that will handle is transferred to the hardware sampling unit of FPGA module;
DA and computing amplification module receive the pretreated multi-axle motor pulse control command of FPGA module, the analog voltage range that provides outside general servo-driver module to be fit to;
Photoelectric isolation module receives the self-defined input signal of outer input interface, and photoelectricity is transferred to the FPGA module after isolating, and outputs to outside output interface after the self-defined output signal isolation with the output of FPGA module;
The power supply signal that supplementary module receives power supply and clock module carries out the power supply detection, receives control signal wire and address wire from DSP module and FPGA module, and reset signal is transferred to DSP module and FPGA module;
Power supply and clock module provide stable voltage and power for IEEE-1394 serial communication interface module of the present invention, DSP module, FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, supplementary module, and unified system clock.Wherein, power supply comprises+12V ,-12V ,+5V ,+3.3V ,+1.8V and+1.2V; System clock provides clock reference for DSP module and FPGA module operate as normal, adopts the quartz crystal oscillator device of a 30MHz, and maximum provides the clock frequency of 150MHz.
Described IEEE-1394 serial communication interface module, specifically comprise: two-way IEEE-1394 bus interface and IEEE-1394 chip, wherein: two-way IEEE-1394 bus interface realizes half-duplex operation, article one, path receives the control command information of host computer, or forward command information is to next node, another path feedback motor information is given host computer, or the motor information of forwarding next stage node is to the upper level node; Described IEEE-1394 chip, be meant that the special use that meets the IEEE-1394 international standard connects chip, be responsible for communicating by the IEEE-1394 bus with host computer, finish the Physical layer and the data Layer agreement of IEEE-1394 bus protocol, and in module, realize at a high speed, real-time synchronous communications protocol, set the interrupt response pattern, set up configuration, monitor network mechanism, reliability of data transmission, synchronism and high speed in bonding node or the multinode communication;
Described DSP module is the servocontrol module, has rich data, resource on signal processing function and the sheet, specifically comprise: 1394 controller units, the servo controller unit, McBSP (Mutil-channelBuffered Serial Port, the multichannel buffer serial port) unit, AD unit and memory-mapped unit, wherein: 1394 controller units read the upper strata motion control information from IEEE-1394 serial communication interface module, be input to the servo controller unit through after the data decode, read the feedback information of servo controller cell processing on the other hand, transmission of feedback information is arrived IEEE-1394 serial communication interface module; The servo controller unit receives the numerical information of the feedback information and the AD unit of the decoded motion control information of 1394 controller units, memory-mapped unit, finishes servo closed loop, and the motor pulses instruction that simultaneously closed loop is produced outputs to the McBSP unit; The McBSP unit receives the motor pulses instruction that servo control unit produces, output to the FPGA module after treatment, the AD unit receives external analog signal to carry out outputing to servo control unit after the analog to digital conversion, and the memory-mapped unit reads the motion feedback information of FPGA module to servo control unit by memory-mapped mechanism;
Described FPGA module is the hardware programmable processor module, have abundant circuit logic and parallel processing capability, specifically comprise: the memory-mapped unit, the hardware sampling unit, DA pretreatment unit and I/O (input and output) processing unit, wherein, the memory-mapped unit receives the feedback signal after the hardware sampling unit is handled, and feedback signal is transferred to the DSP module; The hardware sampling unit receives the supplied with digital signal of photoelectric encoder signal and I/O processing unit, carry out frequency multiplication, phase demodulation, acquisition process after, output to the memory-mapped unit; The DA pretreatment unit receives the motor pulses instruction of memory-mapped unit, finish storage and preprocessing function after, motor pulses instructed output to DA and computing amplification module; The I/O processing unit is transferred to the hardware sampling unit after being received from the definition input signal, and receives the self-defined output signal of memory-mapped unit, is transferred to output interface by photoelectric isolation module;
Described DA and computing amplification module, specifically comprise: DA circuit and operational amplifier, wherein: by the DA circuit finish digital signal to the conversion of simulating signal-1V～+ 1V, by operational amplifier provide analog voltage range-10V that general servo-driver is fit to～+ 10V;
Described supplementary module realization system detects, and the internal memory expansion resets and artificial debugging, specifically comprise, and house dog and reset circuit unit, canned data unit and JTAG (Joint Test Action Group, joint test working group) unit, wherein:
House dog and reset circuit unit are responsible for power supply and whether the clock module power work is normal, realizes to the DSP module zero clearing that resets of FPGA module and canned data unit when the system failure by reset circuit;
The canned data unit is realized the program of DSP module and FPGA module, the expansion of data space, the system program that comprises FALSH storage DSP module, SRAM (Static Random Access Memory, static RAM) data message of storage DSP module, the system program of configuration ROM storage FPGA module, SDRAM (Dynamic Random Access Memory, Synchronous Dynamic Random Access Memory) as standby, the data acquisition information of storage FPGA module, and the internal memory zero clearing order that receives house dog and reset circuit unit;
The JTAG unit meets the IEEE1149.1 standard, for DSP module and FPGA module realize real-time online debugging, artificial circuit, realizes that PC is to modular unit internal register or spatial access and monitoring;
The IEEE-1394 serial communication interface module of present embodiment adopts the TSB43 family chip of Texas Instruments company, be responsible for to realize the Physical layer and the link layer protocol of IEEE1394 bus, realize that motion control card is connected with bus between host computer or the integrated circuit board and function such as bus detection configuration;
The DSP module of present embodiment adopts the TMS320F2812 chip of Texas Instruments company, be responsible for the initialization of 1394-chip and control in real time, to the visit of FPGA module with communicate by letter, finish the trajectory planning of motion control, implement functions such as interpolation and position closed loop; The system program of the FLASH storer operation DSP module that chip carries; The high-speed AD unit sampling simulating signal of built-in chip type is carried out analog to digital conversion; The SRAM-IS61LV51216 of expansion is as the data storage area of DSP module operation;
The EP2C35 chip of the FPGA module samples altera corp of present embodiment, be responsible for the Logic Circuit Design of integrated circuit board, comprise: with mutual memory-mapped mechanism and the decoding scheme of DSP module, to the multiaxis pulse control signal of DA and the transmission of computing amplification module, and to the high-speed sampling circuit of differential reception photoelectric encoder signal and the store circuit of I/O signal; The series arrangement chip EPCS16 of expansion is as the program's memory space of FPGA module; The SDRAM-K4S641632 of expansion is as the storage space of standby " data collecting card ";
As shown in Figure 2, described DA has been connected the FPGA module and the DSP module of motion control card with the computing amplification module, the McBSP unit of DSP module produces frequency division and the pre-service of the multiaxis pulse control information of serial through the DA of FPGA module pretreatment unit, the information of multiaxis is produced the aanalogvoltage of 1.5V～3.5V through the DA circuit, through the relatively generation-1V of 2.5V reference voltage～+ aanalogvoltage of 1V, amplify producing the multi-axes simulation steering order by operational amplifier again, promptly general servo driving is required-10V～+ analog quantity of 10V.
As shown in Figure 3, the hardware sampling unit receives the photoelectric encoder differential wave of handling through differential receiver module in the described FPGA module, finished high speed acquisition, process of frequency multiplication and the phase demodulation tally function of the photoelectric encoder signal of multiaxis, and the signal after will handling outputs to the memory-mapped unit.Counting clock employing and the 150MHz of the unified clock benchmark generation of system or the frequency of 75MHz, clock control cell by the FPGA inside modules is counted sampling, high-speed sampling design by hardware sampling unit circuit can realize the nanosecond sampling frequency multiplication to the photoelectric encoder signal, produce the Index signal, realize accurate position closed loop or speed ring for servo control unit; The Home+Index capture circuit has been realized the high-speed capture to the Home+Index signal of initial point signal, cooperate the servo controller unit that motor is accurately located, the photoelectric coding signal that this circuit receives is to handle through the 26LS32 chip in the differential receiver module to obtain, and the Home signal is caught by described I/O processing unit and obtained;
As shown in Figure 4, I/O processing unit in the described FPGA module, comprised servo enabling, pulse output, report to the police and export, just changeing counter-rotating, the initial point signal, limit switch, general input, totally 56 road input amount signals such as general output etc., the input and output buffering, latch cicuit uses the gate circuit of FPGA inside, d type flip flop and three-state buffer are realized buffering or the latch operation to 56 road signals, avoid using special chip, the integration and the extendability of integrated circuit board have been increased, for realizing disturbing with the electrical equipment of outside servo-driver module and input interface and output interface, all input/output signals are all by the photoelectric isolation module isolation processing, wherein: the employed photoelectrical coupler of described photoelectric isolation module is the TLP521 chip, described outside servo-driver module and input interface, output interface is not a content of the present invention for the concrete function of describing embodiment adds;
As shown in Figure 5, in present embodiment when work,, host computer at first carries out being electrically connected of IEEE-1394 bus, configuration and communication time test, the quantity of bus node in the traversal communication network, and set up traversal list and read separately configuration info in order to the control integrated circuit board; During the operation of control motor, motion control information is electrically connected by IEEE-1394 serial communication interface module, receive the host computer order, bus communication protocol according to definition, command information stores the IEEE-1394 chip into, notify 1394 controller units by the mechanism that event interrupt triggers, 1394 controller units are finished synchronously according to other control cards on configuration info table information and the bus, be transported to the servo controller unit with movable information behind the step calibration, the servo controller unit calls the pulse control information that corresponding High Performance Motion Control algorithm produces motor movement according to command information, the Electric Machine Control pulse command utilizes memory-mapped mechanism via the McBSP unit of DSP module the DA pretreatment unit that control information is transferred to the FPGA module to be carried out pre-service work such as multiaxis frequency division, after the DA of FPGA module pretreatment unit was handled, the pulse steering order outputed to general outside servo-driver module controls multi-axle motor operation by the digital-to-analogue conversion and the computing processing and amplifying of DA and computing amplification module again; Another path, the actual implementation status of motor are finished sampling for the hardware sampling unit after by outside servo-driver module feedback signal being transferred to differential receiver module, and are transferred to servo controller unit execution closed loop calibration by the memory-mapped unit; Meanwhile 1394 controllers can be transferred to IEEE-1394 serial communication interface module by bus communication protocol with the motor actual motion information of feedback and upload to host computer and show in real time for user interface.
Present embodiment has following beneficial effect:
(1), present embodiment adopts the transmission ature of coal of high-speed bus IEEE-1394 as host computer and motion control card, reached the characteristic of high-speed real-time transmission, and the constraint by bus protocol, reach the synchro control of do more physical exercises control panel or multi-axle motor, more can meet the requirement of high-grade numerical control than RS232-bus.
(2), present embodiment adopts DSP as signal processing chip, have resource and faster data calculation process ability on the abundanter sheet than traditional single-chip microcomputer, and AD module that inside is integrated and the Electric Machine Control interface that enriches have greatly reduced the expanded circuit module.Compare with traditional single-chip microcomputer, the DSP of present embodiment has the JTAG function of in-circuit emulation and debugging, has the potential with the supporting hardware-in-loop simulation of MATLAB/Simulink.
(3), present embodiment adopts field programmable gate array FPGA technology, can realize hardware online programming and online reconfiguration function, increased the convenience of system debug, more flexible than traditional special integrated chip, dwindled volume, be easier to debugging and emulation, but increased the performance of modular design and online reconfiguration than CPLD circuit, increased the paces of the updating and upgrading of a product, the FPGA module also can be used as the data collecting card use simultaneously.
(4), present embodiment makes full use of IEEE-1394 bus, DSP and FPGA advantage and characteristics separately, adopt modularization, open by design thinking, with each module as System Design independently, can be with various microprocessors or PC interface, as long as the communication mechanism that adopts the present invention to set is beneficial to the performance and the upgrading that improve integrated circuit board, greatly shortened product development cycle, reduce cost, reduced power consumption.
(5), present embodiment adopts position or speed closed loop control to the type of drive of servo-driver, adopts the hardware sampling unit of FPGA can realize the nanosecond sampling of code device signal, can control the control accuracy height simultaneously to the position and the speed of motion.
Claims (8)
1, a kind of multi-axis motion control card based on the IEEE-1394 universal serial bus is characterized in that, comprises IEEE-1394 serial communication interface module, the DSP module, the FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, power supply and clock module and supplementary module, wherein:
IEEE-1394 serial communication interface module receives the motion control information of PC by the IEEE-1394 bus, carry out the unpacking of data, verification, storage after, motion control information is transferred to the DSP module;
The DSP module receives the motion control information that IEEE-1394 serial communication interface module transmits, and carries out data parsing and servocontrol, and the feedback information of handling is postbacked IEEE-1394 serial communication interface module; And multi-axle motor pulse command and the self-defined output signal that produces be transferred to the FPGA module;
The FPGA module receives the photoelectric encoder feedback signal that differential receiver module was handled on the one hand, gathers the self-defined input signal of photoelectric isolation module output, and the photoelectric encoder feedback signal that will handle and self-defined input signal are transferred to the DSP module; Receive the multi-axle motor pulse command of DSP module on the other hand, storage, frequency division output to DA and computing amplification module after handling, and are transferred to photoelectric isolation module after the self-defined output signal processing with the output of DSP module;
Differential receiver module receives the photoelectric encoder differential wave of outside servo-driver module feedback, and the photoelectric encoder feedback signal of differential reception is transferred to the FPGA module;
DA and computing amplification module receive the multi-axle motor pulse command that the FPGA module transmits, and amplify the operation of the outside servo-driver module controls of rear drive motor through digital-to-analog conversion and computing;
Photoelectric isolation module is received from the definition input signal from outer input interface, is transferred to the FPGA module after photoelectricity is isolated, and outputs to outside output interface after the self-defined output signal isolation with the output of FPGA module;
The power supply signal that supplementary module receives power supply and clock module carries out the power supply detection, receives control signal wire and address wire from DSP module and FPGA module, and reset signal is transferred to DSP module and FPGA module;
Power supply and clock module provide stable voltage and power for IEEE-1394 serial communication interface module of the present invention, DSP module, FPGA module, differential receiver module, DA and computing amplification module, photoelectric isolation module, supplementary module, and unified system clock.
2, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 1, it is characterized in that, described IEEE-1394 serial communication interface module, comprise two-way IEEE-1394 bus interface and IEEE-1394 chip, wherein: two-way IEEE-1394 bus interface realizes half-duplex operation, article one, path receives the control command information of host computer, or forward command information is to next node, another path feedback motor information is given host computer, or the motor information of forwarding next stage node is to the upper level node; IEEE-1394 chip and host computer communicate by the IEEE-1394 bus.
3, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 1 is characterized in that, described DSP module comprises 1394 controller units, the servo controller unit, and the McBSP unit, AD unit and memory-mapped unit, wherein:
1394 control modules will be transferred to the servo controller unit from the upper strata motion control information of IEEE-1394 serial communication interface module, and receive the feedback information of servo controller unit;
The AD unit receives external analog signal, and simulating signal is carried out outputing to the servo controller unit after the analog to digital conversion;
The memory-mapped unit reads the motion feedback information of FPGA module, and the motion feedback information transmission is arrived the servo controller unit;
The servo controller unit receives the motion control information of 1394 control modules, the feedback information of memory-mapped unit and the numerical information of AD unit, and the motor pulses instruction that produces is transferred to the McBSP unit;
The McBSP unit is transferred to the FPGA module with the motor pulses instruction of the servo controller unit of reception.
4, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 1 is characterized in that, described FPGA module comprises the memory-mapped unit, the hardware sampling unit, and DA pretreatment unit and I/O processing unit, wherein:
The hardware sampling unit receives the self-defined input signal that photoelectric encoder signal that differential receiver module handled and I/O processing unit transmit, carry out frequency multiplication, phase demodulation, acquisition process after, output to the memory-mapped unit;
The memory-mapped unit receives the feedback signal after the hardware sampling unit is handled, and feedback signal is transferred to the DSP module;
The DA pretreatment unit receives the motor pulses instruction of memory-mapped unit, after storage and the pre-service, the motor pulses instruction is outputed to DA and computing amplification module;
The I/O processing unit is received from the definition input signal, and the self-defined output signal that the memory-mapped unit transmits is transferred to the output interface of photoelectric isolation module.
5, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 1, it is characterized in that, described DA and computing amplification module, comprise DA circuit and operational amplifier, wherein: the DA circuit is converted to simulating signal with digital signal, the analog voltage range that operational amplifier provides general servo-driver to be fit to.
6, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 1 is characterized in that, described supplementary module comprises house dog and reset circuit unit, canned data unit and JTAG unit, wherein:
House dog and reset circuit unit receive the power supply signal of power supply and clock module, reset signal are outputed to the FPGA module, DSP module and canned data unit;
The canned data unit receives control signal wire and the address wire from DSP module and FPGA module, judges that data message is write the canned data unit by data line still to be read;
The JTAG unit is connected with the debugging pin of DSP module and FPGA module respectively.
7, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 3, it is characterized in that, described 1394 controller units, cooperate servo controller unit and IEEE-1394 bus interface to set up the communication mechanism of the timing/Event triggered of motion control card, finish initial work, interrupt response mechanism and real time data access the IEEE-1394 chip.
8, the multi-axis motion control card based on the IEEE-1394 universal serial bus according to claim 4, it is characterized in that, described hardware sampling unit carries out high-speed sampling, frequency multiplication and phase discrimination processing to code device signal, and machine origin, limit switch switching value signal are carried out captured in real time; SDRAM with expansion is used simultaneously, finishes the function of data collecting card.
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| CN117348501A (en) * | 2023-12-05 | 2024-01-05 | 深圳市大族封测科技股份有限公司 | Linkage control method and linkage control system for multiple motion control cards |
| CN117348501B (en) * | 2023-12-05 | 2024-02-13 | 深圳市大族封测科技股份有限公司 | Linkage control method and linkage control system for multiple motion control cards |
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