CN107203177A - A kind of multi-shaft motion control system based on FPGA - Google Patents
A kind of multi-shaft motion control system based on FPGA Download PDFInfo
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- CN107203177A CN107203177A CN201710460075.1A CN201710460075A CN107203177A CN 107203177 A CN107203177 A CN 107203177A CN 201710460075 A CN201710460075 A CN 201710460075A CN 107203177 A CN107203177 A CN 107203177A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/05—Programmable logic controllers, e.g. simulating logic interconnections of signals according to ladder diagrams or function charts
- G05B19/054—Input/output
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/10—Plc systems
- G05B2219/11—Plc I-O input output
- G05B2219/1103—Special, intelligent I-O processor, also plc can only access via processor
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Abstract
The present invention relates to movement control technology field, a kind of multi-shaft motion control system based on FPGA, including power supply, crystal oscillator, jtag circuit, ARM chips, fpga chip, 15 road DI input circuits, 8 road HDI input circuits and 16 road HDO output circuits.The present invention uses ARM chips as the controller of motion control, and fpga chip not only meets higher demand for control as the data processor of motion control, and possesses that precision is higher, speed data-handling capacity.The controller of existing market presence is solved, processing speed is slow, and precision is not high, and not reproducible programming, autgmentability is poor, and the bad shortcoming of versatility has the advantages that opening, interchangeability, scalability and portability.
Description
Technical field
The present invention relates to a kind of multi-shaft motion control system based on FPGA, belong to movement control technology field.
Background technology
Movement control technology be to the parameters such as position, the speed of mechanical moving element carry out real-time control management, make its by
The technology moved according to predetermined movement locus and kinematic parameter.Mainly by the control to motor driver to reach pair
The position of mechanical movement, speed, the accurate control of acceleration, motion controller with its accurately TRAJECTORY CONTROL ability make its boat
My god, lathe, robot, military be widely applied.The driver of usual servomotor and stepper motor uses bus marco
Or pulse and direction controlling.Bus-type motion controller output signal is instruction and parameter, and uses pulse and the control in direction
Mode processed, the position of the quantity correspondence motion control of pulse, the speed of pulse frequency correspondence motion control, control accuracy is high, spirit
It is active strong.In recent years, multi-axle motor synchronous control technique is used widely in high-speed, high precision Machinery Control System, control
Precision and synchronous sex chromosome mosaicism are prevalent in control system.Problem above is the core for solving high-precision multi-axial Simultaneous motion control
The heart, is also the trend of motion control development.
FPGA (field programmable gate array) obtains extensive with its higher precision and faster speed in motion control
Using.Intrinsic FPGA flexibility, concurrency, integration cause it increasingly to be paid attention to, and FPGA can be with integrated various logical in addition
Communication interface, it is adaptable to various communication protocols.With the raising of production technology, FPGA scale constantly expands, and cost progressively drops
Low, user can realize various logic circuit in the FPGA of monolithic.Come using FPGA as the core processor of motion control
Realize that high-precision multi-axial Simultaneous motion controller already turns into the main trend of numerical control field.
The controller that existing market is present, processing speed is slow, and precision is not high, and not reproducible programming, autgmentability is poor, versatility
Bad the shortcomings of.
The content of the invention
In order to overcome the deficiencies in the prior art, the present invention provides a kind of Multi-axis motion control system based on FPGA
System, the purpose is to：(1) present invention can be moved by exporting up to 8 motor shafts of Pulse Width Control, and circuit design not only can be right
Many motors can also be synchronized control by each single motor independent control, improve linkage precision.(2) circuit design uses ARM
Movement control technology, is combined, designed by the scheme combined with FPGA using the advantage of PLC with PLC control technology
The motion controller that a control accuracy is high, speed is fast, programming is convenient, versatility is good, inexpensive.(3) by motion control function
It is integrated into the FPGA, according to live functional requirement, overprogram can be carried out to FPGA, without changing other hardware
Or software merit rating, construction cycle shortening, reduce the cost of motion controller.(4) using the abundant I/O resource in FPGA peripheries, make
For the extension I/O port of the input and output of motion controller module, control of the motion controller to digital quantity signal is greatly added
Ability.(5) FPGA data interaction is controlled using ARM FSMC, wherein being managed FPGA as SRAM, interface module exists
FPGA indoor designs, the real-time of the data interaction not only improved also saves solution interface resource and used.(6) it is real in FPGA bottoms
The substantial amounts of data processing of existing motion control, realizes the output of all types of pulses, to reach the control to all kinds of servomotors so that
Described motion control design is applied to arbitrary industry spot, has broken special monopolization, has reduced development cost.(7) may be used
Handled with carrying out interrupt processing, frequency measurement counting to external signal, and common digital signal input up to 15 tunnels, high-speed digital signal
Up to 8 tunnels are inputted, complete to detect the feedback of whole fortune work(control system, it is ensured that the high accuracy of kinetic control system and stably
Property.
In order to realize foregoing invention purpose, solving oneself has problem present in technology, and the present invention is adopted the technical scheme that：
A kind of multi-shaft motion control system based on FPGA, including power supply, crystal oscillator, jtag circuit, ARM chips, fpga chip, 15 road DI
Input circuit, 8 road HDI input circuits and 16 road HDO output circuits, 15 described road DI input circuits and 8 road HDI input electricity
Road, the limiting filter circuit and optical coupling isolation circuit being sequentially connected respectively including input protection circuit and with it, the 16 road HDO
Output circuit, including output protection circuit and the output driving circuit and optical coupling isolation circuit that are sequentially connected with it, the optocoupler
Isolation circuit, the interference for avoiding the external world, wherein 15 road DI input circuits are isolated using common optical coupler, 8 road HDI input circuits
Isolated with 16 road HDO output circuits using high speed photo coupling, limiting filter circuit, for avoiding the burr of signal from disturbing, the light
Coupling isolation circuit is connected with fpga chip respectively, for the processing of motion control signal, the jtag circuit respectively with FPGA cores
Piece and ARM chips are connected, and jtag circuit is used for director demon and downloads and debug, and ARM chips carry out the fortune of motion control data
Calculate and configure, communicated by FSMC communication interfaces with fpga chip, corresponding function is performed in fpga chip built-in system, it is described
Power supply is connected with crystal oscillator, ARM chips and fpga chip respectively, and crystal oscillator is also connected with fpga chip, and clock is provided for fpga chip,
Clock is subjected to scaling down processing inside FPGA, is respectively outside ARM chips and Ethernet offer clock；The fpga chip
Including clock module, communication interface modules, interrupt module, counting frequency measurement module, data buffer storage control module, PLS modules, pulse
Output module, signal output selecting module, enable bit control module, enable bit selecting module and DI filtering process module and HDI
Filtering process module, wherein, communication interface modules is connected with data buffer storage control module, and communication interface modules is used for ARM chips
With the data interaction of fpga chip, data buffer storage control module is used for data buffer storage, and by corresponding data configuration to each height
Module port, performs corresponding function, DI filtering process module and HDI the filtering process module respectively by interrupt module with
Data buffer storage control module is connected, at by 15 road DI signals, 8 road HDI signals by DI filtering process module and HDI filtering
Manage the 15 road DI signals obtained after module is filtered again, 8 road HDI signals and interrupted by the 15 road DI obtained after interrupt module and believed
Number, 8 road HDI interrupt signals be directly output to ARM chips, obtained interrupting channel value be respectively sent to data buffer storage control mould
Block, the HDI filtering process module is also connected by counting frequency measurement module with data buffer storage control module, for 8 road HDI to be believed
The 8 road HDI signals obtained after number being filtered again by HDI filtering process modules carry out frequency measurement counting by counting frequency measurement module,
And data buffer storage control module is sent in real time by frequency measurement data are counted；The DI filtering process module and HDI filtering process moulds
Block is joined directly together with data buffer storage control module respectively, when not interrupting, and filtered signal is directly output to data buffer storage
Control module；The data buffer storage control module by enable bit control module, enable bit selecting module, pulse output module with
Signal output selecting module is sequentially connected, wherein, the enable bit selecting module is selected pulse output module, by arteries and veins
Rush output module and be tied to fixed enable bit, then by configuring enable bit control module, enable signal and selected by enable bit
Select module to enable selected pulse output module, by enable bit selecting module and enable bit control module combining makes
With the synchronous interaction for realizing independent controlled motor axle and many motor shafts；The pulse output module, it is slow as data using FIFO
Mechanism is deposited, while being controlled to 8 motor shaft motions；The signal output selecting module passes through PLS modules and data buffer storage
Control module is connected, and the road HDO signal output ports of signal output selecting module Hai Yu 16 are connected.
Present invention has the advantages that：A kind of multi-shaft motion control system based on FPGA, including power supply, crystal oscillator, JTAG electricity
Road, ARM chips, fpga chip, 15 road DI input circuits, 8 road HDI input circuits and 16 road HDO output circuits, 15 described tunnels
DI input circuits and 8 road HDI input circuits, the limiting filter circuit being sequentially connected respectively including input protection circuit and with it and
Optical coupling isolation circuit, the 16 road HDO output circuits, including output protection circuit and the output driving circuit being sequentially connected with it
And optical coupling isolation circuit, the optical coupling isolation circuit is connected with fpga chip respectively, for the processing of motion control signal, JTAG
Circuit is connected with fpga chip and ARM chips respectively, and jtag circuit is used for director demon and downloads and debug, and ARM chips are carried out
The computing and configuration of motion control data, are communicated by FSMC communication interfaces with fpga chip, are held in fpga chip built-in system
The corresponding function of row, the power supply is connected with crystal oscillator, ARM chips and fpga chip respectively, and crystal oscillator is also connected with fpga chip, is
Fpga chip provides clock.Compared with the prior art, the present invention uses ARM chips as the controller of motion control, FPGA cores
Piece not only meets higher demand for control as the data processor of motion control, and possesses that precision is higher, speed
Data-handling capacity.The controller of existing market presence is solved, processing speed is slow, and precision is not high, not reproducible programming, expands
Malleability is poor, the bad shortcoming of versatility, has the advantages that opening, interchangeability, scalability and portability.
Brief description of the drawings
Fig. 1 is principle of the invention block diagram.
Fig. 2 is the fpga chip theory diagram in the present invention.
Fig. 3 is the pulse output flow chart of the pulse output module in fpga chip.
Fig. 4 is the direction output flow chart of the pulse output module in fpga chip.
Fig. 5 is enable bit control module and enable bit selecting module associated working schematic diagram in fpga chip.
Fig. 6 is the pulse output flow chart of the PLS modules in fpga chip.
Fig. 7 is the high-speed counting flow chart for counting frequency measurement module in fpga chip.
Fig. 8 is the high-speed frequency measurement flow chart for counting frequency measurement module in fpga chip.
Fig. 9 is that the DI in fpga chip interrupts the flow chart interrupted with HDI.
Figure 10 is that the high-speed counting in fpga chip interrupts flow chart.
Figure 11 is the filtering process block flow diagram in fpga chip.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.
As shown in Figure 1, 2, a kind of multi-shaft motion control system based on FPGA, including power supply, crystal oscillator, jtag circuit, ARM
Chip, fpga chip, 15 road DI input circuits, 8 road HDI input circuits and 16 road HDO output circuits, described 15 road DI inputs
Circuit and 8 road HDI input circuits, the limiting filter circuit and optocoupler being sequentially connected respectively including input protection circuit and with it every
From circuit, the 16 road HDO output circuits, including output protection circuit and the output driving circuit and optocoupler that are sequentially connected with it
Isolation circuit, the optical coupling isolation circuit, for avoid the external world interference, wherein 15 road DI input circuits using common optical coupler every
From 8 road HDI input circuits and 16 road HDO output circuits are isolated using high speed photo coupling, limiting filter circuit, for avoiding signal
Burr interference, the optical coupling isolation circuit is connected with fpga chip respectively, for the processing of motion control signal, the JTAG
Circuit is connected with fpga chip and ARM chips respectively, and jtag circuit is used for director demon and downloads and debug, and ARM chips are carried out
The computing and configuration of motion control data, are communicated by FSMC communication interfaces with fpga chip, are held in fpga chip built-in system
The corresponding function of row, the power supply is connected with crystal oscillator, ARM chips and fpga chip respectively, and crystal oscillator is also connected with fpga chip, is
Fpga chip provides clock, and clock is carried out into scaling down processing inside FPGA, is respectively ARM chips and the Ethernet offer of outside
Clock；The fpga chip includes clock module, communication interface modules, interrupt module, counting frequency measurement module, data buffer storage control
Module, PLS modules, pulse output module, signal output selecting module, enable bit control module, enable bit selecting module and DI
Filtering process module and HDI filtering process modules, wherein, communication interface modules is connected with data buffer storage control module, and communication connects
Mouth mold block is used for the data interaction of ARM chips and fpga chip, and data buffer storage control module is used for data buffer storage, and will be corresponding
Data configuration performs corresponding function, DI filtering process module and HDI the filtering process module point to each submodule port
It is not connected by interrupt module with data buffer storage control module, at by 15 road DI signals, 8 road HDI signals by DI filtering
15 road DI signals that reason module and HDI filtering process modules are obtained after filtering again, 8 road HDI signals are by after interrupt module
The road DI interrupt signals of Dao 15,8 road HDI interrupt signals are directly output to ARM chips, and obtained interrupting channel value is respectively sent to
Data buffer storage control module, the HDI filtering process module is also connected by counting frequency measurement module with data buffer storage control module,
For the 8 road HDI signals that are obtained after 8 road HDI signals are filtered again by HDI filtering process modules by counting frequency measurement module
Frequency measurement counting is carried out, and data buffer storage control module is sent in real time by frequency measurement data are counted；The DI filtering process module and
HDI filtering process module is joined directly together with data buffer storage control module respectively, when not interrupting, and filtered signal is directly defeated
Go out to data buffer storage control module；The data buffer storage control module passes through enable bit control module, enable bit selecting module, arteries and veins
Output module is rushed to be sequentially connected with signal output selecting module, wherein, the enable bit selecting module is entered to pulse output module
Row selection, pulse output module is tied to fixed enable bit, then by configuring enable bit control module, enables signal warp
Cross enable bit selecting module to enable selected pulse output module, controlled by enable bit selecting module and enable bit
The synchronous interaction for realizing independent controlled motor axle and many motor shafts is used in combination in module；The pulse output module, using FIFO
As data buffer storage mechanism, while being controlled to 8 motor shaft motions；The signal output selecting module passes through PLS modules
It is connected with data buffer storage control module, the road HDO signal output ports of signal output selecting module Hai Yu 16 are connected.
As shown in figure 3, the output of the invention in order to ensure pulse continuous-stable, and acceleration and deceleration and the control of interpolation points
System, data buffer storage is carried out using FIFO；The premise of pulse output is FIFO non-NULLs, because FIFO is provided only for pulse output module
One data configuration.Described ARM is that FIFO writes data, after signal feeding is enabled, the loading of data is carried out first, judgement is
It is no to there is commutation to be delayed, if commutation, it is necessary to which pulse could be exported after the time for waiting commutation delay；Overall process judges that FIFO is
No non-NULL, performs the circulation of the above if non-NULL, out of service if FIFO empty, and pulse output stops.When forbidden energy signal is effective
When, it is necessary to which this all pulses output is finished after, pulse output stops.Emergent stop signal, when jerk is effective, pulse output is vertical
Carve and stop, keeping in the number that current PRF is counted, feed back to ARM.
As shown in figure 4, the direction output of pulse output module of the present invention is individually designed, when pulse output module fortune
Capable beginning is, it is necessary to the current angle detecting of motor, now detect that state is kept.If new direction is identical with last time direction,
It need not then commutate, now commutation states need not be kept, reload commutation delay value, when there is commutation to be delayed again, wait this
Subpulse end of output, the angle detecting at the end of；If new direction is different from last time direction, new direction is exported first, is protected
Angle detecting is held, commutation delay is carried out.
As shown in figure 5, selecting 0-N enable bit selecting modules first, the pulse output mould of No. 0-N correspondingly have selected
Block, then the pulse output module chosen is tied to fixed enable bit, then by configuring enable bit control module, enable
Signal is enabled by enable bit selecting module to selected pulse output module, passes through enable bit selecting module and enable
The synchronous interaction for realizing independent controlled motor axle and many motor shafts is used in combination in position control module.
As shown in fig. 6, the module can only disposably export pulse, when the pulse of output is reached according to certain rate-adaptive pacemaker
During setting value, stop pulse output, this process is without acceleration and deceleration, but the module can export pulse with constant speed.
As shown in Figure 7,8, after HDI filtering process module filters high speed signal, signal is transferred to counting frequency measurement module, root
According to the selection of technology mode, detect pulse signal and then start counting up frequency measurement, the count value that counter is produced passes through communication in real time
Interface module feeds back to ARM chips.
As shown in Fig. 9,10, interrupt module is divided into two parts, and a part of DI as shown in Figure 9 is interrupted and HDI is interrupted；It is another
Partly high-speed counting as shown in Figure 10 is interrupted.The generation principle that DI is interrupted with HDI is interrupted is identical, and interrupt mode has three kinds, i.e.,
Rising edge is interrupted, trailing edge is interrupted or rising edge, trailing edge are interrupted.After pattern configurations are interrupted, to DI signals along detection, once
There is interrupt signal, interrupt requests are sent immediately, interrupting channel is at the same time fed back into ARM chips.High-speed counting interrupt module,
Main realize counts to outside input pulse, when count value reaches setting value, produces interrupt signal.In addition, interrupting setting value
Set in real time by user, multiple interruption demand of the user for counting can be met, the interrupt mode is uniformly matched somebody with somebody with DI interrupt modes
Put, counting interrupt request signal and the public same circuit of DI interrupt request singals of generation.
As shown in figure 11, after data signal is by input circuit, first passes around filtering process module and filter again, it is main complete
Paired high frequency narrow ripple is filtered out.The half cycle time for setting the pulse period samples to input signal, therefore when input signal
When half period is more than or equal to setting time, it can sample, input is normal；Once the pulse half period of input is less than setting time,
That is input pulse frequency is too high, then can not correctly sample semiperiodic signal.
Claims (1)
1. a kind of multi-shaft motion control system based on FPGA, including power supply, crystal oscillator, jtag circuit, ARM chips, fpga chip,
15 road DI input circuits, 8 road HDI input circuits and 16 road HDO output circuits, 15 described road DI input circuits and 8 road HDI are defeated
Enter circuit, the limiting filter circuit and optical coupling isolation circuit being sequentially connected respectively including input protection circuit and with it, described 16
Road HDO output circuits, including output protection circuit and the output driving circuit and optical coupling isolation circuit that are sequentially connected with it, it is described
Optical coupling isolation circuit, the interference for avoiding the external world, wherein 15 road DI input circuits are isolated using common optical coupler, 8 road HDI inputs
Circuit and 16 road HDO output circuits are isolated using high speed photo coupling, limiting filter circuit, for avoiding the burr of signal from disturbing, its
It is characterised by：The optical coupling isolation circuit is connected with fpga chip respectively, for the processing of motion control signal, the JTAG electricity
Road is connected with fpga chip and ARM chips respectively, and jtag circuit is used for director demon and downloads and debug, and ARM chips are transported
The computing and configuration of dynamic control data, are communicated by FSMC communication interfaces with fpga chip, are performed in fpga chip built-in system
Corresponding function, the power supply is connected with crystal oscillator, ARM chips and fpga chip respectively, and crystal oscillator is also connected with fpga chip, is
Fpga chip provides clock, and clock is carried out into scaling down processing inside FPGA, is respectively ARM chips and the Ethernet offer of outside
Clock；The fpga chip includes clock module, communication interface modules, interrupt module, counting frequency measurement module, data buffer storage control
Module, PLS modules, pulse output module, signal output selecting module, enable bit control module, enable bit selecting module and DI
Filtering process module and HDI filtering process modules, wherein, communication interface modules is connected with data buffer storage control module, and communication connects
Mouth mold block is used for the data interaction of ARM chips and fpga chip, and data buffer storage control module is used for data buffer storage, and will be corresponding
Data configuration performs corresponding function, DI filtering process module and HDI the filtering process module point to each submodule port
It is not connected by interrupt module with data buffer storage control module, at by 15 road DI signals, 8 road HDI signals by DI filtering
15 road DI signals that reason module and HDI filtering process modules are obtained after filtering again, 8 road HDI signals are by after interrupt module
The road DI interrupt signals of Dao 15,8 road HDI interrupt signals are directly output to ARM chips, and obtained interrupting channel value is respectively sent to
Data buffer storage control module, the HDI filtering process module is also connected by counting frequency measurement module with data buffer storage control module,
For the 8 road HDI signals that are obtained after 8 road HDI signals are filtered again by HDI filtering process modules by counting frequency measurement module
Frequency measurement counting is carried out, and data buffer storage control module is sent in real time by frequency measurement data are counted；The DI filtering process module and
HDI filtering process module is joined directly together with data buffer storage control module respectively, when not interrupting, and filtered signal is directly defeated
Go out to data buffer storage control module；The data buffer storage control module passes through enable bit control module, enable bit selecting module, arteries and veins
Output module is rushed to be sequentially connected with signal output selecting module, wherein, the enable bit selecting module is entered to pulse output module
Row selection, pulse output module is tied to fixed enable bit, then by configuring enable bit control module, enables signal warp
Cross enable bit selecting module to enable selected pulse output module, controlled by enable bit selecting module and enable bit
The synchronous interaction for realizing independent controlled motor axle and many motor shafts is used in combination in module；The pulse output module, using FIFO
As data buffer storage mechanism, while being controlled to 8 motor shaft motions；The signal output selecting module passes through PLS modules
It is connected with data buffer storage control module, the road HDO signal output ports of signal output selecting module Hai Yu 16 are connected.
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| CN201710460075.1A CN107203177A (en) | 2017-06-17 | 2017-06-17 | A kind of multi-shaft motion control system based on FPGA |
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| CN109129493A (en) * | 2018-11-09 | 2019-01-04 | 梁浩睿 | A kind of three axle robert arm control system |
| CN109240170A (en) * | 2018-10-24 | 2019-01-18 | 深圳市微芯智能科技有限公司 | Multi-axis motion control chip controls method, apparatus, readable storage medium storing program for executing and system |
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| CN111665752A (en) * | 2020-05-27 | 2020-09-15 | 中国核电工程有限公司 | FPGA-based loading and unloading machine motion control system and method |
| CN112162532A (en) * | 2020-09-15 | 2021-01-01 | 北京机电工程研究所 | Motion control system suitable for multi-degree-of-freedom platform |
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| CN109240170A (en) * | 2018-10-24 | 2019-01-18 | 深圳市微芯智能科技有限公司 | Multi-axis motion control chip controls method, apparatus, readable storage medium storing program for executing and system |
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| CN111665752A (en) * | 2020-05-27 | 2020-09-15 | 中国核电工程有限公司 | FPGA-based loading and unloading machine motion control system and method |
| CN111665752B (en) * | 2020-05-27 | 2022-09-27 | 中国核电工程有限公司 | FPGA-based loading and unloading machine motion control system and method |
| CN112162532A (en) * | 2020-09-15 | 2021-01-01 | 北京机电工程研究所 | Motion control system suitable for multi-degree-of-freedom platform |
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