CN101741274A - Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector - Google Patents
Modulation method and implementation circuit for unit vector to carrying out time-delay superimposition of multi-level space vector Download PDFInfo
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Abstract
The invention relates to modulation method and implementation circuit for a unit vector to carrying out the time-delay superimposition of a multi-level space vectors, belonging to the field of electrical energy conversion and solving the problem that a cascading type inverter is modified by adopting a traditional multi-level SVM (Support Vector Machine) method, vector selection is needed, and a calculating method is complicated. The modification method comprises the following steps of: equalizing the unit of each stage of a three-phase N-stage unit cascading type inverter into two double-level three-phase inverters; calculating the output voltage vector of a left bridge arm equivalent inverter of the first-stage unit at the beginning time of a calculating period by adopting a double-level space vector modification method; acting the voltage vector on a left bridge arm equivalent inverter of an ith-stage unit after the voltage vector is delayed by (i-1)Ts/2N; and after delaying, acting on a right bridge arm equivalent inverter of the ith-stage unit so as to realize the output of a multi-level PWM voltage wave form. The implementation circuit consists of a DSP (Digital Signal Processor) chip and a field programmable gate array (FPGA). The invention is used for Modulating the multi-level space vector of the cascading type inverter.
Description
Technical field
The present invention relates to a kind of modulator approach of element vectors time-delay superimposition of multi-level space vector and realize circuit, belong to the transformation of electrical energy field.
Background technology
Cascade multilevel inverter is by having realized the unit cascaded mode of a plurality of low pressure H bridges the electric energy conversion in high pressure field, effectively reduce voltage change ratio stress simultaneously, significantly improved electromagnetic environment, obtained extensive use in fields such as high-voltage motor energy-saving speed regulatings.Key factor---many level PWMs method as direct decision inverter control effect has been subjected to the common concern of Chinese scholars, and has carried out number of research projects.Many level PWMs method of cascaded inverter mainly comprises phase-shifting carrier wave SPWM (CPS-SPWM) method at present, and many level SVM method and selective harmonic are eliminated PWM (SHEPWM) method etc.Wherein the CPS-SPWM method has realized many level output waveform by the certain angle that staggers mutually of the phase place with each carrier wave, but because its thought based on SPWM, voltage utilization is lower, and is difficult to merge mutually with the high-performance motor control strategy.The SVM method is a starting point with the notion of space vector of voltage, has the voltage utilization height, being easy to advantage such as Digital Realization has obtained to pay close attention to widely in two-level inverter, but for many level of tradition SVM method, because small vector quantity is more, cause algorithm too complicated, be applied to the following situation of seven level at present.Though occurred some fast algorithms in recent years, because its thought of still selecting based on vector, the problems referred to above are not solved well.The SHEPWM method is eliminated the low frequency subharmonic of appointment by the optimized choice of switching time, can obtain minimum switching frequency, but needs to calculate transcendental equation, and can only eliminate the limited number of time harmonic wave, and practicality is restricted.
Summary of the invention
The purpose of this invention is to provide a kind of modulator approach of element vectors time-delay superimposition of multi-level space vector and realize circuit, it has solved cascaded inverter and has adopted traditional many level SVM method to modulate, and needs vector to select to make the computational methods complicated problems.
Its modulator approach comprises the steps:
Step 1: with the left brachium pontis of three the H bridge inverters in each grade unit of the unit cascaded type inverter of three-phase N level and right brachium pontis respectively equivalence be left bridge arm equivalent inverter and right bridge arm equivalent inverter, making the output voltage vector equivalence of each grade of the unit cascaded type inverter of three-phase N level unit is the poor of left bridge arm equivalent inverter and right bridge arm equivalent inverter output voltage vector, and N is the natural number greater than 1;
Step 2: the computing cycle of setting the unit cascaded type inverter of three-phase N level is T
s, the progression of unit is i, i is natural number and i≤N, in each computing cycle zero hour, adopts two level space vector modulator approaches to calculate the output voltage vector of the left bridge arm equivalent inverter of the unit cascaded type inverter of three-phase N level first order unit;
Step 3: at each computing cycle T
sIn, with the output voltage vector that calculates in the described step 2, time-delay (i-1) T
sAct on the left bridge arm equivalent inverter of i level unit behind the/2N; Time-delay
After act on the right bridge arm equivalent inverter of i level unit, thus at a computing cycle T
sIn finish the renewal of unit at different levels output voltage vector, realize the output of many level PWMs voltage waveform.
A kind of realization circuit of the modulator approach of element vectors time-delay superimposition of multi-level space vector: it is made up of dsp chip and FPGA field programmable gate array, the FPGA field programmable gate array is made up of data latching module, decoding module, voltage vector module, Dead Time module, PWM control module, counter cycle value module, counter group, a N PWM generator and N signal interlocking module
The control data output of dsp chip connects the control data input of data latch module, the address signal output of dsp chip connects the address signal input of decoding module, the module of decoding module selects the enable signal output to connect the address signal input of data latch module, the control data output of data latching module connects the element vectors input of voltage vector module simultaneously, the Dead Time input of Dead Time module, the time signal input of the signal input end sum counter periodic quantity module of PWM control module, the control signal output ends of voltage vector module connects the signal input end of N PWM generator simultaneously, the signal output part of Dead Time module connects the dead band signal input part of N signal interlocking module simultaneously, the locking signal output of PWM control module connects the locking signal input of N signal interlocking module simultaneously, the enable signal input of the enable signal output linkage counter group of PWM control module, the count signal output of the count signal input linkage counter periodic quantity module of counter group, the count signal output of counter group connects the count signal input of N PWM generator simultaneously, and the control number output of each PWM generator connects the signal input end of a signal interlocking module.
The module of decoding module selects enable signal to represent the module of the address signal correspondence of its input, is the module of the data correspondence of data latching module input, realizes the function of corresponding data input respective modules.For example: when the enable signal of decoding module output voltage vector module, the data of data latching module output are cell vector data, this moment, the voltage vector module can receive these data, and Dead Time module, PWM control module sum counter periodic quantity module do not receive these data.
Advantage of the present invention is:
The present invention adopts element vectors time-delay superimposition of multi-level space vector modulating method (Overlap TimeDelayed-Space Vector Modulation, OTD-SVM) and realize circuit, to simplify many level SVM control algolithm of existing cascaded inverter, in high cascade connection type number inverter, realize the space vector of voltage modulation, improved the control performance of inverter.It when increasing the cascade number, does not increase the computational burden of DSP by stack that cell voltage vectors at different levels are delayed time in turn, effectively reduces the requirement to system resource.It is simple for structure to adopt the implementation of DSP+FPGA to have, and control convenient, flexiblely, is convenient to expansion and is easy to and advantages such as advanced control strategy combines, and realizes for high cascade number inverter that space vector of voltage is modulated new approach is provided, and has clear superiority.
Description of drawings
Fig. 1 is the schematic diagram of three-phase primary unit cascaded inverter; Fig. 2 is with the left brachium pontis of three H bridge inverters among Fig. 1 and the equivalent respectively schematic diagram for left bridge arm equivalent inverter and right bridge arm equivalent inverter of right brachium pontis; Fig. 3 is the vector superposed schematic diagram of primary unit inverter output voltage; Fig. 4 is the vector superposed schematic diagram of N level unit inverter output voltage; Fig. 5 is the structured flowchart that the present invention realizes circuit; Fig. 6 is the schematic diagram of seven segmentation switching modes in the execution mode two; Fig. 7 is the phase diagram of the counter corresponding with each brachium pontis in the FPGA field programmable gate array in the execution mode two; Fig. 8 is the waveform schematic diagram of the last switching tube on the same brachium pontis and the interlocking of following switching tube signal in the execution mode two, and dash area is represented Dead Time among the figure.
Embodiment
Embodiment one: below in conjunction with Fig. 1-Fig. 4 present embodiment is described, present embodiment comprises the steps:
Step 1: with the left brachium pontis of three the H bridge inverters in each grade unit of the unit cascaded type inverter of three-phase N level and right brachium pontis respectively equivalence be left bridge arm equivalent inverter and right bridge arm equivalent inverter, making the output voltage vector equivalence of each grade of the unit cascaded type inverter of three-phase N level unit is the poor of left bridge arm equivalent inverter and right bridge arm equivalent inverter output voltage vector, and N is the natural number greater than 1;
Step 2: the computing cycle of setting the unit cascaded type inverter of three-phase N level is T
s, the progression of unit is i, i is natural number and i≤N, in each computing cycle zero hour, adopts two level space vector modulator approaches to calculate the output voltage vector of the left bridge arm equivalent inverter of the unit cascaded type inverter of three-phase N level first order unit;
Step 3: at each computing cycle T
sIn, with the output voltage vector that calculates in the described step 2, time-delay (i-1) T
sAct on the left bridge arm equivalent inverter of i level unit behind the/2N; Time-delay
After act on the right bridge arm equivalent inverter of i level unit, thus at a computing cycle T
sIn finish the renewal of unit at different levels output voltage vector, realize the output of many level PWMs voltage waveform.
The modulator approach principle:
The equivalent construction of cascaded inverter: three-phase primary unit cascaded inverter shown in Figure 1 is split as two three-phases, three brachium pontis two-level inverters, i.e. equivalence is left bridge arm equivalent inverter and right bridge arm equivalent inverter, as seen the output of cascaded inverter is equivalent to the poor of two three-phase inverter output voltage space vectors, therefore control respectively by left and right sides brachium pontis, two level SVM methods can be incorporated in the cascaded inverter each H bridge inverter.
The modulator approach of primary unit: for three-phase cascaded inverter topology, according to Fig. 1, the synthesized voltage vector u ' of three H bridge inverter outputs of primary unit
1Can be regarded as left bridge arm voltage vector u
L1With right bridge arm voltage vector u
R1Poor, that is: u '
1=u
L1-u
R1, be three level for making H bridge inverter output voltage, need make the control signal of the left and right sides brachium pontis certain hour that staggers, can realize by the method for delayed updating output vector.Therefore with the voltage vector u of the left brachium pontis of two level SVM algorithm computation
L1, again with its time-delay T
sAfter/2 times, identical voltage vector is affacted right brachium pontis.The concrete T that exactly pwm control signal that contains duty cycle information of left brachium pontis delayed time
sAfter/2 times, control the power device of right brachium pontis with identical control signal, it should be noted that, act on and to be added to after the control signal time-delay of switching tube on the left brachium pontis under the right brachium pontis on the switching tube, make left and right sides bridge arm voltage vector become the relation of addition, the control signal of two power devices of same brachium pontis is the relation of negate, through above-mentioned connection, make output voltage become left and right sides brachium pontis output voltage and.
If need the voltage vector amplitude of output this moment is V, the amplitude of the left and right sides bridge arm voltage vector that then calculates is V/2.This method is equivalent to have certain phase difference between the brachium pontis output voltage vector of the left and right sides, vector composition principle such as Fig. 3 of primary unit cascaded inverter.Because computing cycle T
sVery short, be μ s level, the differential seat angle of left and right sides bridge arm voltage vector is very little, can ignore, so left and right sides bridge arm voltage vector and amplitude still can regard as: | u '
1|=| u
L1+ u
R1| ≈ V.
N level cells modulate method: for the unit cascaded type inverter of N level, can become 2N the voltage vector that amplitude is identical to the desired resultant voltage resolution of vectors, then total vector u '
NsumCan be expressed as:
u′
Nsum＝u
L1+u
L2+…+u
Li+…+u
LN+
u
R1+u
R2+…+u
Ri+…+u
RN
U wherein
L1To u
LNBe the voltage vector of a left side, unit at different levels brachium pontis output, u
R1To u
RNVoltage vector for the right brachium pontis output in unit at different levels; If adopt identical modulator approach between each H bridge inverter, output voltage is the simple superposition of same waveform, though can obtain resultant vector, can not form many level waveform.Therefore still continue to use the method for time-delay stack, with each unit output PWM waveform T that delays time in proper order
s/ 2 times, can form many level waveform.Different is no longer the action time of each small vector of double counting, only to calculate u
L1Action time, the vector of a left side, i unit brachium pontis u that lags behind action time
L1Be (i-1) T action time
sLag behind action time left brachium pontis vector of/2N, the right brachium pontis vector of same H bridge inverter still is T action time
s/ 2, so it lags behind u
L1Time t
RiFor:
Fig. 4 has provided the output voltage vector stack situation under the N level cell cases, because the vector updated time is 2N, corresponding overlaying state also is 2N, only provides middle vector superposed state constantly here.This method is equivalent to have certain phase difference between each vector, because the sampling time is very little usually with respect to the fundamental voltage output of voltage cycle, phase difference is very little between each vector, therefore during the compute vectors amplitude, still can think their same-phases, then the amplitude of each vector is about 1/ (2N) of total synthetic amplitude, that is:
Embodiment two: present embodiment is described below in conjunction with Fig. 5-Fig. 8, present embodiment is made up of dsp chip 1 and FPGA field programmable gate array 2, FPGA field programmable gate array 2 is made up of data latching module 2-1, decoding module 2-2, voltage vector module 2-3, Dead Time module 2-4, PWM control module 2-5, counter cycle value module 2-6, counter group 2-7, a N PWM generator 2-8 and N signal interlocking module 2-9
The control data output of dsp chip 1 connects the control data input of data latch module 2-1, the address signal output of dsp chip 1 connects the address signal input of decoding module 2-2, the module of decoding module 2-2 selects the enable signal output to connect the address signal input of data latch module 2-1, wherein the address signal and the control data of data latching module 2-1 reception are one to one, behind the corresponding address of address signal gating that receives, be input to corresponding module with address signal control corresponding data, the control data output of data latching module 2-1 connects the element vectors input of voltage vector module 2-3 simultaneously, the Dead Time input of Dead Time module 2-4, the time signal input of the signal input end sum counter periodic quantity module 2-6 of PWM control module 2-5, the control signal output ends of voltage vector module 2-3 connects the signal input end of N PWM generator 2-8 simultaneously, the signal output part of Dead Time module 2-4 connects the dead band signal input part of N signal interlocking module 2-9 simultaneously, the locking signal output of PWM control module 2-5 connects the locking signal input of N signal interlocking module 2-9 simultaneously, the enable signal input of the enable signal output linkage counter group 2-7 of PWM control module 2-5, the count signal output of the count signal input linkage counter periodic quantity module 2-6 of counter group 2-7, the count signal output of counter group 2-7 connects the count signal input of N PWM generator 2-8 simultaneously, and the control number output of each PWM generator 2-8 connects the signal input end of a signal interlocking module 2-9.
Workflow and operation principle:
Provide the implementation of three grades of unit cascaded type inverters below.For three grades of cell cases, constitute by 9 H bridge inverters, need 36 road PWM drive waveforms altogether.According to the characteristics of algorithm, because dsp chip 1 aspect data processing and the separately advantage of FPGA aspect logical process, is selected the design that adopts DSP and FPGA to combine.
Realize that based on the circuit structure of DSP+FPGA the method for OTD-SVM is divided into two level SVM algorithms and vector time-delay superposition algorithm two parts are finished respectively, wherein two level SVM algorithms are finished in dsp chip 1, and FPGA finishes the time-delay stack and the output of corresponding pwm signal of vector.As shown in Figure 4, FPGA links to each other with the data/address bus of dsp chip 1, and with the peripheral hardware of FPGA as dsp chip, expands in the ZONEO zone, and the address of FPGA is distributed unitedly by dsp chip.DSP and FPGA data transmit the parallel bus mode that adopts.By dsp chip to computing cycle T
sIncreased the flexibility of system with dead band value setting, the output that can enable or block whole pwm signals simultaneously.One big advantage of this structure is, if when changing the element number that drives, need not to change the program of DSP part, only needs to increase corresponding time-delay laminating module and get final product in FPGA.The number of pins of fpga chip is more simultaneously, and its function can be provided with as required, is convenient to realize the output of multi-channel PWM signal.
In addition, for obtaining excellent control performances, adopt seven segmentation SVM switching modes.As shown in Figure 5, DSP regularly needs to send to five data of FPGA in interruption subroutine at each, comprises current master vector and action time thereof, auxilliary vector and action time thereof and zero vector action time.Simultaneously, in initialize routine, need be the periodic quantity of counter among the FPGA, and rolling counters forward enable command and PWM output blocking instruction send FPGA to dead band value and computing cycle.Above-mentioned data allow change in real time.In order to save resource, adopt coded system, six signal interlocking module 2-9 are set in FPGA, above-mentioned five data and two instructions are latched, wherein corresponding instruction according to the difference that transmits content, is carried out in the public same address of enable command and blocking instruction.
Because in each computing cycle, only need to upgrade once main and auxiliary vector and corresponding action time, therefore in the timing interruption subroutine of each DSP, only calculate vector and action time thereof, by FPGA new result of calculation is carried out the time-delay stack of each vector again, respectively the function of DSP and FPGA is described in detail below.
The function design of DSP:
Need to finish two level SVM algorithms among the DSP, the action time of calculating the main and auxiliary vector in each sector and zero vector and each vector, and send FPGA to by data/address bus.Different vectors and action time thereof transmit with different addresses, need simultaneously FPGA is carried out necessary configuration, comprise the dead band value of computing cycle value and pwm signal interlocking, and need enable or block PWM output control signal to the FPGA transmission.
The algorithm design of FPGA:
The main generation that realizes the latching of data, address decoding and control command among the FPGA, the renewal of each voltage vector action time, vector arrives action time such as the conversion of PWM generator output signal and the dead band generation of output signal etc., comprise decoding module 2-2, data latching module 2-1, counter group 2-7, PWM generator 1～PWM generator N, and the signal interlocking module 1～signal interlocking module N that is used to produce the dead band.For three grades of cell cases, comprise 6 counters, three PWM generator 2-8 and three signal interlocking module 2-9.
Address decoding and Data Update:
In FPGA, give above-mentioned each module distribute data latch respectively, so that the storage data.The renewal of data mainly be data that DSP is sent according to its address latch in corresponding latch, need decoding module 2-2 and data latching module 2-1, the effect of address decoding module 2-2 is that the data address that DSP sends is distinguished, produce corresponding enable signal according to different addresses, to enable the latch of inner each module.Decoding module 2-2 is input as address signal, it is exported each signal and deciphers according to table 1, because latch allows data to pass through when high level, therefore latch data when low level can be latched into corresponding data in the latch during for low level by hypermutation at each corresponding enable signal.
Table 1
The pwm signal generation module:
For power controlling device work, vector need be converted to pwm signal action time.With seven segmentation switching mode PWM generation methods with the one-level unit is that example describes, as shown in Figure 6, and at T
K0Constantly, the output zero vector, be low level with switch controlled signal on the left brachium pontis of each unit of one-level this moment.Counter is constantly counted, and compares with the numerical value of zero vector action time.(correspondingly be T constantly if be worth therewith when identical
K1), master vector is affacted on each switching tube, continue counting, and with zero vector and master vector action time and compare, if (the corresponding moment is T when count value equates with it
K2), the auxilliary vector of output.Add the value of zero vector, and compare with ever-increasing count value, (corresponding is T constantly when equating
K3), export complete 1 zero vector, (corresponding is T constantly to be added to periodic quantity up to counter
K4), begin to subtract counting.Subtract counting process and to increase counting process identical, finished the seven segmentation SVM waveforms output of a computing cycle thus.
The time-delay stack of voltage vector:
In order to realize the time-delay stack of voltage vector, 6 counters need be set in counter group 2-7, corresponding 6 equivalent two-level inverters, individual count device phase relation is as shown in Figure 7.Wherein the counter initial value of the inverter of a left side, first order unit brachium pontis formation is made as zero, and the initial value of other counter is calculated according to following formula by Fig. 7:
In the formula, n is a counter place sequence of unit number, n=1, and 2 ..., N; C
NL(0), C
NR(0) is respectively the initial value of the counter of n level unit left and right bridge arm equivalent inverter correspondence, C
CleBe half of counter cycle value.Result of calculation is listed in table 2.Each counter arrives the asynchronism(-nization) at zero point like this, owing to all upgrade when count value is zero the vector of each brachium pontis correspondence and action time thereof, the updated time of each vector action time is also different like this, can realize the time-delay stack of voltage vector.Wherein, counter and DSP that a left side, first order unit brachium pontis uses regularly interrupt synchronously, and promptly when DSP regularly interrupted arriving, this counter should be zero, and this moment, other counter just in time count down to initial value.At this moment, DSP is to its each vector and upgrade action time, and a left side, first order unit brachium pontis will be exported new voltage vector, for avoiding producing synchronous error between DSP and the FPGA, value with all counters when each DSP regularly interrupts arriving changes initial value into, is forced synchronism.At this moment, other counter also no count arrives null value, vector and action time thereof do not upgrade, through the set time, the counter meter of a left side, next stage unit brachium pontis is to zero, this moment is with a first order unit left side pairing vector of brachium pontis and write action time in the pairing latch in order, finish the renewal of self output voltage vector, when other counter arrives null value, finish same operation, and be input to the identical PWM generator of function, thus, finish the waveform output of three grades of unit of computing cycle OTD-SVM method.
Table 2
The dead band generation module:
For the bridge inverter main circuit structure, need the dead band be set to the drive signal of switching tube up and down.Here adopt a kind of fairly simple method, the two paths of signals level is changed to be staggered constantly mutually, schematic diagram as shown in Figure 8, the specific implementation method is, pwm signal negate to modular converter output is input to two paths of signals the signal interlocking module again, and output signal is the drive waveforms of the upper and lower bridge arm that staggers mutually, the counter cycle of interlocking module is adjustable, can realize the online change in dead band.
The decoding of control command produces:
For control command, the level after the decoding is permanently effective, therefore takes elder generation that the content of institute's corresponding address is latched, and again to its method of deciphering, the decode results of data and correspondence thereof is as shown in table 3.If think enable counter, promptly enable the signal output of PWM generator 2-8, then need in latch, to write 000, counter is started working; If want to block PWM output, then in same latch, write 111, Counter Value becomes initial value, and quits work, all PWM output becoming high-impedance states; If other value, then counter break-off, the PWM output signal remains unchanged.
Table 3
Provided the implementation of three grades of unit above, for more level situations, need not to change the program among the DSP, only need in FPGA, increase corresponding counter by counter group 2-7, PWM generator and signal interlocking module are disposed accordingly and can realize its parameter by DSP again.
Present embodiment only provides a kind of circuit structure of realizing the inventive method, but realizes that method of the present invention is not limited to institute and gives an actual example.
Claims (2)
1. the modulator approach of an element vectors time-delay superimposition of multi-level space vector, it is characterized in that: its modulator approach comprises the steps:
Step 1: with the left brachium pontis of three the H bridge inverters in each grade unit of the unit cascaded type inverter of three-phase N level and right brachium pontis respectively equivalence be left bridge arm equivalent inverter and right bridge arm equivalent inverter, making the output voltage vector equivalence of each grade of the unit cascaded type inverter of three-phase N level unit is the poor of left bridge arm equivalent inverter and right bridge arm equivalent inverter output voltage vector, and N is the natural number greater than 1;
Step 2: the computing cycle of setting the unit cascaded type inverter of three-phase N level is T
s, the progression of unit is i, i is natural number and i≤N, in each computing cycle zero hour, adopts two level space vector modulator approaches to calculate the output voltage vector of the left bridge arm equivalent inverter of the unit cascaded type inverter of three-phase N level first order unit;
Step 3: at each computing cycle T
sIn, with the output voltage vector that calculates in the described step 2, time-delay (i-1) T
sAct on the left bridge arm equivalent inverter of i level unit behind the/2N; Time-delay
After act on the right bridge arm equivalent inverter of i level unit, thus at a computing cycle T
sIn finish the renewal of unit at different levels output voltage vector, realize the output of many level PWMs voltage waveform.
2. based on a kind of realization circuit of the modulator approach of the described element vectors time-delay superimposition of multi-level of claim 1 space vector: it is characterized in that: it is made up of dsp chip (1) and FPGA field programmable gate array (2), FPGA field programmable gate array (2) is by data latching module (2-1), decoding module (2-2), voltage vector module (2-3), Dead Time module (2-4), PWM control module (2-5), counter cycle value module (2-6), counter group (2-7), N PWM generator (2-8) and N signal interlocking module (2-9) are formed
The control data output of dsp chip (1) connects the control data input of data latch module (2-1), the address signal output of dsp chip (1) connects the address signal input of decoding module (2-2), the module of decoding module (2-2) selects the enable signal output to connect the address signal input of data latch module (2-1), the control data output of data latching module (2-1) connects the element vectors input of voltage vector module (2-3) simultaneously, the Dead Time input of Dead Time module (2-4), the time signal input of the signal input end sum counter periodic quantity module (2-6) of PWM control module (2-5), the control signal output ends of voltage vector module (2-3) connects the signal input end of N PWM generator (2-8) simultaneously, the signal output part of Dead Time module (2-4) connects the dead band signal input part of N signal interlocking module (2-9) simultaneously, the locking signal output of PWM control module (2-5) connects the locking signal input of N signal interlocking module (2-9) simultaneously, the enable signal input of the enable signal output linkage counter group (2-7) of PWM control module (2-5), the count signal output of the count signal input linkage counter periodic quantity module (2-6) of counter group (2-7), the count signal output of counter group (2-7) connects the count signal input of N PWM generator (2-8) simultaneously, and the control number output of each PWM generator (2-8) connects the signal input end of a signal interlocking module (2-9).
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2009
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| CN111478567B (en) * | 2020-03-12 | 2022-06-10 | 南京航空航天大学 | Cascade H-bridge rectifier bias component and fundamental component injection voltage-sharing method |
| CN113452257A (en) * | 2021-06-23 | 2021-09-28 | 上海电机学院 | Multi-path PWM wave generating circuit for controlling DAB converter based on FPGA |
| CN115882744A (en) * | 2023-02-27 | 2023-03-31 | 闽南理工学院 | Optimization method for SHEPWM modulation switch angle storage |
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