CN105911912A - Numerical control machine tool multi-sensor data synchronous latching method - Google Patents

Abstract

A numerical control machine tool multi-sensor data synchronous latching method relates to the field of high-end machine tool manufacturing equipment, and is applied to the industry of high-end machine tool manufacturing equipment. The method comprises three function parts, namely, parameter setting, data latching, and data fusing and uploading. A parameter setting module sets the sampling frequency, sampling voltage amplitude and digital signal reference value. A data latching module synchronously latches eight channels of analog signals and six channels of digital signals. A data fusing and uploading module processes and analyzes data, and transmits the data in real time to a principal computer. The method is of high degree of integration. The mode of data acquisition is simplified. The problem that the real-time performance of multi-sensor data synchronization is poor is solved.

Description

A kind of Digit Control Machine Tool multi-sensor data synchronizes latch method

Technical field

The present invention relates to high-end Machine Manufacture equipment field, be applied particularly to and multiple grating sensing is installed Device latches with the synchrodata of the Digit Control Machine Tool data of position, many sides sensing.

Background technology

Along with electronic technology and the development of computer technology, lathe the test digitized of system, collection One-tenthization degree is more and more higher, and test system is the most complicated, and high-precision machine tool system is tested, to survey In examination, the synchronous acquisition performance of multiple sensor data is had higher requirement.Add at existing lathe Work and manufacturing, the collecting method of Digit Control Machine Tool is single, and widespread practice is to pass through digital quantity Digital data is obtained by capture card, by analog acquisition card to analog data collection, and And without direct relatedness between the data of synchronization.

In the technology of foregoing description, while lathe multiaxis data acquisition, it is necessary to simultaneously to position, many sides Sensing data obtain, need external device to synchronize, cause data real-time of sampling Property is the highest.The position feedback information data such as same position many sides level sensor data and grating may be different Step.Current most of lathe except X, Y, Z tri-axle, three rotary shafts A, B, C, also can increase Add such as torque sensor, optical sensor, multiple sensing device such as temperature sensor, noise transducer, A kind of method that can simultaneously measure 6 passage digital quantities and 8 tunnels analogy amounts is proposed necessary.Knot The method provided in invention is provided, the synchronized sampling of analog quantity and digital quantity can be completed, and synchronize reliable, Method is easy, and real-time is high.

The invention discloses a new side about machine tool high speed course of processing parameter synchronization triggering collection Method.

Summary of the invention

It is an object of the invention to solve position, Digit Control Machine Tool many sides sensing data and obtain poor synchronization, position Triggering latch mode complicated, and the one proposed can be to 6 railway digital signals, 8 tunnel analogue signals synchronize Latch the synchronous data sampling method obtained

For achieving the above object, the technical measures that this programme uses are as follows:

Position, the many sides sensing data acquisition methods of a kind of Digit Control Machine Tool mainly obtains data source and includes simulation Signal and digital signal.Analog channel can realize 8 channel data synchronous acquisition, and digital channel is permissible Realizing 6 channel signal collections, the sample frequency of analogue signal is determined by trigger condition, digital signal frequency Being divided into two parts, Part I count frequency, Part II is upload frequencies.The counting of digital signal Frequency is not less than 10Mhz, and upload frequencies depends on trigger condition, and i.e. upload frequencies is equal to triggering frequency. Under the conditions of Ru Ci, digital signal and analogue signal synchronous acquisition can be realized.

As it is shown in figure 1, Digit Control Machine Tool many sides level sensor data capture method bag described in the invention Five peripheral hardware parts below having included: high speed AD module (AD7606), FPGA module, sheet modeling Block, ARM microprocessor module, USB transmission module.ARM microprocessor passes through FSMC bus Be connected with high speed AD module, ARM microprocessor by FSMC bus be connected with FPGA module, ARM microprocessor is connected with USB transmission module by FSMC bus, and the data between them are led to Letter mode is allocated by sheet modeling block, is primarily referred to as 74LS139 decoder and decodes address bus, When ARM microprocessor reads analog quantity from A/D module, address bus is decoded by 74LS139, choosing Middle A/D module, when ARM microprocessor reads digital quantity from FPGA module, 74LS139 is over the ground Location bus decoding, chooses FPGA module, when ARM microprocessor upload the data to host computer, Address bus is decoded by 74LS139, chooses USB transmission module, thus in the specific moment, sheet selects Module can realize the bridge that microprocessor is connected with each external function, and the utilization rate of such bus is maximum.

1, FPGA module includes six parallel channels, tunnel, counting module and trigger module, resets mould Block.Counting module completes normal signal filtering and collection.As it is shown in figure 5, filter circuit is by two D type flip flop forms, and is respectively designated as inst1 and inst2, and first d type flip flop inst1 latches pin The signal of A1, first d type flip flop signal is latched, then by second d type flip flop inst2 Two output signals with obtain final signal, burr can be removed by this process, filtering clutter.Touch Send out module to contain data buffer storage and compare with data, compared by data and impose a condition, it may be judged whether product Raw trigger condition.Dump block has reset signal to control with exterior I O, and arranging IO level is high level, Reset signal is effective, and after there is reset signal, the data within enumerator are cleared.If IO level For low level, reset signal is invalid, and enumerator internal data will not be cleared.

2, adc data modular converter can be simultaneously to eight tunnel analogue signal synchronized samplings.Concrete wiring When mode is as it is shown in fig. 7, outer triggering signal starts sampling, eight tunnel analogue signals start synchronized sampling, When sampling completes, the busy line of AD7607 chip produces high level notice arm processor and takes away Data, the conversion range of A/D module is controlled by the RANGE pin of AD7606 chip, if ARM Control RANGE is high level, and gathering voltage range is-5V～5V, if ARM controls RANGE Level is low level, and gathering voltage range is-10V to 10V.

3, ARM microprocessor module plays information relaying action, and information is divided into uplink information with descending Information, uplink information refers to the data of actual samples, and downlink information refers to the parameter that arranges of user, parameter bag Including triggering step pitch, sample frequency, AD conversion range, whether data filter, Protection Counter Functions.ARM Microprocessor processes carries out data and processes and data anticipation uplink information, then forwards.To descending letter Breath carries out unpacking rear unconditional forwarding, does not processes.

4, sheet modeling block plays rule arbitration effect.AB22, AB23 are connected by 74LS139 To FPGA module, A/D module, USB module, as shown in Figure 6, AB22, AB23 are FSMC Address wire, if AB22 is low, AB23 is low, then USB module is selected, its base address For 0x60000000；If AB22 is high, AB23 is low, then A/D module is selected, its base Location is 0x60800000, if AB22 is low, AB23 is high, then FPGA module is selected, its Base address is 0x61000000；Setting up multiple fifo module inside FPGA, it act as data buffer storage With accept buffering, by address wire AB20, AB19, AB18, AB17 introduce inside FPGA module, The selection of FIFO is realized through the cascade of two panels 74ls139.

Capture card accepts host computer user setup, and user walks by arranging the triggering of software design patterns capture card Away from or the triggered time.ARM controller is sent to arranging parameter inside FPGA module.ARM It is connected by bus with external equipment, reaches three time-multiplexed effects of peripheral hardware by bus-sharing. When a triggering condition is met, the triggering port in FPGA module can produce triggering pulse, this triggering arteries and veins Rush and have two effects, first: be connected with the conversion end of A/D module, can synchronize to trigger A/D module Extraneous analog quantity this moment is sampled.Second: trigger Pulse Width Control FPGA count internal module Data update in corresponding FIFO.A/D module passes through the micro-place of interrupt notification ARM after having converted Reason device obtains by the new data triggering pulses generation, ARM microprocessor acquirement analog quantity and digital quantity After data, (data of totally 14 passages) carry out rule constraint to data.If user passes through host computer Selecting data filtering function, analog signals can carry out preliminary shaping by smothing filtering to data. The most again by data packing transmission.If user selects initial data to upload, then initial data is uploaded.

Beneficial effects of the present invention: by by position, Digit Control Machine Tool many sides sensing data acquisition methods, permissible The positional information of each axle of Digit Control Machine Tool and sensing data are carried out one_to_one corresponding, through the party The coordination of the core ARM microprocessor in method, ARM microprocessor can accept to cache under host computer Data can be carried out various Filtering Processing while of internal, release host computer soft by the various instructions sent out The data processing pressure of part, the data so uploaded are i.e. actual at data measured.Not only simplify existing There is the method that in Digit Control Machine Tool test process, multichannel data obtains, solve existing data acquisition simultaneously The real time problems easily affected by upper computer software program during card synchronous acquisition and occur, due to the party The real-time of method is the best, measures for Digit Control Machine Tool and possesses wide significance with manufacture field.

Accompanying drawing explanation

Fig. 1 is the modular structure description figure of the present invention

Fig. 2 is the software flow pattern that in the present invention, microprocessor synergistic data processes

Fig. 3 be the present invention medium time sampling schematic diagram

Fig. 4 is the schematic diagram of equidistantly sampling in the present invention

Fig. 5 is the digital filter circuit figure in the present invention

Fig. 6 is that the sheet in the present invention selects module diagram

Fig. 7 is the A/D module connection figure in the present invention

Detailed description of the invention

Below in conjunction with the accompanying drawings and the present invention is described in further detail by specific embodiment.

A kind of Digit Control Machine Tool sensing data synchronizes latch method and includes when waiting sampling and equidistantly sample two kinds Pattern.The high speed AD module (AD7606) of foregoing description is responsible for synchronizing 8 tunnel analogue signals Gathering, sample frequency is determined by according to practical situation, and trigger signal source is under different mode of operations Variant, if when waiting under sampling configuration, trigger source is that FPGA internal clocking frequency dividing produces, if Under equidistant sampling configuration, then trigger source is that FPGA module compares generation.

People in the art is it will be understood that FPGA module is mainly to the similar encoder based on grating Signal counts, and count frequency is by FPGA module control, so the digital signal of input is two-way Square wave, and square wave possesses phase contrast 90 °.

Access data in substantial amounts of RAM district must be had inside ARM microprocessor, be responsible for data Buffering, it is to avoid the packet loss phenomenon that data send the most in time and occur.

FPGA module is responsible for counting 6 road code device signals, and No. 6 encoder A, B two believes Number enter after FPGA module, under the driving of same clock (this clock frequency is 10Mhz), to former Beginning signal is filtered, and 6 road signals synchronizes four segmentations and operates with sensing, then by 32 Count internal module count, once produce the numerical value of 6 32, the data of 6 passages be divided into 6 groups, bit wide is that the FIFO of 16bit is also classified into 6 groups, and often group FIFO includes that high-order FIFO is with low Position FIFO, first group of data can be divided into high 16 with low 16, be stored in first group by high 16 In the high-order FIFO of FIFO, in low 16 low level FIFO being stored in first group of FIFO, second group Data can be divided into high 16 with low 16, by high 16 the high-order FIFO being stored in second group of FIFO In, in low 16 low level FIFO being stored in second group of FIFO, the 3rd group of data can be divided into high by 16 Position is with low 16, and by high 16 the high-order FIFO being stored in the 3rd group of FIFO, low 16 are stored in In the low level FIFO of the 3rd group of FIFO, the 4th group of data can be divided into high 16 with low 16, will In high 16 high-order FIFO being stored in the 4th group of FIFO, low 16 are stored in the low of the 4th group of FIFO In the FIFO of position, the 5th group of data can be divided into high 16 with low 16, be stored in the 5th by high 16 In the high-order FIFO of group FIFO, in low 16 low level FIFO being stored in the 5th group of FIFO, the 6th Group data can be divided into high 16 with low 16, by high 16 the high-order FIFO being stored in the 6th group of FIFO In, in low 16 low level FIFO being stored in the 6th group of FIFO, last microprocessor is by 16 The numerical value that bus is successively read in FIFO is to public RAM district.

It is as follows that Digit Control Machine Tool many sides level sensor data syn-chronization latch acquisition methods possesses step:

Shown in Fig. 2, after microprocessor powers on, according to arranging the mode of operation of model selection system, soft Part triggers and hardware trigger pattern.

If working under software trigger pattern, trigger source, from the clock division within FPGA, divides Frequently coefficient is from ARM microprocessor, according to the clock after frequency dividing, trigger source at a fixed time between Compartment produces high impulse, and this impulsive synchronization triggers A/D module and FPGA internal data buffer module. Therefore the signal in two modules can realize synchronizing.

Divide ratio is transmitted to FPGA module by step 1:ARM microprocessor, and FPGA module is fixed Time produce 5V high impulse trigger, the frequency of this high impulse must immobilize, this be realize high accuracy adopt The benchmark of sample, this benchmark also serves as the discrete approximation continuous print foundation in step 5 simultaneously.The 5V produced The startup that pulse controls A/D module by the line 1 in Fig. 3 is sampled, and so can be pressed by analog signals Even time interval is sampled.

After step 2:AD module receives 5V pulse, complete 8 channel data samplings immediately, A sampling can be produced after data sampling completes and complete signal, this signal and ARM microprocessor mould Block is connected, as shown in Figure 3.

Step 3: microprocessor module is configured to external interrupt pattern, if A/D module has converted, then Trigger external interrupt.

Step 4: after microprocessor enters external interrupt, is read out the quantity produced in step 2, Disposably by the data of all passages by bus transfer to microprocessor internal RAM.

Step 5: then FPGA data is read out.Signal-count frequency in FPGA module is 10MHZ, the frequency triggering 5V high impulse is 10KHZ to the maximum, compares the conversion rate of A/D module, Count value can be approximately true continuous print signal, when high impulse produces, enumerator currency is sprung into FIFO caches, microcontroller by the data transmission that caches in advance to microprocessor internal RAM, time Between be spaced consistent with A/D module.

Step 6: the data being cached in internal RAM, microprocessor module is by FPGA in RAM Data are mated one by one with AD data, then according to appoint that form carries out data and uploads.Specifically Form: frame head+6 passage digital quantity+8 tunnels analogy amount+verification and, frame head is defined as 0x68,0x11, Verification and for transmit the cumulative of content and, the data determined whether again in microprocessor, according to The arbitration mechanism of sheet modeling block carries out upper sending out to data.So far, the flow process of a packet is complete.? Trigger under the promotion of high impulse, large batch of synchronous data sampling can be completed.

If processor is selected as hardware trigger pattern after powering on, then will be using a-road-through road as benchmark Trigger, be embodied as follows:

Assuming that triggering distance is set to N, first upper computer software passes through USB interface, N value is issued In microprocessor, when microprocessor receives the value of N, close all interruptions, N value is issued again Inside FIFO in FPGA module, counting channel 6 is chosen as benchmark.Benchmark mould in FPGA Block as shown in Figure 4, by the digital independent in FIFO to internal preset module.

After base modules accesses encoder, the currency in counting module can be transferred to benchmark mould Block, when count value forward updates once, and preset value increases by 1, and count value negative sense updates once, preset value Cutting 1, when preset value becomes 0 or is 2N, base modules produces one and triggers signal, the most pre- If value automatically becomes N to trigger next time.As shown in Figure 4, the line being numbered 1 in figure is synchronization Holding wire, synchronous signal line is connected with other counting modules simultaneously, although other modules can count, But if synchronous signal line does not produce high pulse signal, the count value of other grating module will not be locked Deposit, also will not reach in next stage structure.

Synchronous signal line, for triggering signal, also serves as A/D module as other road latch signals simultaneously Data start conversion signal.

So by triggering signal, same in same base modules between A/D module and FPGA module Position carries out the acquisition of data, and A/D module has converted rear data and sent into the micro-place of ARM by bus Reason device, the FPGA signal latched is read in internal RAM by ARM microprocessor simultaneously.

ARM microprocessor needs the most mutual with three peripheral hardwares, therefore data are passed by arbitration mechanism therein Send and start important effect.The core of sheet modeling block is arbitration mechanism, the chip selection signal pipe of three peripheral hardwares Foot receives the outfan of 74ls139, the input end grounding location line of 74ls139, then by address wire Level difference, it is possible to peripheral hardware is made a distinction, completes acquisition and the transmission of data.Microcontroller Have only to provide peripheral hardware address, just can carry out the selection of data channel.

Microprocessor passes through the line 3 in Fig. 3 respectively in the FIFO in A/D module data and FPGA Data move.

The module not specifically described in system of the present invention is mature modules of the prior art, because of Its specific implementation is not illustrated by this.

Above-described embodiment is only the present invention preferably embodiment, but embodiments of the present invention not office It is limited to this, the correction made under any spirit without departing from the present invention with principle, modifies, replace In generation, combine, simplify, all should be the substitute mode of equivalence, be included in protection scope of the present invention it In.

Claims (5)

1. a Digit Control Machine Tool multi-sensor data synchronizes latch method, it is characterised in that:

Obtain data source and include analogue signal and digital signal；Analog channel realizes 8 channel datas Synchronous acquisition, digital channel realizes 6 channel signal collections, and the sample frequency of analogue signal is by triggering Conditional decision, digital signal frequency is divided into two parts, Part I count frequency, and Part II is upper Pass frequency；The count frequency of digital signal is not less than 10Mhz, and i.e. upload frequencies is equal to triggering frequency；； The device applied includes high speed AD module, FPGA module, sheet modeling block, the micro-process of ARM Device module, USB transmission module；High speed AD module uses AD7606；ARM microprocessor Being connected with high speed AD module by FSMC bus, ARM microprocessor passes through FSMC bus Be connected with FPGA module, ARM microprocessor is connected with USB transmission module by FSMC bus Connecing, the data communication mode between them is allocated by sheet modeling block, i.e. 74LS139 decoder Address bus is decoded, when ARM microprocessor reads analog quantity from A/D module, 74LS139 Decoding address bus, choose A/D module, ARM microprocessor reads from FPGA module During digital quantity, address bus is decoded by 74LS139, chooses FPGA module, the micro-process of ARM When device upload the data to host computer, address bus is decoded by 74LS139, chooses USB transmission Module.

Method the most according to claim 1, it is characterised in that:

FPGA module includes six parallel channels, tunnel, counting module and trigger module, resets mould Block；Counting module completes normal signal filtering and collection；Filter circuit is by two d type flip flop groups Becoming, be respectively designated as inst1 and inst2, first d type flip flop inst1 latches the letter of pin A1 Number, first d type flip flop signal is latched by second d type flip flop inst2, so latter two Output signal with obtain final signal；Trigger module is compared by data and imposes a condition, it is judged that be No generation trigger condition；Dump block has reset signal to control with exterior I O, and arranging IO level is High level, reset signal is effective, and after there is reset signal, the data within enumerator are cleared； If IO level is low level, reset signal is invalid, and enumerator internal data will not be cleared.

Method the most according to claim 1, it is characterised in that:

When outer triggering signal starts sampling, eight tunnel analogue signals start synchronized sampling, when having sampled The busy line of Cheng Shi, AD7607 chip produces high level notice arm processor and takes data away, The conversion range of A/D module is controlled by the RANGE pin of AD7606 chip, if ARM control RANGE processed is high level, and gathering voltage range is-5V～5V, if ARM controls RANGE Level is low level, and gathering voltage range is-10V to 10V.

Method the most according to claim 1, it is characterised in that:

ARM microprocessor module information is divided into uplink information and downlink information, and uplink information refers to reality The data of border sampling, downlink information refers to the parameter that arranges of user, and parameter includes triggering step pitch, sampling Frequency, AD conversion range, whether data filter, Protection Counter Functions；It is right that ARM microprocessor processes Uplink information carries out data and processes and data anticipation, then forwards；After downlink information is unpacked Unconditional forwarding, does not processes.

Method the most according to claim 1, it is characterised in that:

AB22, AB23 are connected to FPGA module, A/D module, USB by 74LS139 Module, AB22, AB23 are the address wires of FSMC, if AB22 is low, AB23 is low, Then USB module is selected, and its base address is 0x60000000；If AB22 is high, AB23 For low, then A/D module is selected, and its base address is 0x60800000, if AB22 is low, AB23 is high, then FPGA module is selected, and its base address is 0x61000000；Inside FPGA Setting up multiple fifo module, it act as data buffer storage and accepts buffering, by address wire AB20, AB19, AB18, AB17 introduce inside FPGA module, realize through the cascade of two panels 74ls139 The selection of FIFO.