CN104536330A - Data communication device for absolute value encoder with SSI - Google Patents
Data communication device for absolute value encoder with SSI Download PDFInfo
- Publication number
- CN104536330A CN104536330A CN201410637666.8A CN201410637666A CN104536330A CN 104536330 A CN104536330 A CN 104536330A CN 201410637666 A CN201410637666 A CN 201410637666A CN 104536330 A CN104536330 A CN 104536330A
- Authority
- CN
- China
- Prior art keywords
- data
- absolute value
- register
- value encoder
- ssi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Communication Control (AREA)
Abstract
The invention relates to a data communication device for an absolute value encoder with SSI, relating to digital processing units used in program control systems. A DSP controller, a program processing module, a PA port, a 4*4 matrix keyboard, an SPI module, a level conversion chip, an RS422 differential level standard transceiver and an SSI absolute value encoder are included. The level converting chip 74ALVC164245, the RS422 differential level standard transceiver MAX490CPA and the 4*4 matrix keyboard are added to the TMS320LF2407 type DSP controller embedded with the SPI module to realize data connection of the SSI encoder; and the defects that in the prior art, the SSI communication module is high in the cost, oscillation and burrs tend to occur during port level jump, realization is relatively complex, and the communication speed is not easy to control are overcome.
Description
Technical field
Technical scheme of the present invention relates to the digital processing unit that program control system uses, specifically for the device of SSI interface absolute value encoder data communication.
Background technology
In recent years, automation control system constantly advances, and requires the surveying instrument of more high-precision absolute value encoder as angle and straight-line displacement.In order to address this need, need the resolution improving scrambler, which adds figure place and the cable core number of scrambler, thus increase installation cost and easily occur mistake, in order to effectively solve this contradiction, SSI interface arises at the historic moment.SSI interface is the desired communication interface that absolute value encoder carries out data transmission, there is installation cost few, the advantage that circuit simplifies, it only need by two paths of signals line, i.e. clock cable and data signal line, adopt serial communication mode to transmit angle and the linear displacement signal of absolute value encoder, the precision figure place of cable number and scrambler has nothing to do.There is following defect in existing SSI interface communication module in the market: one is, expensive, and the SM338's of such as Siemens Company is expensive; Two are, have scholar to adopt the I/O mouth level of DSP to overturn the communication sequential simulated and produce SSI interface, concussion and burr easily appear in the program when port level saltus step, realize comparatively complicated, and traffic rate are wayward.
Summary of the invention
Technical matters to be solved by this invention is: the device being provided for the data communication of SSI interface absolute value encoder, adopt an additional level conversion core 74ALVC164245 on the TMS320LF2407 type dsp controller basis of embedded SPI module, the transceiver MAX490CPA of RS422 differential level standard and 4X4 matrix keyboard realize and the data communication of SSI interface encoder, the SSI interface communication module overcoming prior art exists expensive and easily occurs concussion and burr when port level saltus step, realize comparatively complicated, and the uppity defect of traffic rate.
The present invention solves this technical problem adopted technical scheme: for the device of SSI interface absolute value encoder data communication, comprises dsp controller, routine processes module, PA mouth, 4X4 matrix keyboard, SPI module, level transferring chip, the transceiver of RS422 differential level standard and SSI interface absolute value encoder, wherein, dsp controller, level transferring chip, 4X4 matrix keyboard, circuit connecting mode between the transceiver of RS422 differential level standard and SSI interface absolute value encoder five modules is: the key assignments information of 4X4 matrix keyboard setting enters dsp controller through PA mouth, to level transferring chip, to send high level be the clock pulse signal SPICLK of 3.3V and width to SPI module is the low level pulse signal of 2ms, level transferring chip is the location data signal of 3.3V to SPI module input high level, level transferring chip sends to the transceiver of RS422 differential level standard the clock pulse signal SPICLK that high level is 5V, the transceiver of RS422 differential level standard then to level transferring chip input high level be the location data signal of 5V, clock pulse signal SPICLK+ and SPICLK-of two-way complementation inputs SSI interface absolute value encoder by the transceiver of RS422 differential level standard, the position data D ATA+ of the difference form in SSI interface absolute value encoder and DATA-is by the transceivers of RS422 differential level standard, in addition, SPI module, routine processes module and PA mouth are embedded in dsp controller.
The above-mentioned device for the data communication of SSI interface absolute value encoder, described dsp controller is TMS320LF2407 type, described level transferring chip is 74ALVC164245 type, the transceiver of described RS422 differential level standard is the difference transponder chip MAX490CPA of standard, 0-9 in described 4X4 matrix keyboard amounts to the different traffic rate of 10 digitized representations 10 kinds, to represent successively from 100KHZ at interval of 100KHZ until 1MHZ.
The above-mentioned device for the data communication of SSI interface absolute value encoder, described in the IOPA0 to IOPA7 of PA mouth that is embedded in dsp controller be set to general I/O port.
The above-mentioned device for the data communication of SSI interface absolute value encoder, described SPI module is sixteen bit register, and this SPI module comprises principal and subordinate's working mode selection register, data register, data length control register, receives buffer register, traffic rate control register, clock polarity register and clock phase register, wherein, the system clock frequency CLKOUT signal of dsp controller, the frequency of operation needed for scrambler is reached through traffic rate control register frequency division, the SPIBRR=79 of traffic rate control register is made namely to meet the demands, and the time clock of time delay negative edge is obtained by arranging clock polarity register and clock phase register, setting principal and subordinate working mode selection register is aggressive mode, SPICTL register second SPICTL.2=1 is made to meet the demands, under active work mode, position data enters SPI module through SPISOMI pin, because scrambler is individual pen absolute value 12 precision, 12 bit data need be transmitted, time clock needs 13 negative edges and rising edge: first negative edge is for activating monostable circuit, rear 12 negative edges read 12 position datas for spi bus, front 12 rising-edge encoder outwards send data, last rising edge makes data signal line become low level, therefore, need setting data cut to lengthen register transfer 13 characters, the 3rd, SPICCR register is made to meet the demands to zero-bit SPICCR.3 ~ SPICCR.0=1100, after above-mentioned setting, under the effect of SPI module clock pulse signal SPICLK, the position data that position coder is sent enters into data register through SPISOMI pin, when all figure places of position data all transmit complete, this position data just enters into and receives buffer register, follow-up data processing is carried out for dsp controller.
The above-mentioned device for the data communication of SSI interface absolute value encoder, has spi bus sequential in described SPI module, and this spi bus is made up of clock cable and SPICLK and driven output/active input line and SPISOMI.
The above-mentioned device for the data communication of SSI interface absolute value encoder, the described SPI module mode be embedded in dsp controller is the zero setting signal ZERO of general I/O mouth function as SSI absolute value encoder of 30 pin using dsp controller, the system clock frequency of dsp controller delivers to SPI module by inner CLKOUT pin, and the reception buffer register of dsp controller by SPI inside modules and the data interaction of the realization of transmission buffer register and SPI module.
The above-mentioned device for the data communication of SSI interface absolute value encoder, the parts wherein related to and components and parts are all by commercially available.
The invention has the beneficial effects as follows: compared with prior art, outstanding substantive distinguishing features of the present invention is as follows:
(1) the present invention adopts SPI module to realize the data communication of SSI interface encoder for the device of SSI interface absolute value encoder data communication, this is brand-new technology, need to carry out strict configuration to SPI module, there are many registers also to need configuration, have some deviations all cannot realize data acquisition (namely communicating);
(2) the present invention is used for the embedded SPI module of device employing dsp controller of SSI interface absolute value encoder data communication, produce the communication sequential of spi bus interface through corresponding register software configuration simulation, realize SSI interface absolute value encoder data acquisition communication by succinct hardware configuration; By the I/O interface of dsp controller, zero-setting operation is carried out to SSI interface absolute value encoder position data; And complete Gray code with succinct program to change to scale-of-two code system; Different traffic rates is set by the button in 4X4 matrix keyboard, accurately and reliably realizes the communication of SSI interface absolute value encoder placement data acquisition.
(3) having spi bus sequential in the SPI module of the present invention for the device of SSI interface absolute value encoder data communication is: 1) during idle condition, and clock cable can be high level also can be low level; 2) when carrying out data transmission, namely starting the transmission of data-signal at the rising edge of first time clock or negative edge, there is not the situation that monostable circuit is activated; 3) when data lowest order transmits complete, the level time maintaining clock cable is not needed to be greater than the transmission that monostable time has carried out a signal.Thus SPI communication protocol comparatively SSI agreement arrange flexibly, SSI interface encoder communication sequential can be produced by arranging spi bus interface corresponding registers simulate.
(4) clock pulse signal required when clock cable and SPICLK are for providing SSI absolute value encoder to work, driven output/active input and SPISOMI signal wire are used for the outside launching position data of this SSI absolute value encoder, and make the spi bus of work in the active mode in SPI module read the position signalling data of this SSI absolute value encoder.
(5) the present invention produces clock pulse signal in an active mode for the embedded SPI module of dsp controller of the device of SSI interface absolute value encoder data communication, this signal obtains by differential level chip the differential clocks pulse signal that a road has longer transmission distance and strong anti-interference ability, be injected on differential clocks pin required when SSI absolute value encoder works, SSI absolute value encoder is coaxially connected with rotor, just the position data of differential type is delivered to after level difference chip synthesizes single-ended location data signal the driven output/active input pin of SPI module, read and subsequent treatment for dsp controller.
(6) the present invention realizes comprising amounting to 10 kinds of traffic rates at interval of 100KHZ to 1MHZ from 100KHZ by the button in 4X4 matrix keyboard for the device of SSI interface absolute value encoder data communication.
(7) the present invention is used for the level form of I/O mouth by high-low-high of the device employing dsp controller of SSI interface absolute value encoder data communication, be the pulse signal of 2ms to a duration of SSI absolute value encoder, position data current for SSI absolute value encoder is set to zero, thus realizes zero-setting operation.
(8) the present invention is used for the device of SSI interface absolute value encoder data communication is realize code system conversion for the binary numeration system form of numerical evaluation and control by the Gray code numeral system formal transformation of intrinsic for SSI absolute value encoder output.
Compared with prior art, marked improvement of the present invention is as follows:
(1) the present invention is used for the with low cost of the device of SSI interface absolute value encoder data communication, compared with the prior art as following table:
(2) the present invention adopts the embedded SPI module of dsp controller to realize the data acquisition of SSI interface encoder through corresponding configuration for the device of SSI interface absolute value encoder data communication, with dsp controller parallel processing, save the processing time, improve processing power, add the dirigibility of data acquisition.
(3) the present invention is wide for the traffic rate scope of the device of SSI interface absolute value encoder data communication, and traffic rate is high, meet the requirement of Industry Control real-time, and can conveniently realize on-line setup traffic rate by 4X4 matrix keyboard, compared with the prior art adopting I/O mouth method for turning to realize communicating, during change traffic rate, operate very easy, data acquisition is more flexible, and what adopt for the device of SSI interface absolute value encoder data communication due to the present invention is that integration module SPI realizes, during low and high level saltus step, concussion burr is less, its communication stability overturns mode higher than I/O.
(4) the present invention be used for the device of SSI interface absolute value encoder data communication can realize scrambler at an arbitrary position under zero-setting operation, without the need to carrying out dismounting mechanically to realize calibration operation, reduce the fussy degree of engineering, can effectively increase work efficiency.
Accompanying drawing explanation
Below in conjunction with drawings and Examples, the present invention is further described.
Fig. 1 is the formation schematic block diagram of the present invention for the data communication of SSI interface encoder.
Fig. 2 is the internal simplified structure schematic block diagram of the present invention for the SPI module of the device of SSI interface absolute value encoder data communication.
Fig. 3 is the integrated connection circuit diagram of the present invention for the device of SSI interface absolute value encoder data communication.
Fig. 4 is the whole system operational scheme schematic diagram of the present invention for the device of SSI interface absolute value encoder data communication.
Fig. 5 is the spi bus interface communication time diagram of the present invention for the device of SSI interface absolute value encoder data communication.
Fig. 6 is the SSI interface communication time diagram of the present invention for the device of SSI interface absolute value encoder data communication.
Fig. 7 encoder position data waveform figure that to be the present invention gather for the device of SSI interface absolute value encoder data communication.
Fig. 8 is that the present invention takes the position data oscillogram after zero-setting operation for the SSI interface absolute value encoder in the device of SSI interface absolute value encoder data communication.
Fig. 9 is the comparison diagram of the position data waveform that the position data waveform that gathers for the device of SSI interface absolute value encoder data communication and prior art adopt I/O mouth method for turning to gather.
In figure, 1.DSP controller, 2. routine processes module, 3.PA mouth, 4.4X4 matrix keyboard, 5.SPI module, 6. level transferring chip, 7.RS422 the transceiver of differential level standard, 8.SSI interface absolute value encoder, 9. key assignments information, the data of 10.PA mouth 3, 11. initial configuration, 12. code system conversions, 13. high level are the clock pulse signal SPICLK of 3.3V, 14. high level is the location data signal of 3.3V, 15. width are the low level pulse signal of 2ms, 16. high level are the clock pulse signal SPICLK of 5V, 17. high level is the location data signal of 5V, 18.5V level signal, the position data D ATA+ of 19. difference form and DATA-, clock pulse signal SPICLK+ and SPICLK-of 20. two-way complementations, 21. principal and subordinate's working mode selection registers, 22. data registers, 23. data length control registers, 24. receive buffer register, 25. traffic rate control registers, 26. clock polarity registers, 27. clock phase registers.
Embodiment
Embodiment illustrated in fig. 1ly to show, for the device of SSI interface absolute value encoder data communication, comprise dsp controller 1, routine processes module 2, PA mouth 3,4X4 matrix keyboard 4, SPI module 5, level transferring chip 6, the transceiver 7 of RS422 differential level standard and SSI interface absolute value encoder 8, wherein, dsp controller 1, level transferring chip 6, 4X4 matrix keyboard 4, circuit connecting mode between the transceiver 7 of RS422 differential level standard and SSI interface absolute value encoder 8 five modules is: the key assignments information 9 that 4X4 matrix keyboard 4 sets enters dsp controller 1 through PA mouth 3, SPI module 5 sends to level transferring chip 6 the low level pulse signal 15 that clock pulse signal SPICLK13 that high level is 3.3V and width are 2ms, level transferring chip 6 is the location data signal 14 of 3.3V to SPI module 5 input high level, level transferring chip 6 sends to the transceiver 7 of RS422 differential level standard the clock pulse signal SPICLK16 that high level is 5V, the transceiver 7 of RS422 differential level standard is the location data signal 17 of 5V to level transferring chip 6 input high level, level transferring chip 6 injects the level signal 18 of 5V to SSI interface absolute value encoder 8, clock pulse signal SPICLK+ and SPICLK-20 of two-way complementation inputs SSI interface absolute value encoder 8 by the transceiver 7 of RS422 differential level standard, the position data D ATA+ of the difference form in SSI interface absolute value encoder 8 and DATA-19 is received by the transceiver 7 of RS422 differential level standard, in addition, SPI module 5, routine processes module 2 and PA mouth 3 are embedded in dsp controller 1.
Further illustrate as follows: the IOPA0 to IOPA7 of the PA mouth 3 in dsp controller 1 is set to general I/O port, 0-9 in 4X4 matrix keyboard 4 amounts to the different traffic rate of ten digitized representations ten kinds, represent successively from 100KHZ at interval of 100KHZ to 1MHZ, the key assignments information 9 set by 4X4 matrix keyboard 4 enters dsp controller 1 through PA mouth 3, the routine processes module 2 of its inside completes following three main tasks altogether: (a) reads the data 10 of PA mouth 3, and determine the traffic rate of setting accordingly, b () carries out initial configuration 11 according to the traffic rate of setting and the configuration information of SPI module 5 to SPI module 5, c location data signal 14 that () SPI module 5 is 3.3V from the high level that level transferring chip 6 collects will be stored into the reception buffer register 24 of Fig. 2, correct location data signal is obtained by the filtering of multi collect laggard line program, its position data is 12, first mask and receive the highest four of buffer register 24, low 12 bit data are correct position data, this position data is the data of gray code format, it does not numerically have size implication, be unfavorable for numerical evaluation, therefore the Gray code needing to be carried out SPI module 5 enters routine processes module 2 to the code system conversion 12 of binary code, concrete grammar is: following three the succinct C programmer write can realize this function: For (i=0, i<11, i++) { C=Gray & (0X0800>>i), Gray=Gray^ (C>>1), Binary=Gray, 12 absolute value encoders that the present embodiment adopts, can realize through ten for loop statements, amendment cycle index can meet the code system conversion 12 of not isotopic number, Gray is 12 position datas that scrambler is sent, and Binary is the binary location data obtained after code system conversion 12.After configuring SPI module 5, the gatherer process that high level is the location data signal 14 of 3.3V can be started, the high level that SPI module 5 sends is the clock pulse signal SPICLK 13 of 3.3V, the clock pulse signal SPICLK 16 that high level is 5V is converted thereof into by level transferring chip 6, high level is the clock pulse signal SPICLK 16 of 5V is become two-way complementation after the transmitting terminal of the transceiver 7 of RS422 differential level standard clock pulse signal SPICLK+ and SPICLK-20 by difference, this signal is finally input in SSI interface absolute value encoder 8, under the effect of clock pulse signal SPICLK+ and SPICLK-20 of two-way complementation, the position data D ATA+ of the difference form in SSI interface absolute value encoder 8 and DATA-obtains the location data signal 17 that a road high level is 5V after the receiving end of the transceiver 7 of RS422 differential level standard, high level is the location data signal 14 that the location data signal 17 of 5V is converted into that after level transferring chip 6 high level is 3.3V, high level is that the location data signal 14 of 3.3V enters SPI module 5, position data process described in 3rd step of then carrying out said procedure processing module 2.In addition, by the zero-bit that can realize easily will obtaining in engineer applied to the zero-setting operation of SSI interface absolute value encoder 8, and without the need to carrying out the troublesome operation such as dismounting mechanically, a basic I/O the mouth of dsp controller 1 is adopted at this, by program make it produce low level pulse signal 15 that a width is 2ms, width is the level mode that the low level pulse signal 15 of 2ms is similarly 3.3V, convert thereof into the level signal 18 of 5V through level transferring chip 6, be then injected in SSI interface absolute value encoder 8 and complete zero-setting operation.
Embodiment illustrated in fig. 2ly show, the SPI module that the present invention is used for the device of SSI interface absolute value encoder data communication comprises principal and subordinate's working mode selection register 21, data register 22, data length control register 23, receives buffer register 24, traffic rate control register 25, clock polarity register 26 and clock phase register 27, wherein, the system clock frequency CLKOUT signal of dsp controller, the frequency of operation needed for scrambler is reached through traffic rate control register 25 frequency division, the SPIBRR=79 of traffic rate control register 25 is made namely to meet the demands, and the time clock of time delay negative edge is obtained by arranging clock polarity register 26 and clock phase register 27, setting principal and subordinate working mode selection register 21 is aggressive mode, SPICTL register second SPICTL.2=1 is made to meet the demands, under active work mode, position data SPISOMI pin in figure enters SPI module, because scrambler is individual pen absolute value 12 precision, 12 bit data need be transmitted, time clock needs 13 negative edges and rising edge: first negative edge is for activating monostable circuit, rear 12 negative edges read 12 position datas for spi bus, front 12 rising-edge encoder outwards send data, last rising edge makes data signal line become low level, therefore, setting data cut to lengthen register 23 is needed to transmit 13 characters, the 3rd, SPICCR register is made to meet the demands to zero-bit SPICCR.3 ~ SPICCR.0=1100, after above-mentioned setting, under the effect of SPI module clock pulse signal SPICLK, the position data that position coder is sent enters into data register 22 through SPISOMI pin, when all figure places of position data all transmit complete, this position data just enters into and receives buffer register 24, follow-up data processing is carried out for dsp controller.Described SPI module is sixteen bit register, and above-mentioned scrambler is German fort alliance, BMSH-58S1G24C12.
Further illustrate as follows: in figure, CLKOUT is the clock frequency of dsp controller 1, for 40MHZ, be 500KHZ at the traffic rate of this SSI interface absolute value encoder 8, CLKOUT signal is reached frequency of operation needed for SSI interface absolute value encoder 8 through traffic rate control register 25 frequency division, the SPIBRR=79 of traffic rate control register 25 is made to meet the demands, and the time clock of time delay negative edge is obtained by arranging clock polarity register 26 and clock phase register 27, make the 6th SPICCR.6=1 of clock polarity register 26, 3rd SPICTL.3=1 of clock phase register 27 meets the demands.SPI module 5 works in aggressive mode, as dsp controller to the pulse of SSI interface absolute value encoder 8 tranmitting data register, setting principal and subordinate working mode selection register 21 is aggressive mode, the second SPICTL.2=1 of principal and subordinate's working mode selection register is made to meet the demands, under active work mode, high level is that location data signal 14 SPISOMI pin in figure of 3.3V enters SPI module 5, SSI interface absolute value encoder 8 in the present embodiment is German fort alliance, BMSH-58S1G24C12, individual pen absolute value 12 precision, 12 bit data need be transmitted, time clock needs 13 negative edges and rising edge: first negative edge is for activating monostable circuit, rear 12 negative edges read 12 position datas for spi bus, front 12 rising edge SSI interface absolute value encoders 8 outwards send data, last rising edge makes data signal line become low level, therefore, setting data cut to lengthen register 23 is needed to transmit 13 characters, the 3rd of data length control register 23 the to the 0th SPICCR.3 ~ SPICCR.0=1100 is made to meet the demands, after above-mentioned setting, in SPI module 5 under the effect of clock pulse signal SPICLK, the position data that SSI interface absolute value encoder 8 is sent enters into data register 22 through SPISOMI pin, after all figure places of position data are all sent to data register 22, this position data just enters into and receives buffer register 24, follow-up data processing is carried out for dsp controller 1.
When carrying out multi collect to reduce measuring error to same position signal, need to add a time delay between the time clock string needed for twice collection, delay time must be greater than monostable time and t
m, the unit interval is set to herein
(α is the traffic rate of spi bus), namely delay time must be greater than 20+1=21us, namely high to make data signal line level return, thus realizes this position signal acquisition, and prepares to carry out next signals collecting.
Embodiment illustrated in fig. 3ly to show, the integrated connection circuit that the present invention is used for the device of SSI interface absolute value encoder data communication comprises dsp controller 1 module U1, level transferring chip 6 module U2,4X4 matrix keyboard 4 module U3, the transceiver 7 module U4 of RS422 differential level standard and SSI absolute value encoder 8 module U5; Wherein, dsp controller 1 module U1 uses the TMS320LF207A of TI company, system clock frequency is 40MHZ, IOPA0 to the IOPA7 of PA mouth 3 is used to amount to 8 I/O mouths as 4X4 matrix keyboard 4 input port X1, X2, X3, X4.Y1, Y2, Y3, Y4, uses the basic function SPICLK of 35 pin of the dsp controller 1 and basic function SPISOMI of 32 pin as the time clock transmitting terminal of SPI module 5 and position data receiving end, uses the zero setting signal ZERO of general I/O mouth function as SSI absolute value encoder 8 of 30 pin of dsp controller 1.Level transferring chip 6 module U2 is the 74ALVC164245 of TI company, 3.3V voltage signal in dsp controller 1 module U1 and the 5V voltage signal in peripheral hardware are carried out two-way level conversion, wherein 7, 8 pin VCC (5V) and 31, 42 pin VCC (3.3V) are required voltage during this chip operation, supply 5V and 3.3V respectively, this chip has two groups of ALT-CH alternate channels, respectively by 1OE, 1DIR and 2OE, 2DIR controls, passage 1 is changed to 5V for realizing 3.3V, namely A changes to B direction, 1OE is set low level, enable 1 channel operation, and position, direction 1DIR is set high level and realize A and change to B direction, 35 pin SPICLK now in dsp controller 1 module U1 and 30 pin ZERO are 5V level standard after being changed to 1B1 and 1B2 by 1A1 and 1A2 of this level transferring chip 6, passage 2 is changed to 3.3V for realizing 5V, 2OE is set low level, this passage capable of being is operated, and position, direction 2DIR is set low level and realize B and change to A direction, the position signalling XSPISOMI received through the transceiver 7 of RS422 differential level standard to be converted to 3.3V to 2A1 level signal SPISOMI by the 2B1 of passage 2 for 32 pin of dsp controller 1 module U1 as input.4X4 matrix keyboard 4 module U3 comprises 8 pin X1, X2, X3, X4.Y1, Y2, Y3, Y4, X1 to X4 is as the row input of 4X4 matrix keyboard 4, Y1 to Y4 is the MAX490CPA chip of MAXIM company as the transceiver 7 module U4 of the row input .RS422 differential level standard of 4X4 matrix keyboard 4, the traffic rate of maximum support 2.5MHZ, to be input in SSI absolute value encoder 8 after level transferring chip Hou mono-road clock pulse signal XSPICLK difference is clock pulse signal CLOCK+ and CLOCK-20 of two-way complementation, the position data D ATA+ of the two-pass DINSAR form simultaneously sent by SSI absolute value encoder 8 and DATA-19 synthesizes a road location data signal XSPISOMI, in addition between power supply+5V and GND and on a capacitance be the electrochemical capacitor of 100uf, to reach the effect of voltage regulation filtering.SSI absolute value encoder 8 module U5 is the BMSH-58S1G24C12 of German Bao Meng company, this SSI absolute value encoder 8 is individual pen absolute value formula, the SSI interface encoder of 12 precision, have 7 signal wires, wherein two power leads (+24V, SGND), 24V powers, clock cable CLOCK+ and CLOCK-of two difference form, location data signal line DATA+ and DATA-of two difference form, this SSI absolute value encoder 8 frequency response range is 100KHZ to 1MHZ.
Embodiment illustrated in fig. 4ly show, the whole system operational scheme that the present invention is used for the device of SSI interface absolute value encoder data communication is:
Beginning → DSP controls its initialization, button arranges traffic rate → configuration SPI module corresponding registers → enable SPI module, communicate with SSI interface encoder, collection position data → reach times of collection?---be → dsp controller in carry out program filtering and code system is changed → terminated;---does is no → interval time greater than monostable time?---be → then return and enable SPI module, communicate with SSI interface encoder, collection position data;---does is no → wait → interval time greater than monostable time?
Above-mentioned " wait " refers to until satisfy condition, and then enters and enables SPI module, communicates with SSI interface encoder, collection position data, until reach times of collection, carries out program filtering and code system is changed in dsp controller, to all terminating.
Fig. 5 shows the spi bus interface communication sequential of the present invention for the device of SSI interface absolute value encoder data communication, in figure, SPICLK periodicity is the continuous clock pulse that SPI module 5 sends, in figure, A, B, C, D for SPI module 5 provide for user configured four kinds of different mode of operations, be described as follows:
A () A is without time delay rising edge mode, represent that SPI module 5 sends data at the rising edge of time clock SPICLK, receive data at the negative edge of time clock SPICLK;
B () B represents for there being time delay rising edge mode, the half period of SPI module 5 before the rising edge of time clock SPICLK sends data, receives data at the rising edge of time clock SPICLK;
C () C is without time delay negative edge clock mode, represent that SPI module 5 sends data at the negative edge of time clock SPICLK, receive data at the rising edge of time clock SPICLK;
D () D is for there being time delay negative edge clock mode, the half period of SPI module 5 before the negative edge of time clock SPICLK sends data, receives data at the negative edge of time clock SPICLK;
E () SPISIMO is spi bus driven input/active output pin, on the contrary, SOMI is spi bus initiatively input/driven output pin, that is, when SPI module 5 works in active mode, SPISIMO is data output pins, SPISOMI is data-out pin, when SPI module 5 works in slave state, SPISOMI is data output pins, and SPISIMO is data-out pin.
According to the communication succession of SSI interface, during requirement communication idle, clock cable is high level, in the rising edge launching position data of time clock during communication, and now data are not stablized, therefore SPI module 5 clock pulse signal should time delay half period, read in position data when negative edge, should require that SPI module 5 has worked in time delay negative edge accordingly, thus produce the correct communication sequential needed for SSI absolute value encoder 8.In the present embodiment, SPI module 5 works in aggressive mode, then use SPISOMI pin to receive pin as the position data collected.
Fig. 6 shows the SSI interface communication sequential of the present invention for the device of SSI interface absolute value encoder data communication, CLOCK clock signal needed for SSI interface communication in figure, DATA is the position data (bit n...bit 1) that SSI absolute value encoder 8 is sent, T is the cycle of pulse, t
mfor the monostable time, which determine the minimum time interval that twice, front and back placement data acquisition should possess, under the effect of continuous clock pulse CLOCK, position data D ATA is sent at the rising edge of each time clock CLOCK, send successively by high-order bit n, until send lowest order bit1, then data line returns high level automatically, completes a placement data acquisition.
Fig. 7 shows the encoder position data waveform that the present invention gathers for the device of SSI interface absolute value encoder data communication, top is clock pulse signal waveform, amount to 13 rising edges and 13 negative edges, bottom is 12 position datas that random site is adopted, can see that this position data is: 010111001101: when zero-setting operation is carried out in this position, dsp controller 1 exports by its PA0 mouth 3 the low level pulse signal that a duration is 2ms, realizes operation current location being carried out zero setting.
Fig. 8 shows the present invention and takes the position data oscillogram after zero-setting operation for the SSI interface absolute value encoder in the device of SSI interface absolute value encoder data communication, and after zero-setting operation, 12 position datas are all zero.
Adopt a basic I/O mouth of dsp controller 1, make it produce low level pulse signal 15 that a width is 2ms, width is the low level pulse signal 15 of 2ms, it is the level mode of 3.3V, the level signal 18 of 5V is converted thereof into through level transferring chip 6, then be injected in SSI interface absolute value encoder 8 and complete zero-setting operation, after zero-setting operation, high level is that 12 position datas in the location data signal 14 of 3.3V are 0, under the effect of time clock, this position data is outwards sent successively from a high position to low level.
Fig. 9 shows the comparison diagram of position data waveform that the device for the data communication of SSI interface absolute value encoder gathers and the position data waveform that prior art adopts I/O mouth method for turning to gather, the oscillogram of the A position data that to be the present invention gather for the device of SSI interface absolute value encoder data communication in figure, B is that prior art adopts I/O mouth level upset simulation SSI communication timing method oscillogram, the waveform of position data that the present invention is used for the device collection of SSI interface absolute value encoder data communication shakes little when being presented at level saltus step, burr is few, more be conducive to the suppression of the stable of position data and site error.In addition compared to the position data waveform that prior art adopts I/O mouth method for turning to gather, the traffic rate adopting the present invention to be used for the position data of the device collection of SSI interface absolute value encoder data communication can easily realize regulating by configuration register value exactly.
Embodiment 1
According to the device for the data communication of SSI interface absolute value encoder of Fig. 1, Fig. 2 and composition the present embodiment embodiment illustrated in fig. 3, comprise dsp controller 1, routine processes module 2, PA mouth 3,4X4 matrix keyboard 4, SPI module 5, level transferring chip 6, the transceiver 7 of RS422 differential level standard and SSI interface absolute value encoder 8.Wherein dsp controller 1 is TMS320LF2407 type, level transferring chip 6 is 74ALVC164245 type, the transceiver 7 of RS422 differential level standard is the difference transponder chip MAX490CPA of standard, 0-9 in 4X4 matrix keyboard 4 amounts to the different traffic rate of 10 digitized representations 10 kinds, to represent successively from 100KHZ at interval of 100KHZ until 1MHZ, the IOPA0 to IOPA7 being embedded in the PA mouth 3 in dsp controller 1 is set to general I/O port, SPI module 5 comprises principal and subordinate's working mode selection register 21, data register 22, data length control register 23, receive buffer register 24, traffic rate control register 25, clock polarity register 26 and clock phase register 27, there is in SPI module 5 spi bus sequential, this spi bus is made up of clock cable and SPICLK and driven output/active input line and SPISOMI, SPI module 5 mode be embedded in dsp controller 1 is the zero setting signal ZERO of general I/O mouth function as SSI absolute value encoder 8 of 30 pin using dsp controller 1, the system clock frequency of dsp controller 1 delivers to SPI module 5 by CLKOUT pin, and the reception buffer register 24 of dsp controller 1 by SPI module 5 inside and the data interaction of the realization of transmission buffer register 25 and SPI module 5.
The parts related in above-described embodiment and components and parts are all by commercially available.
Claims (6)
1. for the device of SSI interface absolute value encoder data communication, it is characterized in that: comprise dsp controller, routine processes module, PA mouth, 4X4 matrix keyboard, SPI module, level transferring chip, the transceiver of RS422 differential level standard and SSI interface absolute value encoder, wherein, dsp controller, level transferring chip, 4X4 matrix keyboard, circuit connecting mode between the transceiver of RS422 differential level standard and SSI interface absolute value encoder five modules is: the key assignments information of 4X4 matrix keyboard setting enters dsp controller through PA mouth, to level transferring chip, to send high level be the clock pulse signal SPICLK of 3.3V and width to SPI module is the low level pulse signal of 2ms, level transferring chip is the location data signal of 3.3V to SPI module input high level, level transferring chip sends to the transceiver of RS422 differential level standard the clock pulse signal SPICLK that high level is 5V, the transceiver of RS422 differential level standard then to level transferring chip input high level be the location data signal of 5V, clock pulse signal SPICLK+ and SPICLK-of two-way complementation inputs SSI interface absolute value encoder by the transceiver of RS422 differential level standard, the position data D ATA+ of the difference form in SSI interface absolute value encoder and DATA-is by the transceivers of RS422 differential level standard, in addition, SPI module, routine processes module and PA mouth are embedded in dsp controller.
2. according to claim 1 for the device of SSI interface absolute value encoder data communication, it is characterized in that: described dsp controller is TMS320LF2407 type, described level transferring chip is 74ALVC164245 type, the transceiver of described RS422 differential level standard is the difference transponder chip MAX490CPA of standard, 0-9 in described 4X4 matrix keyboard amounts to the different traffic rate of 10 digitized representations 10 kinds, to represent successively from 100KHZ at interval of 100KHZ until 1MHZ.
3., according to claim 1 for the device of SSI interface absolute value encoder data communication, it is characterized in that: described in the IOPA0 to IOPA7 of PA mouth that is embedded in dsp controller be set to general I/O port.
4. according to claim 1 for the device of SSI interface absolute value encoder data communication, it is characterized in that: described SPI module is sixteen bit register, this SPI module comprises principal and subordinate's working mode selection register, data register, data length control register, receives buffer register, traffic rate control register, clock polarity register and clock phase register, wherein, the system clock frequency CLKOUT signal of dsp controller, the frequency of operation needed for scrambler is reached through traffic rate control register frequency division, the SPIBRR=79 of traffic rate control register is made namely to meet the demands, and the time clock of time delay negative edge is obtained by arranging clock polarity register and clock phase register, setting principal and subordinate working mode selection register is aggressive mode, SPICTL register second SPICTL.2=1 is made to meet the demands, under active work mode, position data SPISOMI pin in figure enters SPI module, because scrambler is individual pen absolute value 12 precision, 12 bit data need be transmitted, time clock needs 13 negative edges and rising edge: first negative edge is for activating monostable circuit, rear 12 negative edges read 12 position datas for spi bus, front 12 rising-edge encoder outwards send data, last rising edge makes data signal line become low level, therefore, need setting data cut to lengthen register transfer 13 characters, the 3rd, SPICCR register is made to meet the demands to zero-bit SPICCR.3 ~ SPICCR.0=1100, after above-mentioned setting, under the effect of SPI module clock pulse signal SPICLK, the position data that position coder is sent enters into data register through SPISOMI pin, when all figure places of position data all transmit complete, this position data just enters into and receives buffer register, follow-up data processing is carried out for dsp controller.
5. according to claim 1 for the device of SSI interface absolute value encoder data communication, it is characterized in that: have spi bus sequential in described SPI module, this spi bus is made up of clock cable and SPICLK and driven output/active input line and SPISOMI.
6. according to claim 1 for the device of SSI interface absolute value encoder data communication, it is characterized in that: the described SPI module mode be embedded in dsp controller is the zero setting signal ZERO of general I/O mouth function as SSI absolute value encoder of 30 pin using dsp controller, the system clock frequency of dsp controller delivers to SPI module by CLKOUT pin, and the reception buffer register of dsp controller by SPI inside modules and the data interaction of the realization of transmission buffer register and SPI module.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410637666.8A CN104536330A (en) | 2014-11-13 | 2014-11-13 | Data communication device for absolute value encoder with SSI |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201410637666.8A CN104536330A (en) | 2014-11-13 | 2014-11-13 | Data communication device for absolute value encoder with SSI |
Publications (1)
Publication Number | Publication Date |
---|---|
CN104536330A true CN104536330A (en) | 2015-04-22 |
Family
ID=52851874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201410637666.8A Pending CN104536330A (en) | 2014-11-13 | 2014-11-13 | Data communication device for absolute value encoder with SSI |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN104536330A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107562662A (en) * | 2017-09-13 | 2018-01-09 | 中国航天科技集团公司烽火机械厂 | A kind of conversion method and circuit that SPI signal is converted to SSI signals |
CN108919974A (en) * | 2016-01-05 | 2018-11-30 | 湖南工业大学 | A kind of matrix keyboard state recognition and coding method |
CN109814441A (en) * | 2018-12-30 | 2019-05-28 | 芜湖哈特机器人产业技术研究院有限公司 | A kind of method that STM32 microcontroller receives absolute encoder data |
CN109976489A (en) * | 2019-03-28 | 2019-07-05 | 烽火通信科技股份有限公司 | Automatically reset realization method and system under a kind of iic bus abnormal conditions |
CN114527691A (en) * | 2022-01-20 | 2022-05-24 | 湖南力行动力科技有限公司 | Method for realizing absolute encoder decoding system |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN200983099Y (en) * | 2006-06-24 | 2007-11-28 | 李兵 | Measurement and control instrument of strobe load openness |
WO2011030628A1 (en) * | 2009-09-09 | 2011-03-17 | 株式会社安川電機 | Interface circuit, inverter apparatus, inverter system and transmission/reception method |
CN102436262A (en) * | 2011-09-26 | 2012-05-02 | 北京航空航天大学 | High-precision and large-load control system and method of three-axis inertially stabilized platform for airborne remote sensing |
CN102494599A (en) * | 2011-11-01 | 2012-06-13 | 中国科学院国家天文台南京天文光学技术研究所 | Position detection method of large-calibre millimetre wave/sub-millimetre wave telescope control system |
CN203084482U (en) * | 2013-02-06 | 2013-07-24 | 焦作市明株自动化工程有限责任公司 | Signal acquisition device of synchronous serial output shaft encoder |
CN103530266A (en) * | 2013-10-30 | 2014-01-22 | 陕西高新实业有限公司 | Synchronous 422 interface based on SPI bus technology |
CN103792939A (en) * | 2014-01-28 | 2014-05-14 | 合肥三立自动化工程有限公司 | Absolute value encoder signal measuring and control instrument and detection method thereof |
-
2014
- 2014-11-13 CN CN201410637666.8A patent/CN104536330A/en active Pending
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN200983099Y (en) * | 2006-06-24 | 2007-11-28 | 李兵 | Measurement and control instrument of strobe load openness |
WO2011030628A1 (en) * | 2009-09-09 | 2011-03-17 | 株式会社安川電機 | Interface circuit, inverter apparatus, inverter system and transmission/reception method |
CN102436262A (en) * | 2011-09-26 | 2012-05-02 | 北京航空航天大学 | High-precision and large-load control system and method of three-axis inertially stabilized platform for airborne remote sensing |
CN102494599A (en) * | 2011-11-01 | 2012-06-13 | 中国科学院国家天文台南京天文光学技术研究所 | Position detection method of large-calibre millimetre wave/sub-millimetre wave telescope control system |
CN203084482U (en) * | 2013-02-06 | 2013-07-24 | 焦作市明株自动化工程有限责任公司 | Signal acquisition device of synchronous serial output shaft encoder |
CN103530266A (en) * | 2013-10-30 | 2014-01-22 | 陕西高新实业有限公司 | Synchronous 422 interface based on SPI bus technology |
CN103792939A (en) * | 2014-01-28 | 2014-05-14 | 合肥三立自动化工程有限公司 | Absolute value encoder signal measuring and control instrument and detection method thereof |
Non-Patent Citations (3)
Title |
---|
张琴琴,等: "基于DSP的绝对式光电编码器串行接口设计", 《现代电子技术》 * |
礼冰冰, 等: "基于TMS320F2808的高精度绝对式光电编码器串行接口设计", 《微电机》 * |
谢俊聃,等: "基于SPI总线技术的同步422接口设计", 《电子技术应用》 * |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108919974A (en) * | 2016-01-05 | 2018-11-30 | 湖南工业大学 | A kind of matrix keyboard state recognition and coding method |
CN107562662A (en) * | 2017-09-13 | 2018-01-09 | 中国航天科技集团公司烽火机械厂 | A kind of conversion method and circuit that SPI signal is converted to SSI signals |
CN107562662B (en) * | 2017-09-13 | 2020-07-24 | 四川航天烽火伺服控制技术有限公司 | Conversion method and circuit for converting SPI signal into SSI signal |
CN109814441A (en) * | 2018-12-30 | 2019-05-28 | 芜湖哈特机器人产业技术研究院有限公司 | A kind of method that STM32 microcontroller receives absolute encoder data |
CN109976489A (en) * | 2019-03-28 | 2019-07-05 | 烽火通信科技股份有限公司 | Automatically reset realization method and system under a kind of iic bus abnormal conditions |
CN109976489B (en) * | 2019-03-28 | 2021-04-27 | 烽火通信科技股份有限公司 | Automatic reset implementation method and system under IIC (inter-Integrated Circuit) bus abnormal condition |
CN114527691A (en) * | 2022-01-20 | 2022-05-24 | 湖南力行动力科技有限公司 | Method for realizing absolute encoder decoding system |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN104536330A (en) | Data communication device for absolute value encoder with SSI | |
CN102109836B (en) | Expandable and cuttable multi-shaft movement control system and method | |
CN103117732B (en) | Multi-channel video pulse signal generation device and method | |
CN208985151U (en) | One kind being based on the cascade SSI data acquisition circuit of shift register | |
CN105262490A (en) | Self-adaptive system based on Manchester coding and decoding, and method thereof | |
CN108471303A (en) | Programmable nanosecond timing precision pulse generator based on FPGA | |
CN109968356A (en) | Mechanical arm force-feedback control system and method based on Embedded Motion | |
CN101047447B (en) | Point-to-point industrial series real-time communication system based on optical fibre and its control method | |
CN201163363Y (en) | General multi-axis motion control system on numerical control machine | |
CN202205069U (en) | Analog quantity collecting module for programmable logical controller (PLC) controller | |
CN103699051A (en) | Wireless telecontrol system | |
CN217718457U (en) | Multi-type sensor information acquisition general circuit based on FPGA | |
CN213363816U (en) | Multi-protocol compatible angle acquisition system | |
CN202004710U (en) | Alternating-current servo controller using electronic transmission ratio | |
CN103163825A (en) | Four-channel numerical control system ENDAT2.2 interface | |
CN101109638B (en) | Optic fiber gyroscope analogue quantity angular velocity output circuit with zeroing function | |
CN201674483U (en) | IRIG_B code decoding interface circuit | |
CN202500555U (en) | Data transmission system in petroleum logger | |
CN102736549A (en) | 24-Bit acquisition module | |
CN202632782U (en) | Multi-channel SSI (Small Scale Integration) data acquisition module based on MicroBlaze soft core | |
CN201319135Y (en) | System architecture based on FPGA for industrial composite signal acquiring equipment | |
CN210719211U (en) | Detection system based on signal acquisition and processing of multi-channel incremental encoder | |
CN201184970Y (en) | Embedded board for acquiring data of watercraft engine compartment | |
CN201054591Y (en) | A point-to-point industrial serial real time communication system based on optical fiber | |
CN110752798B (en) | Multi-shaft multifunctional motor position decoding system based on ZYNQ |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20150422 |
|
WD01 | Invention patent application deemed withdrawn after publication |