WO2021179218A1

WO2021179218A1 - Direct memory access unit, processor, device, processing method, and storage medium

Info

Publication number: WO2021179218A1
Application number: PCT/CN2020/078852
Authority: WO
Inventors: 任子木; 韩彬
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2020-03-11
Filing date: 2020-03-11
Publication date: 2021-09-16
Also published as: CN112823343A

Abstract

A direct memory access unit, a digital signal processor, a direct memory access task processing device, a direct memory access task processing method, and a storage medium. The direct memory access unit comprises at least one data path and a direct memory access unit controller, wherein the direct memory access unit controller comprises a task management module that is connected to the at least one data path and a reduced instruction set processor located outside the direct memory access unit; and the task management module acquires, from the reduced instruction set processor, at least one piece of task description parameter information corresponding to data of a plurality of direct memory access tasks, so as to determine, according to the at least one piece of task description parameter information, at least one direct memory access task to be executed currently, thereby improving the execution efficiency of the direct memory access task.

Description

Direct memory access unit, processor, device, processing method and storage medium

Technical field

This application relates to the field of communication technology, and in particular to a direct memory access unit, a processor, a device, a processing method, and a storage medium.

Background technique

Digital Signal Processing (Digital Signal Processing, hereinafter referred to as DSP) has a wide range of applications in image processing, artificial intelligence and other fields due to its high computing power and good programmable characteristics. Among them, direct memory access (Direct Memory Access, DMA) is an important part of DSP. DMA is used to realize the connection between the double-rate synchronous dynamic random access memory (Double Data Rate, hereinafter referred to as DDR) outside the DSP and the internal cache of the DSP. Data movement for direct memory access tasks. In more complex applications, there are many direct memory access tasks that need to be performed, and there are also many types of direct memory access tasks, such as reading large-volume data tasks, writing large-volume data tasks, and so on. Currently, DSP uses A single-threaded approach or a queue approach to manage the execution of these different types of multiple direct memory access tasks is inefficient.

Summary of the invention

Based on this, the present application provides a direct memory access unit, a processor, a device, a processing method, and a storage medium to improve the execution efficiency of the direct memory access task.

In the first aspect, this application provides a direct memory access unit, including at least one data path and a direct memory access unit controller;

in,

The at least one data path is used to transmit data of direct memory access tasks, wherein the at least one data path correspondingly transmits data of different types of direct memory access tasks;

The direct memory access control unit controller includes a task management module connected to the at least one data path and a reduced instruction set processor located outside the direct memory access unit; wherein,

The task management module obtains at least one task description parameter information corresponding to data of a plurality of direct memory access tasks from the reduced instruction set processor to determine at least one task description parameter information currently to be executed according to the at least one task description parameter information Direct memory access tasks.

In the second aspect, the present application also provides a digital signal processor, the digital signal processor including a reduced instruction set processor and the direct memory access unit as described above.

In a third aspect, this application also provides a direct memory access task processing device, the direct memory access task processing device including the above-mentioned digital signal processor.

In a fourth aspect, this application also provides a method for processing multiple direct memory access tasks, which is applied to the above-mentioned direct memory access unit, including:

Acquiring at least one task description parameter information corresponding to the data of multiple direct memory access tasks from the reduced instruction set processor;

According to the at least one task description parameter information, at least one direct memory access task currently to be executed is determined.

In a fifth aspect, the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor realizes the multiple direct commands described above. Memory access task processing method.

The direct memory access unit, digital signal processor, direct memory access task processing equipment, multiple direct memory access task processing methods, and computer-readable storage medium disclosed in the present application improve the execution efficiency of direct memory access tasks.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the application.

Description of the drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following will briefly introduce the drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. Ordinary technicians can obtain other drawings based on these drawings without creative work.

Figure 1 is a schematic diagram of the data interaction process of the digital signal processor;

Figure 2 is a schematic diagram of a data transfer channel in direct memory access;

Fig. 3 is a schematic block diagram of a digital signal processor according to an embodiment of the present application;

4a and 4b are schematic diagrams of task description parameter information provided by an embodiment of the present application;

5 is a schematic block diagram of a direct memory access unit interaction provided by an embodiment of the present application;

6a, 6b, and 6c are schematic diagrams of execution of direct memory access tasks provided by an embodiment of the present application;

FIG. 7 is a schematic diagram of a virtual queue provided by an embodiment of the present application;

FIG. 8 is a schematic diagram of a virtual queue provided by an embodiment of the present application;

FIG. 9 is a schematic diagram of state marking information provided by an embodiment of the present application;

10 is a schematic flowchart of steps of a method for processing multiple direct memory access tasks provided by an embodiment of the present application;

FIG. 11 is a schematic block diagram of a direct memory access unit provided by an embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application will be described clearly and completely in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all of them. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without creative work shall fall within the protection scope of this application.

The flowchart shown in the drawings is only an example, and does not necessarily include all contents and operations/steps, nor does it have to be executed in the described order. For example, some operations/steps can also be decomposed, combined or partially combined, so the actual execution order may be changed according to actual conditions.

It should be understood that the terms used in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit the application. As used in the specification of this application and the appended claims, unless the context clearly indicates other circumstances, the singular forms "a", "an" and "the" are intended to include plural forms.

It should also be understood that the term "and/or" used in the specification and appended claims of this application refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

Hereinafter, some embodiments of the present application will be described in detail with reference to the accompanying drawings. In the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

In the prior art, Direct Memory Access (DMA) is an important part of the Digital Signal Processing (DSP). DMA is used to implement the Double Data Rate Synchronous Dynamic Random Access Memory (Double Data Rate) external to the DSP. , DDR) and DSP internal cache (hereinafter referred to as BLK_MEM) for data movement of direct memory access tasks. For example, as shown in Figure 1, the data interaction process of the DSP, the data of the direct memory access task is stored on the DDR, and the data is moved through DMA, moved to the DSP internal buffer BLK_MEM inside the DSP, and then loaded through the storage unit (load store unit, hereinafter referred to as LSU) completes the loading of data from the DSP internal cache BLK_MEM to the vector process unit (hereinafter referred to as VPU), processes the data through the VPU, and after the data processing is completed, writes the result through the LSU In the DSP internal buffer BLK_MEM, the data in the DSP internal buffer BLK_MEM is finally written out to the DDR through DMA.

As shown in Figure 2, there are generally 4 data transfer channels in DMA: read large amounts of data read nd, write large amounts of data write nd, read small amounts of data read imm, and write small amounts of data write imm. Among them:

read/write nd: These two channels perform the transfer of data with a large amount of data (mass data), nd can be divided into 1d/2d/3d, 1d corresponds to one-dimensional linear data, 2d corresponds to two-dimensional planar data, and 3d corresponds to three-dimensional Block data is generally moved from the DDR external to the DSP to the BLK MEM.

read/write imm, these two channels are used to perform the movement of data with a small amount of data (for example, immediate data). The immediate data is generally stored in the data buffer inside the DSP, and the reduced instruction set processor (Reduced Instruction Set Computer (RISC) can directly and quickly access the data buffer.

In more complex applications, there are many direct memory access tasks that need to be performed, and there are also many types of direct memory access tasks, such as reading large-volume data tasks, writing large-volume data tasks, and so on. Currently, DSP uses A single-threaded approach or a queue approach to manage the execution of these different types of multiple direct memory access tasks is inefficient.

In order to solve the above-mentioned problems, the embodiments of the present application provide a direct memory access unit, a digital signal processor, a direct memory access task processing device, multiple direct memory access task processing methods, and a computer-readable storage medium. To improve the execution efficiency of direct memory access tasks.

Please refer to FIG. 3, which is a schematic block diagram of a digital signal processor according to an embodiment of the application. As shown in FIG. 3, the digital signal processor 1000 may include a direct memory access unit 100 and a reduced instruction set processor 200, and the reduced instruction set processor 200 and the direct memory access unit 100 are in communication connection.

Exemplarily, the direct memory access unit 100 includes at least one data path (not shown in the figure) and a direct memory access unit controller 110, wherein at least one data path is used to transmit data of the direct memory access task, At least one data path corresponds to transmitting data of different types of direct memory access tasks. At least one data path includes, but is not limited to, read large-batch data path, write large-batch data path, read small-batch data path, write small-batch data path, etc. Different types of direct memory access tasks include but are not limited to read large-batch data tasks , Write large-batch data tasks, read small-batch data tasks, write small-batch data tasks, etc. The read large-batch data path corresponds to data transmission and read large-batch data tasks, and the write large-batch data path corresponds to the data transmission and write large-batch data tasks. The read small-batch data path corresponds to the transmission of data for the task of reading small-batch data, and the write small-batch data path corresponds to the transmission of data for the task of writing small-batch data.

The direct memory access unit controller 110 includes a task management module 111 connected to at least one data path and a reduced instruction set processor 200 located outside the direct memory access unit 100, wherein the task management module 111 is from the reduced instruction set processor 200 Acquire at least one task description parameter information corresponding to data of multiple direct memory access tasks to determine at least one direct memory access task currently to be executed according to the at least one task description parameter information, thereby realizing multiple direct memory access tasks Compared with using a single thread or a queue to manage the execution of multiple direct memory access tasks of different types, the parallel execution of the direct memory access tasks improves the execution efficiency of the direct memory access tasks.

At least one task description parameter information corresponding to the data of the direct memory access task is defined in advance. The task description parameter information includes but not limited to priority (pri), interrupt parameter value (irq_mask), order preserving parameter value (order_preserve), transmission The value of the direction parameter (direction), etc. For example, as shown in Figure 4a, the task description parameter information corresponding to one-dimensional linear data, task management is related to priority pri, interrupt parameter value irq_mask, order preserving parameter value order_preserve, and transmission direction parameter value direction. As shown in Figure 4b, the task description parameter information corresponding to the immediate data is related to the interrupt parameter value irq_mask, the order preserving parameter value order_preserve, and the transmission direction parameter value direction.

Exemplarily, the task description parameter information corresponding to the data of the direct memory access task includes the order preserving parameter value order_preserve. The order preserving parameter value order_preserve indicates whether the direct memory access task is executed strictly in order. Optionally, the order preserving parameter is defined A value of order_preserve of 0 means non-strict order-preserving execution, and a value of order-preserve parameter order_preserve of 1 means strict order-preserving execution. Or, define the order preserving parameter value order_preserve to be 1 to indicate non-strict order preserving execution, and to define the order preserving parameter value order_preserve to 0 to indicate strict order preserving execution.

The task management module 111 determines the order-preserving execution direct memory access task among the multiple direct memory access tasks according to the order preservation parameter value order_preserve corresponding to the multiple direct memory access tasks. Specifically, among the multiple direct memory access tasks, if any of them is a direct memory access task, for ease of description, it is hereinafter referred to as the first direct memory access task, if the order preservation parameter corresponding to the first direct memory access task If the value order_preserve is 0, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; if the order preservation parameter value order_preserve corresponding to the first direct memory access task is 1, then the first direct memory access task is determined Take the task as the order-preserving execution of the direct memory access task.

Or, on the contrary, if the order preserving parameter value order_preserve corresponding to the first direct memory access task is 1, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; if the first direct memory access task If the corresponding order preserving parameter value order_preserve is 0, it is determined that the first direct memory access task is the order preserving execution direct memory access task.

After that, the task management module 111 sorts the order-preserving execution direct memory access tasks according to the task loading order, and determines the order-preserving execution direct memory access task with the highest ranking as the current direct memory access task to be executed. By setting the value of the order preserving parameter value order_preserve corresponding to the direct memory access task, the execution order of the direct memory access task can be controlled. For data-dependent application scenarios, it can efficiently realize the existence of multiple direct memory access tasks. Order scheduling.

Exemplarily, the direct memory access unit 100 further includes at least one task queue 120, and a corresponding relationship between the task queue 120 and the data path is preset. Optionally, one task queue 120 corresponds to one data path. In one embodiment, for example, as shown in FIG. 5, the at least one task queue includes a task queue for reading large batches of data, a task queue for writing large batches of data, a task queue for reading small batches of data, and a task queue for writing small batches of data. Paths include read large-batch data path, write large-batch data path, read small-batch data path, and write small-batch data path; read large-batch data task queue corresponds to read large-batch data path, write large-batch data task queue corresponds to write large-batch data Path, the task queue for reading small-batch data corresponds to the path for reading small-batch data, and the task queue for writing small-batch data corresponds to the path for writing small-batch data.

The task management module 111 includes a task processing module, which is used to distribute direct memory access tasks to corresponding task queues. There are 4 task queues in total, and 4 queues are used to maintain 4 parallel direct memory access tasks to complete direct memory storage. Take the task scheduling work, and finally allocate the direct memory access task to the data path to complete the data interaction between the DDR and the internal buffer BLK_MEM of the DSP.

Specifically, if the current direct memory access task to be executed is the task of reading a large batch of data, the first data corresponding to the task of reading the large batch of data is read from the DDR outside the digital signal processor, and the first data is based on the reading The mass data path is transmitted to the DSP internal buffer BLK_MEM of the digital signal processor DSP, and the first data is written into the DSP internal buffer BLK_MEM. If the current direct memory access task to be executed is a task of reading small batch data, read the second data corresponding to the task of reading small batch data from the DDR, and transmit the second data to the digital signal processing based on the read small batch data path And write the second data into the data buffer. If the current direct memory access task to be executed is a bulk data write task, the third data corresponding to the write bulk data task is read from the DSP internal buffer BLK_MEM, and the third data is transmitted to the DDR based on the write bulk data path. And write the third data into DDR. If the current direct memory access task to be executed is the task of writing small batch data, the fourth data corresponding to the task of writing small batch data is read from the data buffer, and the fourth data is transmitted to the DDR based on the writing small batch data path, and Write the fourth data into the DDR.

The task management module 111 determines the task queue corresponding to the at least one direct memory access task currently to be executed according to at least one task description parameter information corresponding to the at least one direct memory access task currently to be executed, and according to the correspondence between the task queue and the data path Relationship, execute at least one direct memory access task currently to be executed. Specifically, at least one direct memory access task to be executed currently is scheduled to the corresponding task queue, and the direct memory access task scheduled to each task queue is allocated to the corresponding task queue according to the corresponding relationship between the task queue and the data path. In the data path of, to execute at least one direct memory access task currently to be executed. Since each task queue corresponds to the corresponding data path and is managed separately, the management granularity is finer, and the direct memory access task management is more efficient.

For example, as shown in Figure 6a, three tasks are pressed successively: task A, task B, and task C, all of which are executed in order to perform direct memory access tasks. The order of task pressing is A->B->C, and task The priority is the same, and the execution order of tasks is the same as the order of task pressing, which is A->B->C, that is, task A is executed first, then task B is executed, and task C is executed last.

As shown in Figure 6b, three tasks are pressed successively: task A, task B, and task C, and none of them are executed in order-preserving direct memory access tasks. The order of task pressing is A->B->C, and the task priority is Similarly, the execution order of the tasks is inconsistent with the order in which the tasks are pressed, and task A and task B are executed in parallel, and then task C is executed.

As shown in Figure 6c, four tasks are pressed successively: task A, task B, task C, and task D. Among them, task A and task B are order-preserving execution direct memory access tasks, and task C and task D are not order-preserving tasks. Execute direct memory access tasks, the task pressing order is A->B->C->D, the task priority is the same, the execution order of the tasks is inconsistent with the task pressing order, the tasks A and D are executed in parallel first, and then in parallel Perform task B and task C. That is to say, when a preserving task needs to wait for other preserving tasks in other channels before the preserving task to be executed first, due to the use of preserving parameter values, non-sequence preserving tasks in the same channel can be executed before The task of preserving order is executed.

Exemplarily, the task management module 111 determines the order preserving of the multiple direct memory access tasks according to the order_preserve parameter value order_preserve corresponding to the multiple direct memory access tasks, and then uses the first direct memory access task to execute the direct memory access task. Take the task as an example. If the first direct memory access task is the order-preserving execution direct memory access task, the first direct memory access task is pressed into the virtual queue according to the task loading order, that is, the order-preserving execution is directly executed. The memory access task is pressed into the virtual queue. The virtual queue is executed in strict first-in, first-out order. Only the tasks at the head of the virtual queue are valid candidate tasks, and the tasks at the non-head of the queue are invalid candidate tasks. For example, as shown in Figure 7, task B, task C, task D, and task I are pressed into the virtual queue. Task B is at the head of the virtual queue. Only task B is a valid candidate task. Task C, task D, Task I is an invalid candidate task. It should be noted that the size of the virtual queue can be flexibly set according to the actual situation. For example, if it is set to 64bit, there is no specific restriction here.

Exemplarily, after the task management module 111 presses the sequenced execution direct memory access tasks among the multiple direct memory access tasks into the virtual queue according to the task loading sequence, when the execution of the current direct memory access tasks to be executed is completed , That is, when the execution of the direct memory access task at the head of the virtual queue is completed, the head pointer queue_head of the virtual queue is increased by 1; in addition, when a new order-preserving execution of the direct memory access task is pressed into the virtual queue, the The tail pointer queue_rear of the virtual queue is incremented by 1.

Exemplarily, the task management module 111 stores task description parameter information corresponding to each direct memory access task in a preset priority queue. Optionally, the priority queue can buffer a preset number of task description parameter information. For example, as shown in FIG. 8, the priority queue buffers 8 task description parameter information dscrp_data0 to dscrp_data7.

Exemplarily, the task description parameter information corresponding to the data of the direct memory access task is correspondingly configured with status tag information. Optionally, the task management module 111 assigns the status tag information corresponding to the task description parameter information of each direct memory access task Stored in the status register pri_status. Optionally, as shown in FIG. 8, the status register pri_status includes 4 regions, and the 4 regions respectively store status flag information such as task valid parameter value valid, task activation parameter value active, priority parameter value dscrp_pri, and time stamp time_stamp.

Among them, the task valid parameter value valid, 1bit, indicates whether there is a task at the current position; the task activation parameter value active, 1bit, indicates whether the active task is cached at the current position, for non-sequential execution direct memory access tasks, all belong to The activated task, for the order-preserving direct memory access task at the head of the virtual queue, belongs to the activated task; the priority parameter value dscrp_pri, 3bit, is directly obtained from the task description parameter information header; the timestamp time_stamp, 3bit , The larger the value, the longer the pressing time.

The task management module 111 determines the direct memory access task with the highest execution level according to the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks, and determines the direct memory access task with the highest execution level as the current to be executed Direct memory access tasks.

Optionally, for example, as shown in FIG. 8, the status flag information corresponding to each task description parameter information includes a task valid parameter value valid, a task activation parameter value active, and a priority parameter value dscrp_pri. The task management module 111 first determines the effective direct memory access task among the multiple direct memory access tasks according to the value of the task effective parameter value valid corresponding to the multiple direct memory access tasks. Optionally, if the valid parameter value of the task corresponding to the direct memory access task is 0, the direct memory access task is determined to be an invalid direct memory access task; if the valid parameter value of the task corresponding to the direct memory access task is 1 , The direct memory access task is determined to be an effective direct memory access task. Or, on the contrary, if the valid parameter value of the task corresponding to the direct memory access task is 1, then the direct memory access task is determined to be invalid. The direct memory access task is determined to be invalid; if the valid parameter value of the task corresponding to the direct memory access task is 0 , The direct memory access task is determined to be an effective direct memory access task.

Then, according to the value of the task activation parameter value active corresponding to the determined effective direct memory access task, the active direct memory access task in the effective direct memory access task is determined. Exemplarily, if the task activation parameter value active corresponding to the direct memory access task is 0, it is determined that the direct memory access task is an inactive direct memory access task; if the task activation parameter value active corresponding to the direct memory access task is 1. The direct memory access task is determined to be the active direct memory access task. Or, on the contrary, if the task activation parameter value active corresponding to the direct memory access task is 1, it is determined that the direct memory access task is an inactive direct memory access task; if the task activation parameter value active corresponding to the direct memory access task is 0, the direct memory access task is determined to be the active direct memory access task.

Then, according to the value of the priority parameter value dscrp_pri corresponding to the activated direct memory access task, the activated direct memory access task with the highest priority is determined, and the activated direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level. Memory access tasks.

Exemplarily, the status tag information corresponding to the task description parameter information of the direct memory access task includes the time stamp time_stamp, and the task management module 111 determines the activated direct memory with the highest priority according to the status tag information corresponding to the multiple direct memory access tasks. Access task, if the active direct memory access task with the highest priority is one, the active direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level; if the active direct memory access task with the highest priority is activated There are multiple direct memory access tasks. According to the timestamp time_stamp corresponding to the multiple highest priority active direct memory access tasks, the highest priority active direct memory access task with the largest time stamp value is determined as the execution level The highest direct memory access task.

That is, the task valid parameter value valid has the highest priority, and the selected one is always a valid direct memory access task; the task activation parameter value active has the second highest priority, and the active direct memory access task takes precedence over the non-active task. Active direct memory access tasks; the priority parameter value dscrp_pri has the third priority. For two active and active direct memory access tasks, the direct memory access tasks with the higher priority parameter value dscrp_pri are loaded first Task; the timestamp time_stamp has the lowest priority. For two direct memory access tasks that are valid and active, if the priority parameter value dscrp_pri is also the same, the direct memory access task with the larger time stamp time_stamp is also selected. It is the direct memory access task with the longest time to press. Since the direct memory access tasks are always pressed in order, there will be no four direct memory access tasks that have the same priority. Scheduling direct memory access tasks in the same queue through 4 priority levels makes the scheduling and execution of direct memory access tasks more flexible.

Exemplarily, the task description parameter information corresponding to the direct memory access task includes an interrupt parameter value irq_mask, and the interrupt parameter value irq_mask indicates whether an interrupt notification is sent after the direct memory access task is completed. Optionally, the interrupt parameter value irq_mask of 0 means that an interrupt notification is sent, and the interrupt parameter value of irq_mask of 1 means that the interrupt notification is not sent.

After the execution of the direct memory access task is completed, the task management module 111 determines whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value irq_mask corresponding to the direct memory access task. Optionally, if the interrupt parameter value irq_mask corresponding to the direct memory access task is 1, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value irq_mask corresponding to the direct memory access task is 0, it is determined to report Interrupt notification to the reduced instruction set processor. Or, on the contrary, if the interrupt parameter value irq_mask corresponding to the direct memory access task is 0, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value irq_mask corresponding to the direct memory access task is 1, it is determined to report Interrupt notification to the reduced instruction set processor.

For example, as shown in Figure 9, task A, task B, and task C are pressed, where the interrupt parameter value irq_mask corresponding to task A is 1, the interrupt parameter value irq_mask corresponding to task B is 1, and the interrupt parameter corresponding to task C The value irq_mask is 0. When task A is executed, because its corresponding interrupt parameter value irq_mask is 1, no interrupt notification is reported; then after task B is executed, because its corresponding interrupt parameter value irq_mask is 1, therefore, no interrupt notification is reported; finally After task C is executed, since its corresponding interrupt parameter value irq_mask is 0, the interrupt notification is reported to the reduced instruction set processor. By setting the interrupt notification to the reduced instruction set processor after the completion of a specific task, the interaction between the reduced instruction set processor and the direct memory access unit is greatly reduced, and the efficiency of the reduced instruction set processor is improved. It should be noted that in another embodiment, the interrupt parameter value irq_mask can also be set to 1 to correspond to the reporting interrupt notification, and the interrupt parameter value irq_mask to 0 corresponds to the reporting interrupt notification.

It can be understood that the aforementioned naming of the various components of the digital signal processor is only for identification purposes, and does not therefore limit the embodiments of the present application.

The following will be based on the digital signal processor, the direct memory access unit in the digital signal processor, and the reduced instruction set processor in the digital signal processor to process multiple direct memory access tasks provided by the embodiments of the present application. The method is introduced in detail. It should be understood that the digital signal processor in FIG. 3 does not constitute a limitation on the application scenarios of the multiple direct memory access task processing methods.

Please refer to FIG. 10, which is a schematic flowchart of a method for processing multiple direct memory access tasks according to an embodiment of the present application. This method can be used in any of the direct memory access units provided in the above embodiments to improve the execution efficiency of the direct memory access task.

As shown in FIG. 10, the method for processing multiple direct memory access tasks specifically includes step S101 to step S102.

S101. Obtain at least one task description parameter information corresponding to data of multiple direct memory access tasks from the reduced instruction set processor.

In this embodiment, the reduced instruction set processor predefines at least one task description parameter information corresponding to the data of each direct memory access task, where the task description parameter information includes but is not limited to priority (pri), interrupt parameter value ( irq_mask), order preservation parameter value (order_preserve), transmission direction parameter value (direction), etc. For example, as shown in Figure 4a, the task description parameter information corresponding to one-dimensional linear data is related to pri, irq_mask, order_preserve, and direction for task management. As shown in Figure 4b, the task description parameter information corresponding to the immediate data is related to irq_mask, order_preserve, and direction for task management.

The direct memory access unit is connected to the external reduced instruction set processor. When the execution of multiple direct memory access tasks is to be managed, the direct memory access unit obtains multiple direct memory access tasks from the reduced instruction set processor At least one task description parameter information corresponding to the data.

S102. Determine at least one direct memory access task currently to be executed according to the at least one task description parameter information.

After obtaining at least one task description parameter information corresponding to the data of multiple direct memory access tasks, at least one direct memory access task to be executed currently is determined according to the at least one task description parameter information, so as to execute the at least one current task. The direct memory access task to be executed.

In some embodiments, the task description parameter information includes an order_preserve parameter value (order_preserve), and the determining at least one direct memory access task currently to be executed according to the at least one task description parameter information includes: according to the The order-preserving parameter values corresponding to the multiple direct memory access tasks determine the order-preserving execution direct memory access task among the multiple direct memory access tasks; the order-preserving execution direct memory access task is performed according to the task loading order Perform sorting, and determine the order-preserving execution direct memory access task at the top of the sort as the current direct memory access task to be executed.

Among them, the order preservation parameter value order_preserve indicates whether the direct memory access task is executed strictly in order. Optionally, the order preservation parameter value order_preserve is defined as 0 to indicate non-strict order preservation execution, and the order preservation parameter value order_preserve is 1 to indicate strict order preservation. implement. Or, define the order preserving parameter value order_preserve to be 1 to indicate non-strict order preserving execution, and to define the order preserving parameter value order_preserve to 0 to indicate strict order preserving execution.

Optionally, among the multiple direct memory access tasks, if any of them is a direct memory access task, for ease of description, it is hereinafter referred to as the first direct memory access task. If the first direct memory access task corresponds to order preservation If the parameter value order_preserve is 0, it is determined that the first direct memory access task is a non-order-executing direct memory access task; if the order preservation parameter value order_preserve corresponding to the first direct memory access task is 1, the first direct memory is determined The access task is to execute the direct memory access task in order.

After that, the direct memory access unit sorts the order-preserving execution direct memory access tasks according to the task loading order, and determines the order-preserving execution direct memory access task with the highest sort as the current direct memory access task to be executed. By setting the value of the order preserving parameter value order_preserve corresponding to the direct memory access task, the execution order of the direct memory access task can be controlled. For data-dependent application scenarios, it can efficiently realize the existence of multiple direct memory access tasks. Order scheduling.

In other embodiments, the direct memory access unit determines the order preserving of the multiple direct memory access tasks according to the order_preserve parameter value order_preserve corresponding to the multiple direct memory access tasks. Take a direct memory access task as an example. If the first direct memory access task is the order-preserving execution of the direct memory access task, the first direct memory access task is pressed into the virtual queue according to the task loading order, that is, The order-preserving execution direct memory access task is pushed into the virtual queue. The virtual queue is executed in strict first-in, first-out order. Only the tasks at the head of the virtual queue are valid candidate tasks, and the tasks at the non-head of the queue are invalid candidate tasks. For example, as shown in Figure 7, task B, task C, task D, and task I are pressed into the virtual queue. Task B is at the head of the virtual queue. Only task B is a valid candidate task. Task C, task D, Task I is an invalid candidate task. It should be noted that the size of the virtual queue can be flexibly set according to the actual situation. For example, if it is set to 64bit, there is no specific restriction here.

Optionally, after the order-preserving execution direct memory access task among multiple direct memory access tasks is pressed into the virtual queue according to the task loading order, when the execution of the current direct memory access task to be executed is completed, that is, it is in When the direct memory access task at the head of the virtual queue is executed, the head pointer queue_head of the virtual queue is increased by 1; in addition, when a new order-preserving direct memory access task is executed in the virtual queue, the tail of the virtual queue is added The pointer queue_rear is incremented by 1.

In other embodiments, the direct memory access unit stores task description parameter information corresponding to each direct memory access task in a preset priority queue. Optionally, the priority queue can buffer a preset number of task description parameter information.

In other embodiments, the task description parameter information corresponding to the data of the direct memory access task is correspondingly configured with status flag information, and the at least one direct memory access to be executed currently is determined according to the at least one task description parameter information. The task includes: determining the direct memory access task with the highest execution level according to the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks; determining the direct memory access task with the highest execution level as the current waiting task Direct memory access tasks performed.

Optionally, the status flag information corresponding to each task description parameter information includes a task valid parameter value valid, a task activation parameter value active, and a priority parameter value dscrp_pri. First, determine the effective direct memory access task among the multiple direct memory access tasks according to the value of the task effective parameter value valid corresponding to the multiple direct memory access tasks. Optionally, if the valid parameter value of the task corresponding to the direct memory access task is 0, the direct memory access task is determined to be an invalid direct memory access task; if the valid parameter value of the task corresponding to the direct memory access task is 1 , The direct memory access task is determined to be an effective direct memory access task. Or, on the contrary, if the valid parameter value of the task corresponding to the direct memory access task is 1, then the direct memory access task is determined to be invalid. The direct memory access task is determined to be invalid; if the valid parameter value of the task corresponding to the direct memory access task is 0 , The direct memory access task is determined to be an effective direct memory access task.

Optionally, the status tag information corresponding to the task description parameter information of the direct memory access task includes a time stamp time_stamp, and the activated direct memory access task with the highest priority is determined according to the status tag information corresponding to multiple direct memory access tasks, If there is one active direct memory access task with the highest priority, the active direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level; if the direct memory access task with the highest priority is activated If there are multiple tasks, according to the timestamp time_stamp corresponding to the multiple highest priority active direct memory access tasks, the highest priority active direct memory access task with the largest timestamp value is determined as the direct memory with the highest execution level Access tasks.

Optionally, the status flag information corresponding to the task description parameter information of each direct memory access task is stored in the status register pri_status. Exemplarily, as shown in FIG. 7, the status register pri_status includes 4 regions, and the 4 regions respectively store status flag information such as task valid parameter value valid, task activation parameter value active, priority parameter value dscrp_pri, and time stamp time_stamp.

In some other embodiments, the task description parameter information corresponding to the direct memory access task includes the interrupt parameter value irq_mask, and the multiple direct memory access task processing methods further include: after the direct memory access task is executed, according to The value of the interrupt parameter value corresponding to the direct memory access task determines whether to report an interrupt notification to the reduced instruction set processor.

Among them, irq_mask indicates whether to send an interrupt notification after the direct memory access task is completed. Optionally, the interrupt parameter value irq_mask of 0 means that an interrupt notification is sent, and the interrupt parameter value of irq_mask of 1 means that the interrupt notification is not sent.

After the direct memory access task is executed, it is determined whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value irq_mask corresponding to the direct memory access task. Optionally, if the interrupt parameter value irq_mask corresponding to the direct memory access task is 1, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value irq_mask corresponding to the direct memory access task is 0, it is determined to report Interrupt notification to the reduced instruction set processor. Or, on the contrary, if the interrupt parameter value irq_mask corresponding to the direct memory access task is 0, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value irq_mask corresponding to the direct memory access task is 1, it is determined to report Interrupt notification to the reduced instruction set processor.

For example, as shown in Figure 9, task A, task B, and task C are pressed, where the interrupt parameter value irq_mask corresponding to task A is 1, the interrupt parameter value irq_mask corresponding to task B is 1, and the interrupt parameter corresponding to task C The value irq_mask is 0. When task A is executed, because its corresponding interrupt parameter value irq_mask is 1, no interrupt notification is reported; then after task B is executed, because its corresponding interrupt parameter value irq_mask is 1, therefore, no interrupt notification is reported; finally After task C is executed, since its corresponding interrupt parameter value irq_mask is 0, the interrupt notification is reported to the reduced instruction set processor. By setting the interrupt notification to the reduced instruction set processor after the completion of a specific task, the interaction between the reduced instruction set processor and the direct memory access unit is greatly reduced, and the efficiency of the reduced instruction set processor is improved.

In other embodiments, the direct memory access unit includes at least one task queue, and the corresponding relationship between the task queue and the data path is preset. Optionally, one task queue corresponds to one data path. At least one task queue includes a task queue for reading large batches of data, a task queue for writing large batches of data, a task queue for reading small batches of data, and a task queue for writing small batches of data. Read small-batch data path, write small-batch data path; read large-batch data task queue corresponds to read large-batch data path, write large-batch data task queue corresponds to write large-batch data path, read small-batch data task queue corresponds to read small-batch data path , Write small batch data task queue corresponds to write small batch data path.

After determining at least one direct memory access task currently to be executed according to the at least one task description parameter information, the method further includes: according to at least one task description parameter corresponding to the at least one direct memory access task currently to be executed Information to determine the task queue corresponding to the at least one direct memory access task currently to be executed; execute the at least one direct memory access task currently to be executed according to the corresponding relationship between the task queue and the data path.

Optionally, at least one direct memory access task currently to be executed is scheduled to the corresponding task queue, and the direct memory access task scheduled to each task queue is allocated to the corresponding task queue according to the corresponding relationship between the task queue and the data path In the corresponding data path, at least one direct memory access task currently to be executed is executed.

Since each task queue corresponds to the corresponding data path and is managed separately, the management granularity is finer, and the direct memory access task management is more efficient.

Please refer to FIG. 11. FIG. 11 is a schematic block diagram of a direct memory access unit provided by an embodiment of the present application. As shown in FIG. 11, the direct memory access unit 100 includes a processor 101 and a memory 102. The processor 101 and the memory 102 are connected by a bus, such as an I2C (Inter-integrated Circuit) bus.

Specifically, the processor 101 may be a micro-controller unit (MCU), a central processing unit (Central Processing Unit, CPU), a digital signal processor (Digital Signal Processor, DSP), or the like.

Specifically, the memory 102 may be a Flash chip, a read-only memory (ROM, Read-Only Memory) disk, an optical disk, a U disk, or a mobile hard disk.

Wherein, the processor is used to run a computer program stored in a memory, and implement the following steps when executing the computer program:

In some embodiments, the task description parameter information includes an order-preserving parameter value, and the processor determines at least one direct memory access task currently to be executed according to the at least one task description parameter information. ,Implementation:

Determining the order-preserving execution direct memory access task among the multiple direct memory access tasks according to the order-preserving parameter values corresponding to the multiple direct memory access tasks;

The order-preserving execution direct memory access tasks are sorted according to the task loading order, and the order-preserving execution direct memory access task with the highest ranking is determined as the current direct memory access task to be executed.

In some embodiments, the processor is implementing the sequence-preserving parameter value corresponding to the multiple direct memory access tasks to determine the sequence-preserving execution direct memory access among the multiple direct memory access tasks. During the task, the specific realization:

If the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 0, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 1, determining that the first direct memory access task is an order-preserving execution direct memory access task;

or

If the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 1, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 0, it is determined that the first direct memory access task is an order-preserving execution direct memory access task.

In some embodiments, the processor is implementing the sequence-preserving parameter value corresponding to the multiple direct memory access tasks to determine the sequence-preserving execution direct memory access among the multiple direct memory access tasks. After the task, concrete realization:

If it is determined that the first direct memory access task among the multiple direct memory access tasks is an order-preserving execution direct memory access task, then the first direct memory access task is pressed into the virtual queue according to the task loading order .

In some embodiments, when the processor executes the computer program, it also implements:

When the execution of the direct memory access task currently to be executed is completed, add 1 to the head pointer of the virtual queue;

When a new order-preserving execution direct memory access task is pressed into the virtual queue, the tail pointer of the virtual queue is incremented by one.

In some embodiments, the processor is configured with status flag information corresponding to the task description parameter information, and when determining at least one direct memory access task currently to be executed according to the at least one task description parameter information ,Implementation:

Determine the direct memory access task with the highest execution level according to the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks;

The direct memory access task with the highest execution level is determined as the direct memory access task currently to be executed.

In some embodiments, the status flag information includes task effective parameter values, task activation parameter values, and priority parameter values, and the processor is implementing the task description parameter information according to the multiple direct memory access tasks. Corresponding status flag information, when determining the direct memory access task with the highest execution level, the specific implementation is as follows:

Determine the effective direct memory access task among the multiple direct memory access tasks according to the values of the task effective parameter values corresponding to the multiple direct memory access tasks;

Determine the active direct memory access task in the effective direct memory access task according to the value of the task activation parameter value corresponding to the effective direct memory access task;

Determine the activated direct memory access task with the highest priority according to the value of the priority parameter value corresponding to the activated direct memory access task;

The active direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level.

In some embodiments, the status tag information includes a timestamp, and the processor determines the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks to determine the highest execution level of the direct When the memory access task, the specific realization:

Determine the activated direct memory access task with the highest priority according to the status flag information corresponding to the multiple direct memory access tasks;

If the activated direct memory access task with the highest priority includes multiple, then according to the multiple timestamps corresponding to the activated direct memory access tasks with the highest priority, the activated direct memory access task with the highest time stamp value is the highest priority. Take the task and determine it as the direct memory access task with the highest execution level.

In some embodiments, the processor determines the effective direct memory storage of the multiple direct memory access tasks according to the values of the effective parameter values of the tasks corresponding to the multiple direct memory access tasks. When taking a task, the specific realization is as follows:

If the task valid parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an invalid direct memory access task; if the task valid parameter value corresponding to the direct memory access task is 1, then the direct memory access task is determined Take the task as an effective direct memory access task;

or

If the effective parameter value of the task corresponding to the direct memory access task is 1, the direct memory access task is determined to be an invalid direct memory access task; if the task effective parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be 0. Take the task as an effective direct memory access task.

In some embodiments, the processor determines the active direct memory access task in the effective direct memory access task according to the value of the task activation parameter value corresponding to the effective direct memory access task When, the specific realization:

If the task activation parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 1, then the direct memory is determined The access task is to activate the direct memory access task;

or

If the task activation parameter value corresponding to the direct memory access task is 1, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 0, the direct memory is determined The access task is to activate the direct memory access task.

The status tag information corresponding to the task description parameter information of each direct memory access task is stored in the status register.

In some embodiments, the status register includes 4 areas, and the 4 areas respectively store task effective parameter values, task activation parameter values, priority parameter values, and time stamps.

The task description parameter information corresponding to each direct memory access task is stored in the preset priority queue.

In some embodiments, the task description parameter information includes interrupt parameter values, and when the processor executes the computer program, it also implements:

After the execution of the direct memory access task is completed, it is determined whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task.

In some embodiments, when the processor realizes the determination of whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task, it specifically implements:

If the interrupt parameter value corresponding to the direct memory access task is 1, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 0, then Determine to report the interrupt notification to the reduced instruction set processor;

or

If the interrupt parameter value corresponding to the direct memory access task is 0, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 1, then It is determined to report the interrupt notification to the reduced instruction set processor.

In some embodiments, the direct memory access unit further includes at least one task queue, preset with a corresponding relationship between the task queue and the data path, and the processor is implementing the parameter information according to the at least one task description, After determining at least one direct memory access task currently to be executed, it also implements:

Determine the task queue corresponding to the at least one direct memory access task currently to be executed according to at least one task description parameter information corresponding to the at least one direct memory access task currently to be executed;

According to the corresponding relationship between the task queue and the data path, execute the at least one direct memory access task currently to be executed.

In some embodiments, the correspondence between the task queue and the data path includes: one task queue corresponds to one data path.

In some embodiments, when the processor implements the at least one direct memory access task currently to be executed according to the corresponding relationship between the task queue and the data path, it specifically implements:

The at least one currently to be executed direct memory access task is scheduled to the corresponding task queue, and the direct memory access task scheduled to each task queue is allocated to the corresponding task queue according to the corresponding relationship between the task queue and the data path In the data path, the at least one direct memory access task currently to be executed is executed.

In some embodiments, the at least one data path includes a read bulk data path, a write bulk data path, a read small bulk data path, and a write low bulk data path, and the at least one task queue includes a read bulk data task queue , Write large-batch data task queue, read small-batch data task queue, write small-batch data task queue; the read large-batch data task queue corresponds to the read large-batch data path, and the write large-batch data task queue corresponds to the Write a large-batch data path, the read small-batch data task queue corresponds to the read small-batch data path, and the write small-batch data task queue corresponds to the write small-batch data path.

In some embodiments, the direct memory access unit is provided in a digital signal processor.

In some embodiments, when the processor implements the at least one direct memory access task currently to be executed, it specifically implements:

If the current direct memory access task to be executed is the task of reading bulk data, the first data corresponding to the task of reading bulk data is read from the external double-rate synchronous dynamic random access memory, and the first data is based on Read the bulk data path and transmit it to the internal buffer of the digital signal processor, and write the first data into the internal buffer;

If the target direct memory access task is a task of reading small-batch data, the second data corresponding to the task of reading small-batch data is read from the external double-rate synchronous dynamic random access memory, and the second data is Based on the read small batch data path, the data is transmitted to the data buffer of the digital signal processor, and the second data is written into the data buffer;

If the target direct memory access task is a task of writing bulk data, the third data corresponding to the task of writing bulk data is read from the internal cache, and the third data is transmitted based on the write bulk data path To the external double-rate synchronous dynamic random access memory, and write the third data into the double-rate synchronous dynamic random access memory;

If the target direct memory access task is a small batch data writing task, the fourth data corresponding to the small batch data writing task is read from the data buffer, and the fourth data is based on the writing small batch data path It is transmitted to the double-rate synchronous dynamic random access memory, and the fourth data is written into the double-rate synchronous dynamic random access memory.

An embodiment of the present application also provides a direct memory access task processing device. The direct memory access task processing device includes the digital signal processor 1000 in the foregoing embodiment. The direct memory access task processing device obtains at least one task description parameter information corresponding to the data of multiple direct memory access tasks from the reduced instruction set processor, and determines at least one task description parameter information currently to be executed according to the at least one task description parameter information For the direct memory access task, the specific operation can refer to the steps of the multiple direct memory access task processing methods provided in the embodiments of the present application, which will not be repeated here.

An embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium stores a computer program, the computer program includes program instructions, and a processor executes the program instructions to implement the embodiments of the present application. Provides the steps of multiple direct memory access task processing methods.

Wherein, the computer-readable storage medium may be the direct memory access unit or the digital signal processor or the internal storage unit of the direct memory access task processing device described in the foregoing embodiment, for example, the direct memory access unit or the digital signal processor. Signal processor or direct memory access to the hard disk or memory of task processing equipment. The computer-readable storage medium may also be an external storage device of the direct memory access unit or a digital signal processor or a direct memory access task processing device, such as the direct memory access unit or a digital signal processor or an external storage device. The plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, Flash Card, etc. equipped on the memory access task processing equipment.

According to the embodiments of the present invention, a direct memory access unit, a digital signal processor, a direct memory access task processing device, multiple direct memory access task processing methods, and a computer-readable storage medium are proposed. The direct memory access unit includes at least one data path and a direct memory access unit controller, wherein at least one data path is used to transmit data of the direct memory access task, and the direct memory access unit controller includes at least one data path and The task management module connected to the reduced instruction set processor located outside the direct memory access unit, the task management module obtains at least one task description parameter information corresponding to the data of the multiple direct memory access tasks from the reduced instruction set processor, so as to At least one task description parameter information, to determine at least one direct memory access task currently to be executed, so as to realize the parallel execution of multiple direct memory access tasks, compared to using a single thread or a queue to manage different types The execution of multiple direct memory access tasks improves the execution efficiency of direct memory access tasks.

The above are only specific implementations of this application, but the protection scope of this application is not limited to this. Any person skilled in the art can easily think of various equivalents within the technical scope disclosed in this application. Modifications or replacements, these modifications or replacements shall be covered within the protection scope of this application. Therefore, the protection scope of this application shall be subject to the protection scope of the claims.

Claims

A direct memory access unit, characterized in that:

The direct memory access unit includes at least one data path and a direct memory access unit controller;

in,

The at least one data path is used to transmit data of direct memory access tasks, wherein the at least one data path correspondingly transmits data of different types of direct memory access tasks;

The direct memory access unit controller includes a task management module connected to the at least one data path and a reduced instruction set processor located outside the direct memory access unit; wherein,

The task management module obtains at least one task description parameter information corresponding to data of a plurality of direct memory access tasks from the reduced instruction set processor, so as to determine at least one task description parameter information currently to be executed according to the at least one task description parameter information Direct memory access tasks.
The direct memory access unit according to claim 1, wherein the task description parameter information includes an order preserving parameter value, and the at least one task description parameter information is used to determine at least one direct current to be executed Memory access tasks, including:

Determining the order-preserving execution direct memory access task among the multiple direct memory access tasks according to the order-preserving parameter values corresponding to the multiple direct memory access tasks;

The order-preserving execution direct memory access tasks are sorted according to the task loading order, and the order-preserving execution direct memory access task with the highest ranking is determined as the current direct memory access task to be executed.
The direct memory access unit according to claim 2, wherein the task management module is specifically configured to:

If the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 0, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 1, determining that the first direct memory access task is an order-preserving execution direct memory access task;

or

If the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 1, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 0, it is determined that the first direct memory access task is an order-preserving execution direct memory access task.
The direct memory access unit according to claim 2, wherein the order preserving among the multiple direct memory access tasks is determined according to the order preserving parameter values corresponding to the multiple direct memory access tasks After performing the direct memory access task, it also includes:

If it is determined that the first direct memory access task among the multiple direct memory access tasks is an order-preserving execution direct memory access task, then the first direct memory access task is pressed into the virtual queue according to the task loading order .
The direct memory access unit according to claim 4, wherein the task management module is further configured to:

When the execution of the direct memory access task currently to be executed is completed, add 1 to the head pointer of the virtual queue;

When a new order-preserving execution direct memory access task is pressed into the virtual queue, the tail pointer of the virtual queue is incremented by one.
The direct memory access unit according to claim 1, wherein the task description parameter information is correspondingly configured with state flag information, and the at least one task description parameter information is used to determine at least one direct current to be executed Memory access tasks, including:

Determine the direct memory access task with the highest execution level according to the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks;

The direct memory access task with the highest execution level is determined as the direct memory access task currently to be executed.
The direct memory access unit according to claim 6, wherein the status flag information includes a task effective parameter value, a task activation parameter value, and a priority parameter value, and the task is based on the plurality of direct memory access tasks The status tag information corresponding to the task description parameter information determines the direct memory access task with the highest execution level, including:

Determine the effective direct memory access task among the multiple direct memory access tasks according to the values of the task effective parameter values corresponding to the multiple direct memory access tasks;

Determine the active direct memory access task in the effective direct memory access task according to the value of the task activation parameter value corresponding to the effective direct memory access task;

Determine the activated direct memory access task with the highest priority according to the value of the priority parameter value corresponding to the activated direct memory access task;

The active direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level.
The direct memory access unit according to claim 6, wherein the status mark information includes a time stamp, and the task management module is further configured to:

Determine the activated direct memory access task with the highest priority according to the status flag information corresponding to the multiple direct memory access tasks;

If the activated direct memory access task with the highest priority includes multiple, then according to the multiple timestamps corresponding to the activated direct memory access tasks with the highest priority, the activated direct memory access task with the highest time stamp value is the highest priority. Take the task and determine it as the direct memory access task with the highest execution level.
The direct memory access unit according to claim 7, wherein the task management module is specifically configured to:

If the task valid parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an invalid direct memory access task; if the task valid parameter value corresponding to the direct memory access task is 1, then the direct memory access task is determined Take the task as an effective direct memory access task;

or

If the effective parameter value of the task corresponding to the direct memory access task is 1, the direct memory access task is determined to be an invalid direct memory access task; if the task effective parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be 0. Take the task as an effective direct memory access task.
The direct memory access unit according to claim 7, wherein the task management module is specifically configured to:

If the task activation parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 1, then the direct memory is determined The access task is to activate the direct memory access task;

or

If the task activation parameter value corresponding to the direct memory access task is 1, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 0, the direct memory is determined The access task is to activate the direct memory access task.
The direct memory access unit according to any one of claims 6 to 10, wherein the task management module is further configured to:

The status tag information corresponding to the task description parameter information of each direct memory access task is stored in the status register.
The direct memory access unit according to claim 11, wherein the status register includes 4 areas, and the 4 areas respectively store task effective parameter values, task activation parameter values, priority parameter values, and time stamps. .
The direct memory access unit according to any one of claims 6 to 12, wherein the task management module is further configured to:

The task description parameter information corresponding to each direct memory access task is stored in the preset priority queue.
The direct memory access unit according to claim 1, wherein the task description parameter information includes interrupt parameter values, and the task management module is further configured to:

After the execution of the direct memory access task is completed, it is determined whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task.
The direct memory access unit according to claim 14, wherein the determining whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task, include:

If the interrupt parameter value corresponding to the direct memory access task is 1, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 0, then Determine to report the interrupt notification to the reduced instruction set processor;

or

If the interrupt parameter value corresponding to the direct memory access task is 0, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 1, then It is determined to report the interrupt notification to the reduced instruction set processor.
The direct memory access unit according to any one of claims 1 to 15, wherein the direct memory access unit further comprises at least one task queue, and the corresponding relationship between the task queue and the data path is preset, and the The task management module is also used to:

Determine the task queue corresponding to the at least one direct memory access task currently to be executed according to at least one task description parameter information corresponding to the at least one direct memory access task currently to be executed;

According to the corresponding relationship between the task queue and the data path, execute the at least one direct memory access task currently to be executed.
The direct memory access unit according to claim 16, wherein the correspondence between the task queue and the data path comprises: one task queue corresponds to one data path.
The direct memory access unit according to claim 16 or 17, wherein the executing the at least one direct memory access task currently to be executed according to the corresponding relationship between the task queue and the data path comprises:

The at least one direct memory access task currently to be executed is scheduled to the corresponding task queue, and the direct memory access task scheduled to each task queue is allocated to the corresponding task queue according to the corresponding relationship between the task queue and the data path In the data path, the at least one direct memory access task currently to be executed is executed.
The direct memory access unit according to any one of claims 16 to 18, wherein the at least one data path includes a read large-batch data path, a write large-batch data path, a read small-batch data path, and a write small-batch data path. In the data path, the at least one task queue includes a task queue for reading large batches of data, a task queue for writing large batches of data, a task queue for reading small batches of data, and a task queue for writing small batches of data; the task queue for reading large batches of data corresponds to the reading A large-batch data path, the write large-batch data task queue corresponds to the write large-batch data path, the read small-batch data task queue corresponds to the read small-batch data path, and the small-batch data write task queue corresponds to the Write small batch data path.
18. The direct memory access unit of claim 19, wherein the direct memory access unit is disposed in a digital signal processor.
22. The direct memory access unit of claim 20, wherein the executing the at least one direct memory access task currently to be executed comprises:

If the current direct memory access task to be executed is the task of reading bulk data, the first data corresponding to the task of reading bulk data is read from the external double-rate synchronous dynamic random access memory, and the first data Based on the read bulk data path, the data is transmitted to the internal buffer of the digital signal processor, and the first data is written into the internal buffer;

If the current direct memory access task to be executed is the task of reading small batch data, the second data corresponding to the task of reading small batch data is read from the double-rate synchronous dynamic random access memory, and the second data Based on the read small batch data path, the data is transmitted to the data buffer of the digital signal processor, and the second data is written into the data buffer;

If the current direct memory access task to be executed is a task of writing large batch data, the third data corresponding to the task of writing large batch data is read from the internal cache, and the third data is based on the writing large batch data path Transmitting to the double-rate synchronous dynamic random access memory, and writing the third data into the double-rate synchronous dynamic random access memory;

If the current direct memory access task to be executed is a task of writing small batch data, the fourth data corresponding to the task of writing small batch data is read from the data buffer, and the fourth data is based on writing small batch data The channel is transmitted to the double-rate synchronous dynamic random access memory, and the fourth data is written into the double-rate synchronous dynamic random access memory.
A digital signal processor, wherein the digital signal processor comprises a reduced instruction set processor and the direct memory access unit according to any one of claims 1 to 21, and the reduced instruction set processor The direct memory access unit is communicatively connected.
A direct memory access task processing device, wherein the direct memory access task processing device comprises the digital signal processor according to claim 22.
A method for processing multiple direct memory access tasks, applied to the direct memory access unit according to any one of claims 1 to 21, characterized in that it comprises:

Acquiring at least one task description parameter information corresponding to the data of multiple direct memory access tasks from the reduced instruction set processor;

According to the at least one task description parameter information, at least one direct memory access task currently to be executed is determined.
The method according to claim 24, wherein the task description parameter information includes a sequence preservation parameter value, and the at least one direct memory access task currently to be executed is determined according to the at least one task description parameter information ,include:

Determining the order-preserving execution direct memory access task among the multiple direct memory access tasks according to the order-preserving parameter values corresponding to the multiple direct memory access tasks;

The order-preserving execution direct memory access tasks are sorted according to the task loading order, and the order-preserving execution direct memory access task with the highest ranking is determined as the current direct memory access task to be executed.
25. The method according to claim 25, wherein the order-preserving execution direct memory storage of the multiple direct memory access tasks is determined according to the order-preserving parameter values corresponding to the multiple direct memory access tasks. Take tasks, including:

If the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 0, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the plurality of direct memory access tasks is 1, determining that the first direct memory access task is an order-preserving execution direct memory access task;

or

If the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 1, it is determined that the first direct memory access task is a non-order-preserving execution direct memory access task; And if the order-preserving parameter value corresponding to the first direct memory access task among the multiple direct memory access tasks is 0, it is determined that the first direct memory access task is an order-preserving execution direct memory access task.
25. The method according to claim 25, wherein the order-preserving execution direct memory storage of the multiple direct memory access tasks is determined according to the order-preserving parameter values corresponding to the multiple direct memory access tasks. After taking the task, it also includes:

If it is determined that the first direct memory access task among the multiple direct memory access tasks is an order-preserving execution direct memory access task, then the first direct memory access task is pressed into the virtual queue according to the task loading order .
The method according to claim 27, wherein the method further comprises:

When the execution of the direct memory access task currently to be executed is completed, add 1 to the head pointer of the virtual queue;

When a new order-preserving execution direct memory access task is pressed into the virtual queue, the tail pointer of the virtual queue is incremented by one.
The method according to claim 24, wherein the task description parameter information is correspondingly configured with status flag information, and the at least one direct memory access task currently to be executed is determined according to the at least one task description parameter information ,include:

Determine the direct memory access task with the highest execution level according to the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks;

The direct memory access task with the highest execution level is determined as the direct memory access task currently to be executed.
The method according to claim 29, wherein the status flag information includes task effective parameter values, task activation parameter values, and priority parameter values, and the task description parameters of the multiple direct memory access tasks are The status tag information corresponding to the information determines the direct memory access task with the highest execution level, including:

Determine the effective direct memory access task among the multiple direct memory access tasks according to the values of the task effective parameter values corresponding to the multiple direct memory access tasks;

Determine the active direct memory access task in the effective direct memory access task according to the value of the task activation parameter value corresponding to the effective direct memory access task;

Determine the activated direct memory access task with the highest priority according to the value of the priority parameter value corresponding to the activated direct memory access task;

The active direct memory access task with the highest priority is determined as the direct memory access task with the highest execution level.
The method according to claim 29, wherein the status tag information includes a time stamp, and the status tag information corresponding to the task description parameter information of the multiple direct memory access tasks is determined to determine the highest execution level Direct memory access tasks, including:

Determine the activated direct memory access task with the highest priority according to the status flag information corresponding to the multiple direct memory access tasks;

If the activated direct memory access task with the highest priority includes multiple, then according to the multiple timestamps corresponding to the activated direct memory access tasks with the highest priority, the activated direct memory access task with the highest time stamp value is the highest priority. Take the task and determine it as the direct memory access task with the highest execution level.
The method according to claim 30, wherein the effective direct memory of the multiple direct memory access tasks is determined according to the values of the effective parameter values of the tasks corresponding to the multiple direct memory access tasks Access tasks, including:

If the task valid parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an invalid direct memory access task; if the task valid parameter value corresponding to the direct memory access task is 1, then the direct memory access task is determined Take the task as an effective direct memory access task;

or

If the effective parameter value of the task corresponding to the direct memory access task is 1, the direct memory access task is determined to be an invalid direct memory access task; if the task effective parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be 0. Take the task as an effective direct memory access task.
The method according to claim 30, wherein the active direct memory access in the effective direct memory access task is determined according to the value of the task activation parameter value corresponding to the effective direct memory access task Tasks include:

If the task activation parameter value corresponding to the direct memory access task is 0, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 1, then the direct memory is determined The access task is to activate the direct memory access task;

or

If the task activation parameter value corresponding to the direct memory access task is 1, the direct memory access task is determined to be an inactive direct memory access task; if the task activation parameter value corresponding to the direct memory access task is 0, the direct memory is determined The access task is to activate the direct memory access task.
The method according to any one of claims 29 to 33, wherein the method further comprises:

The status tag information corresponding to the task description parameter information of each direct memory access task is stored in the status register.
The method according to claim 34, wherein the status register comprises 4 areas, and the 4 areas respectively store task effective parameter values, task activation parameter values, priority parameter values, and time stamps.
The method according to any one of claims 29 to 35, wherein the method further comprises:

The task description parameter information corresponding to each direct memory access task is stored in the preset priority queue.
The method according to claim 24, wherein the task description parameter information includes interrupt parameter values, and the method further comprises:

After the execution of the direct memory access task is completed, it is determined whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task.
37. The method of claim 37, wherein the judging whether to report an interrupt notification to the reduced instruction set processor according to the value of the interrupt parameter value corresponding to the direct memory access task comprises:

If the interrupt parameter value corresponding to the direct memory access task is 1, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 0, then Determine to report the interrupt notification to the reduced instruction set processor;

or

If the interrupt parameter value corresponding to the direct memory access task is 0, it is determined not to report the interrupt notification to the reduced instruction set processor; if the interrupt parameter value corresponding to the direct memory access task is 1, then It is determined to report the interrupt notification to the reduced instruction set processor.
The method according to any one of claims 24 to 38, wherein the direct memory access unit further comprises at least one task queue, and the correspondence relationship between the task queue and the data path is preset, and the at least one task queue is preset according to the at least one task queue. A task description parameter information, after determining at least one direct memory access task currently to be executed, further includes:

Determine the task queue corresponding to the at least one direct memory access task currently to be executed according to at least one task description parameter information corresponding to the at least one direct memory access task currently to be executed;

According to the corresponding relationship between the task queue and the data path, execute the at least one direct memory access task currently to be executed.
The method according to claim 39, wherein the correspondence between the task queue and the data path comprises: one task queue corresponds to one data path.
The method according to claim 39 or 40, wherein the executing the at least one direct memory access task currently to be executed according to the corresponding relationship between the task queue and the data path comprises:

The at least one direct memory access task currently to be executed is scheduled to the corresponding task queue, and the direct memory access task scheduled to each task queue is allocated to the corresponding task queue according to the corresponding relationship between the task queue and the data path In the data path, the at least one direct memory access task currently to be executed is executed.
The method according to any one of claims 39 to 41, wherein the at least one data path includes reading a large-batch data path, writing a large-batch data path, reading a small-batch data path, and writing a small-batch data path, so The at least one task queue includes a task queue for reading large batches of data, a task queue for writing large batches of data, a task queue for reading small batches of data, and a task queue for writing small batches of data; the task queue for reading large batches of data corresponds to the channel for reading large batches of data , The task queue for writing large-batch data corresponds to the large-batch writing data path, the task queue for reading small-batch data corresponds to the small-batch reading data path, and the task queue for writing small-batch data corresponds to the writing small-batch data path.
42. The method of claim 42, wherein the direct memory access unit is provided in a digital signal processor.
The method of claim 43, wherein the executing the at least one direct memory access task currently to be executed comprises:

If the current direct memory access task to be executed is the task of reading bulk data, the first data corresponding to the task of reading bulk data is read from the external double-rate synchronous dynamic random access memory, and the first data Based on the read bulk data path, the data is transmitted to the internal buffer of the digital signal processor, and the first data is written into the internal buffer;

If the current direct memory access task to be executed is a task of reading small batch data, the second data corresponding to the task of reading small batch data is read from the double-rate synchronous dynamic random access memory, and the second data Based on the read mini-batch data path, the data is transmitted to the data buffer of the digital signal processor, and the second data is written into the data buffer;

If the current direct memory access task to be executed is a task of writing large batch data, the third data corresponding to the task of writing large batch data is read from the internal cache, and the third data is based on the writing large batch data path Transmitting to the double-rate synchronous dynamic random access memory, and writing the third data into the double-rate synchronous dynamic random access memory;

If the current direct memory access task to be executed is a task of writing small batch data, the fourth data corresponding to the task of writing small batch data is read from the data buffer, and the fourth data is based on writing small batch data The channel is transmitted to the double-rate synchronous dynamic random access memory, and the fourth data is written into the double-rate synchronous dynamic random access memory.
A computer-readable storage medium, characterized in that, the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the processor realizes the method described in any one of claims 24 to 44. The multiple direct memory access task processing methods described above.