CN102195891A - Low-power consumption router with control signal for network on chip - Google Patents

Abstract

The invention belongs to the technical field of networks on chip, and particularly discloses a low-power consumption router with a control signal for the network on chip. An ordinary router generally comprises a buffer, a link controller, an arbitrator and an exchange switch. The low-power consumption router is obtained by setting a control circuit and the control signal at an input port of the ordinary router so as to be endowed with a switching-off function. Only when the router of a certain stage is required to transmit data, the control signal of the router is set to be at a high level, and the router is switched on; and the transmission of the data is not required, namely when the forwarding of the data is finished, the control signal is set to be at a low level, and the router is switched off to fulfill the aim of reducing power consumption.

Description

The low-power consumption router that is used for the belt controling signal of network-on-chip

Technical field

The invention belongs to the network-on-chip technical field, be specifically related to a kind of low-power consumption router that is used for network-on-chip.

Background technology

Along with the progress of integrated circuit technology, main product technology in 2010 has been 65nm, also comes out based on the chip of high technology 45nm and 32nm more.(Systom on Chip SoC) can't satisfy growing function and performance index to the uniprocessor SOC (system on a chip), IP kernels such as a plurality of processors and memory cell need be integrated in the chip piece.SoC now mainly with bus realize between each computing module interconnection with communicate by letter.In order to satisfy communication requirement growing on the sheet, bussing technique is also being updated, and develops into the bridge joint of multibus gradually from single shared bus, and then develops more complicated structures such as stratification bus.

When the multiprocessor SOC (system on a chip) (Multi-processor Systom on Chip, when MPSoC) IP in [1] (Intellectual Property) nuclear is more and more, bus structures will be difficult to satisfy following the requirement:

(1) scalability problem.Along with increasing of IP kernel on the sheet, data processing amount also increases at double, and limited address resource will become the bottleneck that enlarges circuit scale.Article one, bus can't support a pair of above node to communicate by letter simultaneously, and efficient is very low.Though the stratification bus can be alleviated this problem, the number of IP kernel further increases (such as up to a hundred) on sheet, seems powerless.

(2) single clock stationary problem.Bus structures require global synchronization but along with the dwindling of technology characteristics size, operating frequency rises rapidly, reaches after the 10GHz, and the influence that Interconnect Delay causes will seriously be set to designing global clock.In addition, huge clock network will occupy most of power consumption of chip.

In order effectively to solve among the following MPSoC communication issue complicated between the multinuclear, use for reference the achievement in research in computer network and parallel computation field, engendered a kind of brand-new method for designing---network-on-chip (Network On Chip, NoC) [3].The Ahmed Hemani of Sweden KTH proposed this notion for the first time in 2000, and was defined: network-on-chip is made of computing unit, memory cell, I/O interface, and the network that connects by router.Dally professor's one piece article the making a start as NoC of part scholar with calendar year 2001 Stanford University also arranged.

Adopt NoC to have the following advantages:

(1) solved line and crossed that Global Asynchronous is adopted in the too big problem of long delay: NoC design, (each processing unit all has the clock zone of oneself to local synchronization for Globally Asynchronous Locally Synchronous, mechanism GALS); And can close some temporary transient no module as required, reduce power consumption.

(2) remedy integrated circuit (Integrated Circuits, IC) technology of design and manufacturing is poor: comprehensive and technique of compiling lags behind the development of IC manufacturing technology, formed so-called " price scissors ", this just makes more massive chip of redesign difficult more, and the mode of employing network-on-chip, by reusing a lot of existing module of software and hardware, can obviously improve desin speed, shorten the design cycle.

(3) zmodem: chip is as an organic whole, if one of them parts misplaces, may make entire chip at a standstill, and use network-on-chip, the parts of makeing mistakes can replace with other identical parts, make entire chip can continue operate as normal.

(4) be applicable to polycaryon processor: the bus in the multiple nucleus system is subjected to bandwidth constraints, and bottleneck has appearred in autgmentability.Network-on-chip utilizes the traditional computer network concept to manage data communication between a plurality of IP kernels, not only has better extensibility, concurrency, and can avoid long line, and the line between the unit is very short, becomes the developing direction of system-on-a-chip.

(5) on-chip interconnect of each processing unit generally all passes through a router, and it is a requisite module in the interference networks, is used to connect the transmission line and the transmission means of each processing unit, determination data.Designing a kind ofly can provide quick Communications service, and the router that can reduce used area, power consumption again is based on one of hot research content interconnected on the sheet of mesh structure.

The transmission of data realizes that by packet (process element PE) sends a packet to adjacent router (Router) to the source processing unit, and packet propagates into the target processing unit through the forwarding of router.A packet (packet) comprises packet header, indentured, bag tail, as shown in Figure 2, and the microplate (flit) in each periodic transfer packet.A packet generally comprises tens microplates, and number can be fixed also and can not fixed, and the microplate number has a strong impact on the bag transmission delay.

As shown in Figure 3, router is generally by constitute (different routing algorithms, network configuration, current control mode have different formations) with lower module:

(1) buffer (buffer): (first-in first-out, FIFO) mode is stored data, the general parallel several buffers (also claim pseudo channel, will introduce below) of placing to adopt first in first out.Buffer can be placed on input port or output port, but different placements may have different performances.

(2) (Link Controller, LC), whether decision allows to transmit data to link controller, full or when be empty as the FIFO storage, then stops to continue to receive or the transmission data.

(3) which channel moderator (Arbiter) determines to transmit data and which channel is the data of importing router into should select as input.

(4) alteration switch (switch or title crossbar), which delivery channel the decision input channel can select as output port.

But router occupies than large tracts of land in the network-on-chip, and consumes big power consumption.

List of references

[1] Ahmed?Amine?Jerraya,?Wayne?Wolf.?Multiprocessor?System-on-Chips?.Morgan?Kaufmann,?2005

[2] WOLFW,JERRAYAA,MARTING.Multiprocessorsystem-on-chip(MPSoC)technology[J]?.IEEE?Transactions?on?Computer-Aided?Design?of?Integrated?Circuits?and?Systems,?2008,?27?(10)?:1701-1713?.

[3] Kim?J,Nicopoulos?C,Park?D.?A?gracefully?degradingand?energy-efficient?modular?router?architecture?for?on-chip?networks[C]?.Proceedings?of?the?33rd?AnnualInternational?Symposium?on?Computer?Architecture.?Boston:?IEEE,?2006,?:4-15?.

[4] Das?R,Mishra?A?K,Nicopoulos?Cet?al.?Performance?andpower?optimization?through?data?compression?in?network-on-chip?architectures[C]?.Proceedings?of?the?14th?Inter-national?Symposium?on?High?Performance?Computer?Archi-tecture.?Salt?Lake?City:?IEEE,?2008,?:215-225?.

[5] Alameldeen?A?R,Wood?D?A.?Interactions?between?com-pression?and?prefetching?in?chip?multiprocessors[C]?.Proceedings?of?the?13th?International?Symposium?onHigh-Performance?Computer?Architecture.?Phoenix:?IEEE,?2007,?:228-239?。

Summary of the invention

The object of the present invention is to provide a kind of router topology that can effectively reduce the network-on-chip router power consumption.

Based on above goal of the invention, the present invention proposes a kind of router topology of belt switch control circuit.Promptly add a control circuit and control signal at common router input port, the work that plays shutoff or unlatching router is in order to reduce power consumption.If EN is an enable signal, CLK is a clock signal, uses latch to suppress burr.

Specifically, common router is generally by constituting with lower module: (Link Controller LC), moderator (Arbiter), alteration switch (switch or claim crossbar), sees shown in Figure 3 for buffer (buffer), link controller.

Low-power consumption router of the present invention, only when certain level-1 router need transmit data, its control signal was put high level, and router is opened.When not having data to transmit, when promptly data forwarding finished, control signal was put low level, turn-offed router, reached the purpose that reduces power consumption.

Whether low-power consumption router of the present invention is that sky is judged whether data that the upper level routing unit sends to routing unit at the corresponding levels are transmitted and finished by the detection buffer state.

Low-power consumption router of the present invention, the idiographic flow of its transfer of data is:

When (1) certain one-level routing unit output port receives from input port request to send signal at the same level, adopt repeating query mechanism to determine output channel number and judge the operating state of next stage routing unit;

(2) if the next stage routing unit input port that connects is in running order, then begin to send request signal and data;

(3) if be in closed condition, then control signal is put ' 1 ', open the clock signal of this input port, and begin to send request signal and data;

(4) receive and finish when next stage input link control section detects the transmission of upper level routing unit by an effective data packets of this input port, and this moment, the request from the upper level routing unit was ' 0 ', then control signal is put ' 0 ', interrupt the clock signal of this input port.

Traditional router is realized the storage forwarding capability of signal, and when usage quantity was few, power consumption still can be accepted.Yet in network-on-chip, need a large amount of routers (router of each resource node band) that use, power problems is very outstanding.The router of belt switch control circuit proposed by the invention can address this problem effectively.

Description of drawings

Fig. 1 is the router-module of belt controling signal.

Fig. 2 is the composition of packet.

Fig. 3 is the main composition module of router.

Embodiment

When upper level routing unit output port receives from input port request to send signal at the same level, adopt repeating query mechanism to determine output channel number and judge the operating state of next stage routing unit.

If the next stage routing unit input port that connects is in running order, then begin to send request signal and data; If be in closed condition, then control signal is put ' 1 ', open the clock signal of this input port, and begin to send request signal and data.

Next stage input link control section receives the transmission request from the previous stage routing unit, and provides corresponding answer signal, promptly begins log-on data and receives and storage process.Route is handled answer signal and is shown that not only the route computing finishes, also indicate a new packet wait to be sent, transmit control section this moment and handle to reply by the monitoring route and come log-on data to send process, according to Virtual Channel number and cache location reading of data and transmission with the Virtual Channel buffer status.

When detecting fifo status, next stage input link control section becomes sky, and the output port corresponding at the same level of being asked is forwarded to next stage smoothly with data, illustrate that the upper level routing unit finishes by the transmission reception of an effective data packets of this input port, if this moment, the request from the upper level routing unit was ' 0 ', control signal is put ' 0 ', interrupt the clock signal of this input port.

Claims (4)

1. a low-power consumption router that is used for the belt controling signal of network-on-chip is characterized in that adding lastblock control circuit and a control signal on the basis of common router, makes router possess the function of shutoff.

2. low-power consumption router according to claim 1 only is characterized in that when certain level-1 router need transmit data, its control signal was put high level, and router is opened; When not having data to transmit, when promptly data forwarding finished, control signal was put low level, turn-offed router, reached the purpose that reduces power consumption.

3. the low-power consumption router that is used for network-on-chip according to claim 2 is characterized in that by the detection buffer state whether being that sky is judged whether data that the upper level routing unit sends to routing unit at the corresponding levels are transmitted and finished.

4. the low-power consumption router that is used for network-on-chip according to claim 3 is characterized in that the idiographic flow of transfer of data is:

When (1) certain one-level routing unit output port receives from input port request to send signal at the same level, adopt repeating query mechanism to determine output channel number and judge the operating state of next stage routing unit;

(2) if the next stage routing unit input port that connects is in running order, then begin to send request signal and data;

(3) if be in closed condition, then control signal is put ' 1 ', open the clock signal of this input port, and begin to send request signal and data;

(4) receive and finish when next stage input link control section detects the transmission of upper level routing unit by an effective data packets of this input port, and this moment, the request from the upper level routing unit was ' 0 ', then control signal is put ' 0 ', interrupt the clock signal of this input port.

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