CN118069580B - Synchronization method for recording information by using two ping-pong caches through double CPUs - Google Patents
Synchronization method for recording information by using two ping-pong caches through double CPUs Download PDFInfo
- Publication number
- CN118069580B CN118069580B CN202410481929.4A CN202410481929A CN118069580B CN 118069580 B CN118069580 B CN 118069580B CN 202410481929 A CN202410481929 A CN 202410481929A CN 118069580 B CN118069580 B CN 118069580B
- Authority
- CN
- China
- Prior art keywords
- cpu
- cpus
- caches
- cache
- pong
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 23
- 239000000872 buffer Substances 0.000 claims description 30
- 238000011282 treatment Methods 0.000 claims description 6
- 230000000694 effects Effects 0.000 abstract description 2
- 238000012545 processing Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
The invention provides a synchronization method for recording information by using two ping-pong caches by using two CPUs, which is characterized in that the two CPUs set values in a shared register, periodically check the change of the values and check whether a switching flag is lifted to judge whether a certain CPU needs to perform cache switching or not so as to ensure that the two CPUs use the same cache in the ping-pong caches at the same time, avoid the influence of an interrupt mode used in the prior art on the operation of the CPUs and improve the operation effect of the two CPUs.
Description
Technical Field
The invention relates to the technical field of CPU read-write caching, in particular to a method for synchronizing recorded information of two ping-pong caches by using double CPUs.
Background
When two CPUs independently operate, record information is needed to be stored, so that analysis is convenient when problems occur. The two CPUs are independently operated but have an operation relationship dependent on each other, so that if the information is independently stored, the relevance cannot be found out from the information after long-time testing. It is therefore necessary to synchronize the information stored by the two CPUs in the same cache area for analysis.
Because of the limitation of the buffer size space, the information is stored in NAND FLASH again and again, so that two ping pong buffers (ping pong buffers) are used for switching, so that the information in the second block buffer can be synchronously written into NAND FLASH without being influenced while two CPUs record the information into the first block buffer. Synchronization is required between the two CPUs.
In the prior art, when two CPUs need to communicate, an interrupt (interrupt) mode is generally used to make a notification, but when the interrupt is triggered, the CPU temporarily puts down the task at hand to check the interrupt state and then jump back to process the current event, which may cause the following problems: firstly, the CPU may be currently processing more important work, so that the current important processing work is likely to be influenced by interruption; and secondly, the stored information does not need to be immediately executed in an emergency state.
In view of the above-mentioned drawbacks, there is a need to design a method for synchronizing information recorded by two ping-pong caches by using two dual CPUs, so as to solve the above-mentioned problems, ensure writing by using the same cache, and improve CPU processing efficiency.
Disclosure of Invention
In order to solve the problems mentioned in the foregoing, the present invention proposes a synchronization method for recording information by using two ping-pong caches by using two CPUs, which uses registers to realize that two CPUs synchronously use ping-pong caches, that is, keep writing by using the same cache, thereby improving CPU efficiency.
A synchronization method for recording information by using two pieces of ping-pong caches by using a double CPU is characterized by comprising the following steps: the two CPUs judge whether the caches written by the two CPUs at present need to be switched to synchronously use ping-pong caches by periodically checking the value of the shared register, and the same block of caches is kept to be used for writing.
Further, the method specifically comprises the following steps:
Step 1, preparing a block of registers which can be read by two CPUs as a shared register, wherein the two CPUs respectively use a certain 1B space in the shared register;
step 2, preparing two caches as ping-pong caches;
And 3, any CPU checks the value of the shared register every several seconds to judge whether the CPU needs to switch the currently written cache.
Further, the step 3 specifically includes:
step 3-0, executing step 3-1 every several seconds;
Step 3-1, detecting whether the values set by the CPU and the other CPU in the shared register are the same; if the two types are different, the fact that a certain CPU has completed the buffer switching is indicated, and step 3-2 is executed; if the two CPUs are identical, the two CPUs are using the same block of cache, and the cache is not required to be switched at the moment, the step 3-5 is executed;
Step 3-2, checking whether the flag switched by the CPU is lifted or not; if not, the other CPU completes the buffer switching, and then step 3-3 is executed; if yes, the other CPU does not perform cache switching, and step 3-4 is executed;
step 3-3, the CPU writes an end character string in the current buffer memory: 0xffff, then modifying the value in the shared register, switching to another block of cache, and ending the step 3;
Step 3-4, the CPU does not perform cache switching, and the step 3 is ended;
Step 3-5, checking whether the flag switched by the CPU is lifted or not; if yes, the other CPU is indicated to finish the buffer switch, and then the step 3-6 is executed; if not, executing the step 3-4;
and 3-6, clearing the flag switched by the CPU, and ending the step 3.
Further, the interval of several seconds is specifically 5 seconds.
Further, the method further includes step4, where step4 is started after step 2 is completed, specifically:
Step 4-1, checking the value of the shared register after any CPU records a plurality of data, then executing step 3-1 until step 3 is finished, and then executing step 4-2;
step 4-2, detecting whether the current buffer memory of the CPU only has two spaces in which data can be recorded, if so, executing step 4-3; if not, executing the step 4-7;
Step 4-3, recording the data after the current buffer, and recording an end character string: 0xffff, then checking whether the flag switched by the CPU is lifted, and if so, executing the step 4-4; if not, executing the step 4-5;
Step 4-4, checking again whether the values set by the CPU and the other CPU in the shared register are the same, if so, indicating that the other CPU has completed the buffer switching, and the other buffer can be used, executing step 4-5; if not, executing the step 4-6;
Step 4-5, the CPU performs cache switching, then lifts the flag switched by the CPU, continues to record data, and ends the step 4;
Step 4-6, carrying out additional treatment, and ending the step 4;
And 4-7, the CPU writes the data to be recorded into the current cache, and the step 4 is ended.
Further, the additional treatments are: firstly, information to be stored is placed at a local end of a system, and after a space is cached, the information is placed in a cache.
Further, the number of data per record is specifically 10 data per record.
The beneficial effects of the invention are as follows:
1. The method of the invention judges whether a certain CPU needs to carry out buffer switching or not by setting the value in the shared register by the double CPUs, periodically checking the change of the value and checking whether the switching flag is lifted, so as to ensure that the double CPUs use the same buffer in the ping-pong buffer at the same time, avoid the influence of the interrupt mode used in the prior art on the operation of the CPU and improve the operation effect of the double CPUs.
2. The method further adopts a mode of periodically checking the residual space of the buffer to judge whether one CPU needs to perform buffer switching, and further ensures that the double CPUs use the same buffer in the ping-pong buffer at the same time.
Drawings
Fig. 1 is a schematic flow chart of step 3 in the embodiment of the invention.
Fig. 2 is a schematic flow chart of step 4 in the embodiment of the invention.
Detailed Description
The invention is further described below with reference to examples.
The following examples are illustrative of the present invention but are not intended to limit the scope of the invention. The conditions in the examples can be further adjusted according to specific conditions, and simple modifications of the method of the invention under the premise of the conception of the invention are all within the scope of the invention as claimed.
Example 1,
A synchronization method for recording information by using two pieces of ping-pong caches by two CPUs judges whether the caches currently written by the two CPUs need to be switched to synchronously use the ping-pong caches by periodically checking the value of a shared register, and keeps writing by using the same piece of cache.
The method specifically comprises the following steps:
Step 1, preparing a U32-sized register which can be read by two CPUs as a shared register, wherein the two CPUs respectively use a certain 1B space in the shared register. The two CPUs are respectively front-end CPUs in this embodiment: FE and backend CPU: BE.
Step 2, preparing two caches with the size of 64K as ping-pong caches. Wherein the FE uses the first 16k and the BE uses the last 48k, and the actual allocation size can BE estimated according to the normal flow.
Step 3, any CPU checks the value of the shared register every 5 seconds (the time can be customized) to judge whether the CPU needs to switch the currently written cache; as shown in fig. 1, the step 3 specifically includes:
step 3-0, executing step 3-1 every 5 seconds.
Step 3-1, detecting whether the values set by FE and BE in the shared register are the same; if the two types are different, the fact that a certain CPU has completed the buffer switching is indicated, and step 3-2 is executed; if the same indicates that both CPUs are using the same block of cache, no cache switch is needed, step 3-5 is performed.
Step 3-2, checking whether the flag of the FE switch is lifted; if not, the BE completes the cache switch, and then step 3-3 is executed; if so, the step 3-4 is performed if the BE indicates that the BE has not performed the cache switch.
Step 3-3, the FE writes an end character string in the current cache: 0xffff, then modifying the value in the shared register and switching to another block cache, ending step 3.
And 3-4, the FE does not perform cache switching, and the step 3 is ended.
Step 3-5, checking whether the FE switched flag is lifted or not; if yes, the BE also completes the cache switch, and then step 3-6 is executed; if not, step 3-4 is performed.
And 3-6, clearing the FE switching flag, and ending the step 3.
On the basis of example 1, the invention also provides example 2.
The method of the present invention further includes step 4, where step 4 is performed after step 2 is completed, as shown in fig. 2, specifically:
Step 4-1, wherein any CPU checks the value of the shared register after recording 10 (customizable) data, then step 3-1 is executed until step 3 is finished, and then step 4-2 is executed.
Step 4-2, detecting whether the current cache of the FE only has two spaces in which data can be recorded, and if so, executing step 4-3; if not, step 4-7 is performed.
Step 4-3, recording the data after the current buffer, and recording an end character string: 0xffff, then checking whether the FE-switched flag is lifted, and if so, executing step 4-4; if not, step 4-5 is performed.
Step 4-4, checking whether the values set by FE and BE in the shared register are the same again, if so, indicating that the BE has completed the cache switching, and executing step 4-5 if another cache can BE used; if not, step 4-6 is performed.
And 4-5, performing cache switching on the FE, lifting the flag switched by the FE, continuing to record data, and ending the step 4.
Step 4-6, carrying out additional treatment, and ending the step 4; it is currently possible that both caches cannot be used. Additional treatments are needed, which are: firstly, information to be stored is placed at a local end of a system, and after a space is cached, the information is placed in a cache.
And 4-7, the FE writes the data to be recorded into the current cache, and the step 4 is ended.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims and their equivalents.
Claims (5)
1. A synchronization method for recording information by using two pieces of ping-pong caches by using a double CPU is characterized by comprising the following steps: the two CPUs judge whether the caches written by the two CPUs at present need to be switched to synchronously use ping-pong caches by periodically checking the value of the shared register, and the same block of cache is kept to be used for writing;
The method specifically comprises the following steps:
Step 1, preparing a block of registers which can be read by two CPUs as a shared register, wherein the two CPUs respectively use a certain 1B space in the shared register;
step 2, preparing two caches as ping-pong caches;
Step 3, any CPU checks the value of the shared register every several seconds to judge whether the CPU needs to switch the currently written cache;
the step 3 specifically comprises the following steps:
step 3-0, executing step 3-1 every several seconds;
Step 3-1, detecting whether the values set by the CPU and the other CPU in the shared register are the same; if the two types are different, the fact that a certain CPU has completed the buffer switching is indicated, and step 3-2 is executed; if the two CPUs are identical, the two CPUs are using the same block of cache, and the cache is not required to be switched at the moment, the step 3-5 is executed;
Step 3-2, checking whether the flag switched by the CPU is lifted or not; if not, the other CPU completes the buffer switching, and then step 3-3 is executed; if yes, the other CPU does not perform cache switching, and step 3-4 is executed;
step 3-3, the CPU writes an end character string in the current buffer memory: 0xffff, then modifying the value in the shared register, switching to another block of cache, and ending the step 3;
Step 3-4, the CPU does not perform cache switching, and the step 3 is ended;
Step 3-5, checking whether the flag switched by the CPU is lifted or not; if yes, the other CPU is indicated to finish the buffer switch, and then the step 3-6 is executed; if not, executing the step 3-4;
and 3-6, clearing the flag switched by the CPU, and ending the step 3.
2. The method for synchronizing information recorded by two ping-pong caches by using two CPUs according to claim 1, wherein: the intervals are in particular 5 seconds.
3. The method for synchronizing information recorded by two ping-pong caches by using two CPUs according to claim 1, wherein: the method further comprises a step 4, wherein the step 4 starts to be executed after the step 2 is completed, specifically:
Step 4-1, checking the value of the shared register after any CPU records a plurality of data, then executing step 3-1 until step 3 is finished, and then executing step 4-2;
Step 4-2, detecting whether the current buffer memory of the CPU only has two spaces in which data can be recorded, if so, executing step 4-3; if not, executing the step 4-7;
step 4-3, recording the next data after the current buffer, and recording an end character string: 0xffff, then checking whether the flag switched by the CPU is lifted, and if so, executing the step 4-4; if not, executing the step 4-5;
step 4-4, checking again whether the values set by the CPU and the other CPU in the shared register are the same, if so, indicating that the other CPU has completed the buffer switching, and the other buffer can be used, executing step 4-5; if not, executing the step 4-6;
Step 4-5, the CPU performs cache switching, then lifts the flag switched by the CPU, continues to record data, and ends the step 4;
Step 4-6, carrying out additional treatment, and ending the step 4;
And 4-7, the CPU writes the data to be recorded into the current cache, and the step 4 is ended.
4. A method for synchronizing information recorded by two ping pong caches by using two CPUs according to claim 3, wherein: the additional treatments were: firstly, information to be stored is placed at a local end of a system, and after a space is cached, the information is placed in a cache.
5. A method for synchronizing information recorded by two ping pong caches by using two CPUs according to claim 3, wherein: the number of data per record is specifically 10 data per record.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410481929.4A CN118069580B (en) | 2024-04-22 | 2024-04-22 | Synchronization method for recording information by using two ping-pong caches through double CPUs |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410481929.4A CN118069580B (en) | 2024-04-22 | 2024-04-22 | Synchronization method for recording information by using two ping-pong caches through double CPUs |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN118069580A CN118069580A (en) | 2024-05-24 |
| CN118069580B true CN118069580B (en) | 2024-06-28 |
Family
ID=91095855
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202410481929.4A Active CN118069580B (en) | 2024-04-22 | 2024-04-22 | Synchronization method for recording information by using two ping-pong caches through double CPUs |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN118069580B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104239232A (en) * | 2014-09-10 | 2014-12-24 | 北京空间机电研究所 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
| CN109582480A (en) * | 2018-12-09 | 2019-04-05 | 江苏华存电子科技有限公司 | A kind of UART master control system that can automatically switch to send data source outside in multicore scene |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3954248B2 (en) * | 1999-08-12 | 2007-08-08 | 富士通株式会社 | Testing method for information processing apparatus |
| CN105550156B (en) * | 2015-12-02 | 2018-08-07 | 浙江大华技术股份有限公司 | A kind of method and device of time synchronization |
| CN110532110A (en) * | 2019-08-27 | 2019-12-03 | 江苏华存电子科技有限公司 | A kind of UART master control system for automatically switching to send data outside in multicore scene |
-
2024
- 2024-04-22 CN CN202410481929.4A patent/CN118069580B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104239232A (en) * | 2014-09-10 | 2014-12-24 | 北京空间机电研究所 | Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array) |
| CN109582480A (en) * | 2018-12-09 | 2019-04-05 | 江苏华存电子科技有限公司 | A kind of UART master control system that can automatically switch to send data source outside in multicore scene |
Also Published As
| Publication number | Publication date |
|---|---|
| CN118069580A (en) | 2024-05-24 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7325112B2 (en) | High-speed snapshot method | |
| US7475202B2 (en) | Memory controller and method for optimized read/modify/write performance | |
| US20080201615A1 (en) | Apparatus and computer program product for implementing atomic data tracing | |
| CN109669635B (en) | Command LBA (logical block addressing) coincidence detection method and device for solid-state storage master control chip | |
| CN107145301B (en) | Data access method and device based on hybrid disk | |
| US6240489B1 (en) | Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system | |
| CN108182151B (en) | Method, apparatus, storage medium and the terminal device of sequential flow caching and detection | |
| CN118069580B (en) | Synchronization method for recording information by using two ping-pong caches through double CPUs | |
| CN100484047C (en) | Data cache system and method | |
| CN103176753B (en) | Storing device and data managing method thereof | |
| CN113109778A (en) | Multi-system radar preprocessing implementation method based on interrupt response mechanism | |
| GB2531105A (en) | Implementing enhanced performance with read before write to phase change memory to avoid write cancellations | |
| CN116701246A (en) | Method, device, equipment and storage medium for improving cache bandwidth | |
| US11768778B2 (en) | Re-reference indicator for re-reference interval prediction cache replacement policy | |
| JP3767521B2 (en) | Cache fill control method and CPU | |
| JPH05233155A (en) | Disk array device | |
| JP3962853B2 (en) | Memory data error correction method | |
| CN113507610B (en) | Method and device for multi-path concurrent decoding of JPG image by master-slave system | |
| CN116244223A (en) | Data page management method, system, equipment and storage medium | |
| CN110058783B (en) | Temporary memory processing method, temporary memory program and storage device | |
| CN113655949B (en) | PM-based database page caching method and system | |
| KR100817203B1 (en) | Method for reading data of a nonvolatile storage device | |
| CN116610596B (en) | Memory device and data processing method thereof | |
| JPH11265262A (en) | High speed write cache disk device | |
| CN110688155A (en) | Merging method for storage instruction accessing non-cacheable area |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |