CN101697491B - Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM - Google Patents

Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM Download PDF

Info

Publication number
CN101697491B
CN101697491B CN2009101533341A CN200910153334A CN101697491B CN 101697491 B CN101697491 B CN 101697491B CN 2009101533341 A CN2009101533341 A CN 2009101533341A CN 200910153334 A CN200910153334 A CN 200910153334A CN 101697491 B CN101697491 B CN 101697491B
Authority
CN
China
Prior art keywords
branch road
sdram
address
data
dein
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CN2009101533341A
Other languages
Chinese (zh)
Other versions
CN101697491A (en
Inventor
谢磊
陈惠芳
李珊
王匡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Zhejiang University ZJU
Original Assignee
Zhejiang University ZJU
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Zhejiang University ZJU filed Critical Zhejiang University ZJU
Priority to CN2009101533341A priority Critical patent/CN101697491B/en
Publication of CN101697491A publication Critical patent/CN101697491A/en
Application granted granted Critical
Publication of CN101697491B publication Critical patent/CN101697491B/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Landscapes

  • Error Detection And Correction (AREA)

Abstract

The invention relates to a method for realizing convolution interleaving and de-interleaving of a time domain by using an SDRAM. The prior art has disadvantages. In the method, during interleaving, each interleaved subcircuit is operated according to a sequence of reading before writing, and when the left units, namely the difference between the maximum storage capacity addresses and the relative addresses in the current subcircuit, are not enough, the interleaved data is divided into sections to be read and written; and during de-interleaving, each subcircuit is also operated according to the sequence of reading before writing. The method continuously performs address reading and writing on interleaved data of each interleaved subcircuit according to a subcircuit sequence to effectively reduce the time consumed by controlling the SDRAM to frequently searching addresses in the whole interleaving and de-interleaving process and uses the SDRAM to substitute for an FIFO register to further save resources. In addition, the method performs operation of centralized refresh on the SDRAM and cancels the complex stop operation on the SDRAM so as to avoid influence on the continuity of data transmission.

Description

A kind of use SDRAM realizes time domain convolutional interleave reconciliation interweaving method
Technical field
The invention belongs to the digital communication field that interweaves, relate to and in the digital television broadcasting transmission, use SDRAM (synchronous DRAM) to realize that the transmission data are carried out the time domain convolutional interleave conciliates interweaving method.
Background technology
Interweaving is an indispensable part in the GSM.The effect of interleaver is that the sending order of data or data block is upset, and purpose is to reduce the burst error that data or data block occur in transport process.On the contrary, the effect of deinterleaver is that the data sequence of originally upsetting is reverted to original data sequence.
Convolutional interleave is a kind of of interleaving technology.The memory capacity that typical convolutional deinterleaver needs is B * (B-1) * M/2 symbolic unit, and wherein variable B representes the number of branches that interweaves, and variable M representes the delay period that interweaves.Just used convolutional interleave in the DTMB standard of country and interweaved as time domain, wherein B is 52 branch roads, and M is 240 or 720 symbols.
Fig. 1 has represented the principle of convolutional deinterleaver and deinterleaver.The incoming symbol data of interleaver input get into B bar finger device in order respectively, and each road postpones different symbol periods, and the first via does not have delay; The second the tunnel postpones M symbol period; The second the tunnel postpones 2M symbol period ..., the B road postpones (B-1) M symbol period.The output of interleaver is pressed the work tempo of input and is exported the data of corresponding branch road through postponing respectively synchronously.The delay period and the interleaver of each branch road of deinterleaver are opposite, and the first via postpones (B-1) M symbol period, and the second the tunnel postpones (B-2) M symbol period ..., the B road does not then have delay.
When B and M value are big, use the on-chip memory resource consumption excessive, adopt that cost is low, capacity is big, fast SDRAM is scheme preferably.SDRAM utilizes the multiplexing technology access chip internal unit of rank addresses, has adopted many bodies (Bank) memory construction and burst mode, can transmit a monoblock rather than one piece of data continuously, in high-speed data acquistion system, has very big using value.
Utilize SDRAM to carry out data write, need some clock cycle gating rank addresses, and for keeping the data on the SDRAM not lose, must periodic refreshing.SDRAM mode of operation efficiently just is to make each same lines data of removing to read and write continuation address as much as possible in memory cell, and time is with regard to the less time that only accounted for like this.When data are transmitted in discontinuous address, because need consuming the long time, SDRAM is used for the gating address, so can cause the performance of SDRAM to reduce greatly.
Summary of the invention
The purpose of this invention is to provide a kind of use SDRAM and realize time domain convolutional interleave reconciliation interweaving method.
The inventive method comprises time domain convolutional interleave method and the realization time domain convolution de-interleaving method of realizing.
The concrete steps that realize time domain convolutional interleave method among the present invention are:
When step I. calculates frame data and interweaves in every interweaves branch road the required symbolic number T that interweaves (i):
Figure GSB00000870175100021
Wherein L is the length of Frame, a B way that is to interweave, i be current branch road number (i=0,1,2 ..., B-1), mod is complementation.
Step II. when calculating frame data and interweaving at the initial address in_addr of every the branch road that interweaves (i):
in_addr(i)＝in_bs(i)+in_bn(i)，i＝1，2，...，B-1；
Wherein in_bs (i) is the first address of i branch road in SDRAM, and in_bn (i) is the relative address in the i branch road.
The 0th branch road that interweaves is straight-through branch road, and without SDRAM, the first address in_bs (1) of the 1st branch road in SDRAM is Unit 0, then:
in_bs(i)＝in_bs(i-1)+temp1(i)-M，i＝2，3，...，B-1；
Temp1 (i)=temp1 (i-1)+M wherein, temp1 (1)=M, M representes the delay period that interweaves.
When interleaving data was first frame data, the in_bn of each branch road (i) was 0, when interleaving data is not first frame data, then
in_bn(i)＝(in_bn p(i)+T(i))mod(iM)，i＝1，2，...，B-1；
In_bn wherein p(i) expression former frame interleaving data is visited the relative address in the i bar branch road.
Step II I. calculates the address of the SRAM (static random access memory) that deposits the front and back Frame that interweaves.
When interweaving, the individual data of the T that the i branch road need interweave (i) will obtain from the individual unit of T (i) the SRAM1 that deposits interleaving data frame not; The individual data of T after this branch road interweaves (i) will deposit in the individual unit of T (i) of the SRAM2 that deposits the back Frame that interweaves.This moment, the individual read/write address of T (i) of SRAM1 and SRAM2 was identical, and the corresponding i branch road that interweaves is: i, and B+i, 2B+i ..., (T (i)-1) B+i, i=1,2 ..., B-1.
Step IV. the 0th branch road that interweaves, current branch road i=0, promptly straight-through branch road directly passes to address location identical the SRAM2 with interleaving data from SRAM1, and the address of the individual data of T (0) in two SRAM is 0, B, 2B ..., (T (0)-1) B.
Step V. gets into next bar branch road that interweaves, i=i+1; Obtain the initial address in_addr (i) that the place branch road interweaves in SDRAM.Judge whether the relative address in_bn (i) in the branch road of place enough has T (i) individual apart from the residue unit of branch road maximum storage capacity address in_bm (i), in_bm (i)=iM wherein, if enough, execution in step VI then; If not enough, need be divided into twice to interweaving of this branch road and interweave the read-write stage, order is initialized as 0 marking signal in_step and equals 1, execution in step VII.
Step VI. specifies among the SDRAM amount of reading and writing data Tin=T (i) continuously, and the first address in_sa that interweaves of SDRAM is in_addr (i), carries out step VIII.
The data volume that the step VII. phase I reads and writes is T1 (i), is the residue unit number of the relative address in the current branch road that interweaves to branch road maximum storage capacity address, that is:
T1(i)＝in_bm(i)-in_bn(i)；
Specify among the SDRAM amount of reading and writing data Tin=T1 (i) continuously, the first address in_sa that interweaves of SDRAM is in_addr (i), carries out step VIII.
Step VIII. operates by " write-after-read " for each branch road that interweaves in SDRAM.Read at first that first address is continuous T in the location contents that in_sa begins among the SDRAM; Deposit in Tin the unit of SRAM2; Tin the Tin of symbol content from the SRAM1 unit that need are interweaved obtains, and at last these data that need interweave being write first address among the SDRAM continuously is in continuous T in the unit beginning of in_sa.
Step IX. judges that whether the amount of the reading and writing data Tin of SDRAM equals the data volume T (i) that this branch road should interweave, if identical, then carries out step XI; If inequality, the value of continuation judgement symbol signal in_step is if equal 1 with regard to execution in step X, if be not equal to 1, execution in step XI.
The data volume of step X. second stage read-write is T2 (i), for the phase I is read and write the data volume that the back residue that finishes need interweave, that is:
T2(i)＝T(i)-T1(i)；
This moment, the first address that interweaves of SDRAM became this branch road first address in_bs (i).Specify among the SDRAM amount of reading and writing data Tin=T2 (i) continuously, the first address in_sa that interweaves of SDRAM is in_bs (i), and marking signal in_step=0 carries out step VIII.
Step XI. is to the interweaving after all read-write finishes of the current branch road that interweaves, and judges that whether current branch road is the last item branch road that interweaves, if then forward step XII to, if not, forward step V to.
Step XII. interweaves to all behind the branch road end of operation; Can not lose for guaranteeing the data in SDRAM; Adopt to concentrate among the present invention and refreshes, that promptly behind the frame data that interweave, concentrates refreshes several rows, does not refresh and in interleaving data frame process, do not interrupt interlace operation.Be no more than the recognized standard 64ms as long as guarantee the refresh cycle of every row.Concentrate that to refresh line number be the line number of employed SDRAM memory cell of interweaving.Concentrate refresh end after, the order that interweaves of system wait next frame data.
The concrete steps that realize time domain convolution de-interleaving method among the present invention are:
The symbolic number T (i) ' of required deinterleaving in every deinterleaving branch road when step 1. is calculated a frame data deinterleaving:
Figure GSB00000870175100031
Wherein L ' is the length of deinterleaved data frame, and B ' props up way for deinterleaving, and j is the current branch road of deinterleaving number, j=0, and 1,2 ..., B '-1, mod are complementation.
When step 2. is calculated a frame data deinterleaving at the initial address dein_addr of every deinterleaving branch road (j):
dein_addr(j)＝dein_bs(j)+dein_bn(j)；
Wherein dein_bs (j) is the first address of j branch road in SDRAM, and dein_bn (j) is the relative address in the j branch road.
Specifying the first address dein_bs (0) of the 0th branch road in SDRAM is Unit 0, removes B '-1 branch road and is straight-through branch road, and outside SDRAM, other branch roads do
Dein_bs (j)=dein_bs (j-1)+temp2 (j)+(B '+1) M '; Wherein: temp2 (j)=temp2 (j-1)-M ', temp2 (0)=-M ', M ' expression deinterleaving delay period.
When deinterleaved data was first frame data, the dein_bn of each branch road (j) was 0.When deinterleaved data is not first frame data, then:
dein_bn(j)＝(dein_bn p(j)+T(j)′)mod((B′-1-j)M′)；
Dein_bn wherein pRelative address when (j) expression former frame deinterleaved data is visited j bar branch road.
Step 3. is calculated the address of the SRAM that deposits deinterleaving front and back Frame.
During deinterleaving, the j branch road needs the individual data of T (j) ' of deinterleaving to obtain from the individual unit of the T the SRAM1 that deposits the deinterleaved data frame (j) '.The individual data of T (j) ' after this branch road deinterleaving will deposit in the individual unit of T (j) ' of depositing the SRAM2 ' of Frame after the deinterleaving; This moment, the individual read/write address of T (j) ' of SRAM1 ' and SRAM2 ' was the same, and corresponding j deinterleaving branch road is:
j，B′+j，2B′+j，...，(T(j)′-1)B′+j，i＝1，2，...，B′-1；
Step 4. convolution de-interleaving begins, mark branch road j=0.
Step 5. obtains the initial address dein_addr (j) of place branch road deinterleaving; Judge whether branch road interior relative address dein_bn (j) in place enough has T (j) ' individual apart from the residue unit of branch road maximum storage capacity address dein_bm (j); Wherein dein_bm (j)=(B '-j-1) M ', if enough, then execution in step 6; If it is not enough; Need be divided into twice deinterleaving read-write stage to the deinterleaving of this branch road, specify to be initialized as 0 marking signal dein_step and to equal 1, execution in step 7.
Step 6. specifies among the SDRAM amount of reading and writing data Tdein=T (j) ' continuously, and the deinterleaving first address dein_sa of SDRAM is dein_addr (j), carry out step 8.
The step 7. phase I data volume of read-write is T1 (j) ', is the residue unit number of the relative address in the current deinterleaving branch road to branch road maximum storage capacity address, that is:
T1(j)′＝dein_bm(j)-dein_bn(j)；
Specify among the SDRAM amount of reading and writing data Tdein=T1 (j) ' continuously, the deinterleaving first address dein_sa of SDRAM is dein_addr (j), carry out step 8.
Step 8. is operated by " write-after-read " for each deinterleaving branch road in SDRAM.Read at first that first address is continuous T dein the location contents that dein_sa begins among the SDRAM; Deposit in Tdein the unit of SRAM2 '; Tdein the Tdein of symbol content from a SRAM1 ' unit of need deinterleaving obtained, and needing the data of deinterleavings to write first address among the SDRAM continuously these at last is in continuous T dein the unit beginning of dein_sa.
Step 9. judges whether the amount of the reading and writing data Tdein of SDRAM equals this branch road and answer the data volume T of deinterleaving (j) ', if identical, then carry out step 11; If it is inequality; Continue the value of judgement symbol signal dein_step, if equal 1, if be not equal to 1 execution in step 11 with regard to execution in step 10.
The data volume of step 10. second stage read-write is T2 (j) ', for the phase I is read and write the data volume that the back residue that finishes needs deinterleaving, that is:
T2(j)′＝T(j)′-T1(j)′；
This moment, the deinterleaving first address of SDRAM became this branch road first address dein_bs (j).Specify among the SDRAM amount of reading and writing data Tdein=T2 (j) ' continuously, the first address dein_sa that interweaves of SDRAM is dein_bs (j), and marking signal dein_step=0 carry out step 8;
Step 11. is after the deinterleaving read-write to current deinterleaving branch road finishes, and j=j+1 judges whether the branch road after upgrading is the last item deinterleaving branch road, if then forward step 12 to, if not forwarding step 5 to.
Step 12. pair the last item deinterleaving branch road, promptly straight-through branch road directly passes to address location identical the SRAM2 ' with data from SRAM1 '; The address of the individual data of T (B '-1) ' in two SRAM is B '-1,2B '-1,3B '-1; ..., B ' (T (B '-1) ')-1.
Behind all deinterleaving branch road end of operations of step 13., SDRAM concentrated refresh, concentrate and refresh the line number that line number is the employed SDRAM memory cell of deinterleaving.Concentrate refresh end after, the deinterleaving order of system wait next frame data.
The inventive method is carried out the read-write of continuation address to the interleaving data of every the branch road that interweaves by the branch road order; Effectively reduce in whole interweaving and conciliate the time that the frequent addressing of control SDRAM is consumed in the interleaving process; And propose to utilize SRAM to replace fifo register; Saved that depositing interweaves conciliates the cell fifo of interleaving address, further saved resource.In addition SDRAM is concentrated the operation that refreshes, cancelled complicated interrupt operation, thereby avoid influencing the continuity of transfer of data SDRAM.
Description of drawings
Fig. 1 convolutional deinterleaver and deinterleaver structure chart;
Fig. 2 convolutional interleave is conciliate the interlacing system block diagram;
Fig. 3 convolutional interleave flow chart;
Fig. 4 convolution de-interleaving flow chart.
Embodiment
The present invention is applicable to any application scenarios that needs convolutional interleave to conciliate interleaving technology.
As shown in Figure 2, this figure has explained the system block diagram that convolution (separating) interweaves among the present invention.Frame sram cell (SRAM1 and SRAM2), sdram controller and (separating) interleaver memory cell SDRAM formed before and after whole system was interweaved by convolution (separating) interleaving address maker, (separating).Address generator generates the address SDRAM_ADDR of every branch road (separating) when interweaving in SDRAM and the address SRAM_ADDR of (separating) interleaving data in the Frame sram cell.The relative address of former frame interleaving data in each branch road leaves in the sram cell (SRAM3).At no delayed branch, corresponding (separating) interleaving data directly writes in the SRAM2 corresponding cells from the SRAM1 address is the unit of SRAM_ADDR.The read-write of sdram controller control SDRAM in the branch road of delay is arranged; Read the legacy data that the SDRAM address is SDRAM_ADDR; SRAM2 address after delivering to (separating) and interweaving is in the unit of SRAM_ADDR, is that the data of SRAM_ADDR are write in the unit that the SDRAM address is SDRAM_ADDR with the SRAM1 address then.System by (separating) interweave branch road order from the 0th branch road to a last branch road, a frame data frame (separating) interweaves and finishes afterwards, SDRAM concentrates and refreshes to satisfy system's needs, waits for the order that next frame (separating) interweaves then.
The memory capacity that the present invention uses (separating) interleaver memory cell SDRAM is B * (B-1) * M/2 symbolic unit.If a frame data length that needs (separating) to interweave is L symbolic unit; Before (the separating) that has deposited L symbolic unit in interweaves among the sram cell SRAM1; Data after (separating) interweaves need be deposited an other SRAM of L symbolic unit, and sram cell is SRAM2 to claim this (separating) to interweave afterwards.
In the specific implementation, select the parameter in the DTMB standard for use, i.e. B=52, M=240.Stipulate in the standard interweave before Frame length be 3744 symbols, i.e. L=3744 is T (i)=72 so can get the symbolic number that every the branch road that interweaves will interweave; I=0,1 ...; 51, take the SDRAM space and be B * (B-1) * M/2=318240 memory cell.
This interleaver is produced by 52 branch roads, and the memory cell of specified interlace in SDRAM is since 0, and then when the i branch road was interweaved, its first address that interweaves was in_addr (i), that is:
in_addr(i)＝in_bs(i)+in_bn(i)， i＝1，2，...，B-1；
in_bn(i)＝(in_bn p(i)+T(i))mod(iM)， i＝1，2，...，B-1；
in_bs(i)＝in_bs(i-1)+temp1(i)-M， i＝1，2，...，B-1；
temp1(i)＝temp1(i-1)+M，temp1(1)＝M， i＝2，3，...，B-1；
Calculate the convolutional interleave address through above-mentioned formula, for first frame data, in_bn (i)=0, (i=1 in each interweaves branch road; 2 ..., 51) to 72 continuous unit of SDRAM addressing, be respectively: 0～71; 240～311,720～791 ..., 306000～306071; Second frame data obtain selected cell and are respectively according to first frame data: 72～143,312～383,792～863 ..., 306072～306143.Every frame data afterwards according to the interleaving address of former frame data by that analogy.
When interweaving, the SRAM1 that deposits the interleaving data frame is the same with 72 read/write address that SRAM2 obtains, and the corresponding i branch road that interweaves is: i, and B+i, 2B+i ..., (T (i)-1) B+i, i=1,2 ..., B-1.Corresponding in this example every the branch road that interweaves is respectively: 0,72,144 ..., 3692; 1,73,145 ..., 3693; 2,74,146 ..., 3694; 71,143,215 ..., 3743.
After obtaining the required address information of SDRAM and SRAM respectively, when interweaving, operate by " write-after-read " for each branch road that interweaves.If during not enough 72 apart from the residue unit of branch road maximum storage capacity address of relative addresses in the branch road of current place, 72 interleaving datas will split into two sections and carry out read-write operation.
Also select the parameter in the DTMB standard during deinterleaving for use, i.e. B '=52, M '=240; The symbolic number that every branch road that interweaves will interweave is T (j) '=72, j=0,1; ..., 51, the memory cell when specifying deinterleaving in SDRAM is since 0; Then when the j branch road was carried out deinterleaving, its deinterleaving first address was dein_addr (j), that is:
dein_addr(j)＝dein_bs(j)+dein_bn(j)， j＝0，1，...，B′-2；
dein_bn(j)＝(dein_bn p(j)+T(j)′)mod((B′-1-j)M′)， j＝0，1，...，B′-2；
dein_bs(j)＝dein_bs(j-1)+temp2(j)+(B′+1)M′， j＝0，1，...，B′-2；
temp2(j)＝temp2(j-1)-M′，temp2(0)＝-M′， j＝1，2，...，B′-2。
Calculate the convolution de-interleaving address through above-mentioned formula, for first frame data, dein_bn (j)=0, in each interweaves branch road (j=0,1 ..., 50) to 72 continuous unit of SDRAM addressing, be respectively: 0～71; 12240～12311; 24240～24311; 318000～318071; Second frame data obtain selected cell and are respectively according to first frame data: 72～143,12312～12383,24312～24383 ..., 318072～318143.Every frame data afterwards according to the deinterleaving address of former frame data by that analogy.
When deinterleaving, the SRAM1 that deposits the deinterleaved data frame is the same with 72 read/write address that SRAM2 obtains, and corresponding j deinterleaving branch road is: j, and B '+j, 2B '+j ..., (T (j) '-1) B '+j, j=1,2 ..., B '-1.Corresponding in this example every the branch road that interweaves is respectively: 0,72,144 ..., 3692; 1,73,145 ..., 3693; 2,74,146 ..., 3694; 71,143,215 ..., 3743.
After obtaining the required address information of SDRAM and SRAM respectively, during deinterleaving, operate by " write-after-read " for each branch road.If during not enough 72 apart from the residue unit of branch road maximum storage capacity address of relative addresses in the branch road of current place, 72 deinterleaved data will split into two sections and carry out read-write operation.
Through implementing and can seeing, owing to be that 72 symbols are read and write continuously, saved the time delay that each symbol is activated the SDRAM ranks, can reach the effective time of this operation more than 90%, shortened (separating) greatly and interweaved the required time.

Claims (1)

1. one kind is used SDRAM to realize time domain convolutional interleave reconciliation interweaving method, comprises and realizes time domain convolutional interleave method and realize time domain convolution de-interleaving method, it is characterized in that:
The concrete steps that realize time domain convolutional interleave method are:
When step I. calculates frame data and interweaves in every interweaves branch road the required symbolic number T that interweaves (i):
Figure FSB00000870175000011
Wherein L is the length of interleaving data frame, a B way that is to interweave, and i is for interweaving current branch road number, i=0,1,2 ..., B-1, mod are complementation;
Step II. when calculating frame data and interweaving at the initial address in_addr of every the branch road that interweaves (i):
in_addr(i)＝in_bs(i)+in_bn(i)，i＝1，2，...，B-1；
Wherein in_bs (i) is the first address of i branch road in SDRAM, and in_bn (i) is the relative address in the i branch road;
The 0th branch road that interweaves is straight-through branch road, and without SDRAM, the first address in_bs (1) of the 1st branch road in SDRAM is Unit 0, then:
in_bs(i)＝in_bs(i-1)+temp1(i)-M，i＝2，3，...，B-1；
Temp1 (i)=temp1 (i-1)+M wherein, temp1 (1)=M, M is the delay period that interweaves;
When interleaving data was first frame data, the in_bn of each branch road (i) was 0; When interleaving data is not first frame data, then
in_bn(i)＝(in_bn p(i)+T(i))mod(iM)，i＝1，2，...，B-1；
In_bn wherein p(i) expression former frame interleaving data is visited the relative address in the i bar branch road;
Step II I. calculates the address of the SRAM that deposits the front and back Frame that interweaves;
When interweaving, the individual data of the T that the i branch road need interweave (i) will obtain from the individual unit of T (i) the SRAM1 that deposits interleaving data frame not; The individual data of T after this branch road interweaves (i) will deposit in the individual unit of T (i) of the SRAM2 that deposits the back Frame that interweaves; This moment, the individual read/write address of T (i) of SRAM1 and SRAM2 was identical, and the corresponding i branch road that interweaves is: i, and B+i, 2B+i ..., (T (i)-1) B+i, i=1,2 ..., B-1;
Step IV. the 0th branch road that interweaves, current branch road i=0, promptly straight-through branch road directly passes to address location identical the SRAM2 with interleaving data from SRAM1, and the address of the individual data of T (0) in two SRAM is 0, B, 2B ..., (T (0)-1) B;
Step V. gets into next bar branch road that interweaves, i=i+1; Obtain the initial address in_addr (i) that the place branch road interweaves in SDRAM; Judge whether branch road interior relative address in_bn (f) in place enough has T (i) individual apart from the residue unit of branch road maximum storage capacity address in_bm (i); In_bm (i)=iM wherein, if enough, execution in step VI then; If it is not enough; Need be divided into twice to interweaving of this branch road and interweave the read-write stage, specify to be initialized as 0 marking signal in_step and to equal 1, execution in step VII;
Step VI. specifies among the SDRAM amount of reading and writing data Tin=T (i) continuously, and the first address in_sa that interweaves of SDRAM is in_addr (i), carries out step VIII;
The data volume that the step VII. phase I reads and writes is T1 (i), is the residue unit number of the relative address in the current branch road that interweaves to branch road maximum storage capacity address, that is:
T1(i)＝in_bm(i)-in_bn(i)；
Specify among the SDRAM amount of reading and writing data Tin=T1 (i) continuously, the first address in_sa that interweaves of SDRAM is in_addr (i), carries out step VIII;
Step VIII. operates by " write-after-read " for each branch road that interweaves in SDRAM; Read at first that first address is continuous T in the location contents that in_sa begins among the SDRAM; Deposit in Tin the unit of SRAM2; Tin the Tin of symbol content from the SRAM1 unit that need are interweaved obtains, and at last these data that need interweave being write first address among the SDRAM continuously is in continuous T in the unit beginning of in_sa;
Step IX. judges that whether the amount of the reading and writing data Tin of SDRAM equals the data volume T (i) that this branch road should interweave, if identical, then carries out step XI; If inequality, the value of continuation judgement symbol signal in_step is if equal 1 with regard to execution in step X, if be not equal to 1, execution in step XI;
The data volume of step X. second stage read-write is T2 (i), for the phase I is read and write the data volume that the back residue that finishes need interweave, that is:
T2(i)＝T(i)-T1(i)；
This moment, the first address that interweaves of SDRAM became this branch road first address in_bs (i); Specify among the SDRAM amount of reading and writing data Tin=T2 (i) continuously, the first address in_sa that interweaves of SDRAM is for cutting in_bs (i), and marking signal in_step=0 carries out step VIII;
Step XI. is to the interweaving after all read-write finishes of the current branch road that interweaves, and judges that whether current branch road is the last item branch road that interweaves, if then forward step XII to, if not, forward step V to;
Step XII. interweaves to all behind the branch road end of operation, and that behind the frame data that interweave, concentrates refreshes, and concentrates that to refresh line number be the line number of employed SDRAM memory cell of interweaving; Concentrate refresh end after, the order that interweaves of system wait next frame data;
The concrete steps that realize time domain convolution de-interleaving method are:
The symbolic number T (j) ' of required deinterleaving in every deinterleaving branch road when step 1. is calculated a frame data deinterleaving:
Figure FSB00000870175000031
Wherein L ' is the length of deinterleaved data frame, and B ' props up way for deinterleaving, and j is the current branch road of deinterleaving number, j=0, and 1,2 ..., B '-1, mod are complementation;
When step 2. is calculated a frame data deinterleaving at the initial address dein_addr of every deinterleaving branch road (j):
dein_addr(j)＝dein_bs(j)+dein_bn(j)；
Wherein dein_bs (j) is the first address of j branch road in SDRAM, and dein_bn (j) is the relative address in the j branch road;
Specifying the first address dein_bs (0) of the 0th branch road in SDRAM is Unit 0, removes B '-1 branch road and is straight-through branch road, and outside SDRAM, other branch roads do
Dein_bs (j)=dein_bs (j-1)+temp2 (j)+(B '+1) M '; Wherein: temp2 (j)=temp2 (j-1)-M ', temp2 (0)=-M ', M ' is the deinterleaving delay period;
When deinterleaved data was first frame data, the dein_bn of each branch road (j) was 0; When deinterleaved data is not first frame data, then:
dein_bn(j)＝(dein_bn p(j)+T(j)′)mod((B′-1-j)M′)；
Dein_bn wherein pRelative address when (j) expression former frame deinterleaved data is visited j bar branch road;
Step 3. is calculated the address of the SRAM that deposits deinterleaving front and back Frame;
During deinterleaving, the j branch road needs the individual data of T (j) ' of deinterleaving to obtain from the individual unit of the T the SRAM1 ' that deposits the deinterleaved data frame (j) '; The individual data of T (j) ' after this branch road deinterleaving will deposit in the individual unit of T (j) ' of depositing the SRAM2 ' of Frame after the deinterleaving; This moment, the individual read/write address of T (j) ' of SRAM1 ' and SRAM2 ' was the same, and corresponding j deinterleaving branch road is:
j，B′+j，2B′+j，...，(T(j)′-1)B′+j，i＝1，2，...，B′-1；
Step 4. convolution de-interleaving begins, mark branch road j=0;
Step 5. obtains the initial address dein_addr (j) of place branch road deinterleaving; Judge whether branch road interior relative address dein_bn (j) in place enough has T (j) ' individual apart from the residue unit of branch road maximum storage capacity address dein_bm (j); Wherein dein_bm (j)=(B '-j-1) M ', if enough, then execution in step 6; If it is not enough; Need be divided into twice deinterleaving read-write stage to the deinterleaving of this branch road, specify to be initialized as 0 marking signal dein_step and to equal 1, execution in step 7;
Step 6. specifies among the SDRAM amount of reading and writing data Tdein=T (j) ' continuously, and the deinterleaving first address dein_sa of SDRAM is dein_addr (j), carry out step 8;
The step 7. phase I data volume of read-write is T1 (j) ', is the residue unit number of the relative address in the current deinterleaving branch road to branch road maximum storage capacity address, that is:
T1(j)′＝dein_bm(j)-dein_bn(j)；
Specify among the SDRAM amount of reading and writing data Tdein=T1 (j) ' continuously, the deinterleaving first address dein_sa of SDRAM is dein_addr (j), carry out step 8;
Step 8. is operated by " write-after-read " for each deinterleaving branch road in SDRAM; Read at first that first address is continuous T dein the location contents that dein_sa begins among the SDRAM; Deposit in Tdein the unit of SRAM2 '; Tdein the Tdein of symbol content from a SRAM1 ' unit of need deinterleaving obtained, and needing the data of deinterleavings to write first address among the SDRAM continuously these at last is in continuous T dein the unit beginning of dein_sa;
Step 9. judges whether the amount of the reading and writing data Tdein of SDRAM equals this branch road and answer the data volume T of deinterleaving (j) ', if identical, then carry out step 11; If it is inequality; Continue the value of judgement symbol signal dein_step, if equal 1, if be not equal to 1 execution in step 11 with regard to execution in step 10;
The data volume of step 10. second stage read-write is T2 (j) ', for the phase I is read and write the data volume that the back residue that finishes needs deinterleaving, that is:
T2(j)′＝T(j)′-T1(j)′；
This moment, the deinterleaving first address of SDRAM became this branch road first address dein_bs (j); Specify among the SDRAM amount of reading and writing data Tdein=T2 (j) ' continuously, the first address dein_sa that interweaves of SDRAM is dein_bs (j), and marking signal dein_step=0 carry out step 8;
Step 11. is after the deinterleaving read-write to current deinterleaving branch road finishes, and j=j+1 judges whether the branch road after upgrading is the last item deinterleaving branch road, if then forward step 12 to, if not forwarding step 5 to;
Step 12. pair the last item deinterleaving branch road, promptly straight-through branch road directly passes to address location identical the SRAM2 ' with data from SRAM1 '; The address of the individual data of T (B '-1) ' in two SRAM is B '-1,2B '-1,3B '-1; ..., (T (B '-1) ') B '-1;
Behind all deinterleaving branch road end of operations of step 13., SDRAM concentrated refresh, concentrate and refresh the line number that line number is the employed SDRAM memory cell of deinterleaving; Concentrate refresh end after, the deinterleaving order of system wait next frame data.
CN2009101533341A 2009-10-15 2009-10-15 Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM Expired - Fee Related CN101697491B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2009101533341A CN101697491B (en) 2009-10-15 2009-10-15 Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2009101533341A CN101697491B (en) 2009-10-15 2009-10-15 Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM

Publications (2)

Publication Number Publication Date
CN101697491A CN101697491A (en) 2010-04-21
CN101697491B true CN101697491B (en) 2012-11-21

Family

ID=42142572

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2009101533341A Expired - Fee Related CN101697491B (en) 2009-10-15 2009-10-15 Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM

Country Status (1)

Country Link
CN (1) CN101697491B (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105099599B (en) * 2014-04-16 2019-12-27 上海澜至半导体有限公司 Interleaving and deinterleaving method and corresponding device
GB2533308A (en) * 2014-12-15 2016-06-22 Sony Corp Transmitter and method of transmitting and receiver and method of receiving
CN104993837B (en) * 2015-07-24 2018-08-03 丽水博远科技有限公司 A kind of convolutional interleave method and convolutional deinterleaver
CN110383785B (en) * 2017-02-27 2020-09-25 高拓讯达（北京）科技有限公司 Apparatus for performing time-domain deinterleaving of binary data streams in a DVB-T2 receiver
CN110009103B (en) * 2019-03-26 2021-06-29 深兰科技（上海）有限公司 Deep learning convolution calculation method and device
CN111245447B (en) * 2020-02-28 2023-07-25 武汉虹信科技发展有限责任公司 Antenna data interleaving and de-interleaving method based on FPGA
CN116961841B (en) * 2023-09-19 2023-12-26 芯潮流(珠海)科技有限公司 Decoding method, device and storage medium for high-speed data center

Also Published As

Publication number Publication date
CN101697491A (en) 2010-04-21

Similar Documents

Publication Publication Date Title
CN101697491B (en) Method for realizing convolution interleaving and de-interleaving of time domain by using SDRAM
CN101237240B (en) A method and device for realizing cirrocumulus interweaving/de-interweaving based on external memory
CN107590085B (en) A kind of dynamic reconfigurable array data path and its control method with multi-level buffer
CN102681946A (en) Memory access method and device
CN104239232B (en) Ping-Pong cache operation structure based on DPRAM (Dual Port Random Access Memory) in FPGA (Field Programmable Gate Array)
CN104993837B (en) A kind of convolutional interleave method and convolutional deinterleaver
CN102945213A (en) FPGA (field programmable date array) based out-of-order memory controller and realizing method thereof
CN101923522B (en) Storage controller and processing method of data operation commands
CN110442321A (en) One kind prefetching fifo circuit and method
CN110265073A (en) Semiconductor devices
CN109359729A (en) It is a kind of to realize data cached system and method on FPGA
CN104461934B (en) A kind of time solution convolutional interleave device and method of suitable DDR memory
CN101825997A (en) Asynchronous first-in first-out storage
CN101674093B (en) Two-stage realization method of convolutional interleave and device thereof
CN104599706B (en) The method that random access memory and adjustment random access memory read sequential
CN101404555B (en) Convolution interleaving/de-interleaving method in digital transmission
CN103226977B (en) Quick NAND FLASH controller based on FPGA and control method thereof
CN102043591B (en) Write operation method for phase-change random access memory (PRAM)
CN101883046B (en) Data cache architecture applied to EPON terminal system
CN104461956A (en) Method, device and system for accessing synchronous dynamic random access memories (SDRAMs)
CN104575589B (en) A kind of radiation-resistant SRAM self-refresh circuits of availability high and its self-refresh method
CN102497287A (en) Method and system for realizing energy-saving statistics in Ethernet switching chip
CN100370436C (en) Method for improving storage access efficiency and storage coutroller
US9183908B2 (en) Method and apparatus for memory access
CN105528305B (en) A kind of short cycle storage method based on DDR2 SDRAM

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20121121

Termination date: 20151015

EXPY Termination of patent right or utility model