CN101404555B - Convolution interleaving/de-interleaving method in digital transmission - Google Patents
Convolution interleaving/de-interleaving method in digital transmission Download PDFInfo
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Abstract
The invention discloses a method for interleaving and deinterleaving a convolution in digital transmission. The method regards an RAM as a ring with end-to-end addresses, and occupies RAM I(I+1)M/2 space while interleaving according to the I and M information. While interleaving, the RAM is subject to writing-after-reading operations round by round. Differences among various addresses that are read and written in each round are M, 2M, to IM, and the address of the next round is close to that of the prior round. RAM I(I+3)M/2 space is occupied while deinterleaving, and reading-reading-writing operations are performed round by round. Differences among various addresses that are read for the first time in each round are (I+1)M, IM, to 2M, and the address of the next round is close to that of the prior round. The address that is read for the second time and the address that is read for the first time are separated by 2M+1 space, namely having a distance of the 2M (shown as in the figure). The written address is the same as the address that is read for the first time. The convolution process is simply controlled, and a deinterleaver and an RS decoder can share an RAM, which saves the resources.
Description
Technical field
The invention belongs to digital signal transmission field, particularly in the digital television broadcasting transmission transmission data are carried out the implementation method of convolution byte-interleaved.
Background technology
In the modern digital communication systems, transmission channel often is subjected to various interference and weak influence, so the signal of transmission can make a mistake.Generally all can adopt chnnel coding for this reason and interweave, to improve systematic function.Chnnel coding often adopts forward error correction (FEC, Forward Error Correction) to make outer sign indicating number, and adopts interlaced code to make ISN.For random error, generally can be corrected, and, then must be added interleaving technology for burst error by the channel error correction coding.Promptly the data that will transmit are upset order by interweaving, by deinterleaving the original order recovery of data is come out again at receiving terminal then at transmitting terminal.So just can change burst error discretization in groups into random error, can correct by error correction coding then.
According to the different interleaving mode, interweave and mainly be divided into random interleaving, block interleaving, convolutional interleave.
(1) random interleaving.Random interleaving is actually pseudo random interleaving, handles by data being carried out pseudorandom permutation, obtains the output of approximate random, is used for secure communication and spread spectrum communication field more.
(2) block interleaving.It is that (N B) writes data earlier a two dimensional memory arrays by row, then data are read by row again, finishes interleaving process.Correspondingly the process of deinterleaving is data to be write by row again read by row.This advantage that interweaves be simple in structure, be easy to realize, shortcoming be the memory space that needs big, interweave and the time-delay of deinterleaving long.Block interleaving is used more in burst system (GSM), normal and RS coding or Turbo coding associating use.
(3) convolutional interleave.Convolutional interleave is formed by delaying time into the I road shift register that equal difference increases progressively, and the input data enter the different input in I road successively, and dateout is read from corresponding road through time-delay.Because time-delay is different, adjacent input data at output by discretization.The advantage of convolutional interleave is that input and output are synchronous, and under the identical situation of performance, required memory space is half of block interleaving.The DVB-C system in Europe has adopted the convolutional interleave technology, uses 12 branches, and increasing progressively timer is 17.Deinterleaving then is according to the opposite mode that interweaves data being rearranged back original order, generally need with the identical memory that interweaves, also similar on the structure.
Under identical weaving length, compare the memory resource that to save half with block interleaving, and convolutional interleave time-delay is shorter, so convolutional interleave is fit to high code check, continuous data stream transmission system, as digital television broadcasting system.The also normal and RS coding associating use of convolutional interleave.
The detailed description of convolution interleaving/de-interleaving basic principle:
As shown in Figure 1, interleaver is made of I branch, from 0 to (I-1), by successively each branch being read and write under the effect of diverter switch.The time-delay difference of each branch is branched off into (I-1) branch from the 0th, and time-delay is respectively 0, M, 2M, 3M ... (I-2) M, (I-1) M, because the time-delay difference of each branch, the order difference that causes data to read realizes interleave function.
The principle of deinterleaver is basic identical, constitute by I branch, from 0 to (I-1), by successively each branch being read and write under the effect of diverter switch.The time-delay difference of each branch is branched off into (I-1) branch from the 0th, and time-delay is respectively (I-1) M, (I-2) M ... 3M, 2M, M, 0, because the time-delay difference of each branch, the order difference that causes data to read realizes the deinterleaving function.
Convolutional deinterleaver has three kinds of implementation methods usually: shift register method, RAM subregion loop shifting, RAM monoblock loop shifting.
The shift register method is that the FIFO of every delayed branch with certain-length realized, for interleaver, the used register number of this scheme is: 0+M+2M+L (I-2)+(I-1)=I (I-1)/2, and each byte is 8, needs 4I (I-1) bit register, therefore, the advantage of this method is more directly perceived, implements simply, and shortcoming is when I, M numerical value are big, register resources consumption is very big, and hardware is difficult to realize.
RAM subregion loop shifting is to utilize the read-write to the different addresses of RAM to realize the time-delay of each branch.RAM is divided into I district, and the size in each district is because the different used space differences of time-delay.In the read-write that circulated in each district, read-write also circulates in the inside in each district.This method focus on control to read/write address, the address of address generator output for the first address in district and bias internal address, district and.This method adopts RAM to realize convolutional interleave, has saved resource, and total scale is reduced, but this method still need be used to deposit the FIFO of the bias internal address, district in each district, and capacity is (I-1) individual unit, and the control more complicated of this method.
RAM monoblock loop shifting is to utilize the read-write to the different addresses of RAM to realize the time-delay of each branch equally.This method monoblock RAM of team circulation read-write need not used FIFO, has further saved resource, is the best practice that realizes convolutional deinterleaver with RAM.
Summary of the invention
The objective of the invention is to propose a kind of new convolutional interleave and conciliate interweaving method.Interleaver adopts the method for reading-writing, therefore for an address space among the RAM, during operation, will exist the data in this space, address to read earlier, next clock will be imported data again and write in this space, address, and this method is carried out monoblock circulation read-write to used ram space.In deinterleaver,, be the output time difference because deinterleaver and shared this RAM of RS decoder so RAM is carried out twice read operation, are equivalent to two identical outputs of content.Therefore, deinterleaver is read-is read-write operation RAM, and wherein, the address of reading for the second time differs 2M with the address of reading for the first time, and the address of write operation is identical with the address of reading for the first time.
This interleaver is made of I branch, and from 0 to (I-1), the address of each branch differs M, 2M, 3M ... (I-1) M, IM, so required altogether ram space is N, N=I (I+1) M/2.Can regard RAM as annular RAM that first address and tail address join, as shown in Figure 2.
When interweaving, each branch road is carried out read-write operation successively.Suppose that current reading and writing data of interweaving is that the RAM read/write address that participates in i bar delayed branch correspondence is A
n, next address that reads and writes data that interweaves is A corresponding to the corresponding read/write address of i+1 bar delayed branch just so
N+1, then have:
A
N+1=A
n+ (i+1) M when i!=(I-1), A
n+ (i+1) M＜N;
A
N+1=A
n+ (i+1) M-N when i!=(I-1), A
n+ (i+1) M 〉=N;
A
N+1=A
n+ IM+1 is as i=(I-1), A
n+ IM+1＜N;
A
N+1=A
n+ IM+1-N is as i=(I-1), A
n+ IM+1 〉=N;
During the transmission beginning, the reading and writing data address be respectively the 0th branch, the 1st branch ... first address space of (I-1) individual branch, carry out the read-write of next round then, read/write address be respectively the 0th branch, the 1st branch ... second address space of (I-1) individual branch is close to the address space that last round of read-write is write.
When carrying out the read-write of M+1 wheel, M+1 address space of the 0th branch is first address space of the 1st branch, as shown in Figure 3.Then carry out the lower whorl read-write ...
When reading and writing IM+1 address space of (I-1) individual branch, because the tail address that IM the address space of (I-1) individual branch is RAM, so IM+1 the address space read/write address of (I-1) individual branch is first address space of the 0th branch, as shown in Figure 4.Same reason, for the next round read-write, second IM+2 address space that address space is (I-1) individual branch of the 0th branch then carries out the next round read-write ...
Each takes turns read-write all will carry out I time read-write operation, and the address of this I time input differs and is respectively M, 2M, 3M ... (I-1) M, IM regard RAM as annular RAM that first address and tail address join, and first address is 0, and read/write address is:
0、M、3M、6M、……(I-2)(I-1)M/2、(I-1)IM/2、
1、M+1、3M+1、6M+1、……(I-2)(I-1)M/2+1、(I-1)IM/2+1、
2、M+2、3M+2、3M+2、6M+2、……(I-2)(I-1)M/2+2、(I-1)IM/2+2……。
The deinterleaver of receiving terminal, basic identical on the principle with the interleaver of transmitting terminal because deinterleaver and shared this RAM of RS decoder, thus RAM is carried out twice read operation, so with the interleaver of transmitting terminal some difference again.Deinterleaver is read-is read-write operation RAM, and wherein the address of reading for the second time differs 2M with the address of reading for the first time, and the address of write operation is identical with the address of reading for the first time.
This deinterleaver is made of I branch equally, and from 0 to (I-1), the address of each branch differs (I+1) M, IM ... 4M, 3M, 2M read and write successively to I branch, and required altogether ram space is N, N=I (I+3) M/2.
Therefore, suppose that it is A that current deinterleaving participates in the address that the RAM of i bar delayed branch correspondence reads for the first time
n, corresponding to read the address for the first time be A to i+1 bar delayed branch so
N+1, RAM is regarded as the annular RAM that first address and tail address join, then have
A
N+1=A
n+ (I-i+1) M when i!=(I-1), A
n+ (I-i+1) M＜N;
A
N+1=A
n+ (I-i+1) M-N when i!=(I-1), A
n+ (I-i+1) M 〉=N;
A
N+1=A
n+ 2M+1 is as i=(I-1), A
n+ 2M+1＜N;
A
N+1=A
n+ 2M+1-N is as i=(I-1), A
n+ 2M+1 〉=N;
I bar delayed branch is carried out the read operation second time, and corresponding address ram is B
n, with A
n2M-1 the space that be separated by, as shown in Figure 6, i.e. B
n-A
n=2M, as shown in Figure 6.Be that current reading and writing data of interweaving is that the RAM read/write address that participates in i bar delayed branch correspondence is B
n, next address that reads and writes data that interweaves is B corresponding to the corresponding read/write address of i+1 bar delayed branch just so
N+1, then have:
B
N+1=A
n+ (I-i+3) M when i!=(I-1), A
n+ (I-i+3) M＜N;
B
N+1=A
n+ (I-i+3) M-N when i!=(I-1), A
n+ (I-i+3) M 〉=N;
B
N+1=A
n+ 4M+1 is as i=(I-1), A
n+ 4M+1＜N;
B
N+1=A
n+ 4M+1-N is as i=(I-1), A
n+ 4M+1 〉=N;
The address of the write operation of deinterleaver is identical with the address of read operation for the first time, i.e. A
n
Below the read operation first time in twice read operation is elaborated.
The transmission beginning, the address of reading for the first time in the first round operation be respectively the 0th branch, the 1st branch ... first address space of (I-1) individual branch, the address of reading for the first time in second wheel operation be respectively the 0th branch, the 1st branch ... second address space of (I-1) individual branch ...
When carrying out the read-write of 2M+1 wheel, 2M+1 the address space of (I-1) individual branch is first address space of the 0th branch, as shown in Figure 6.Then carry out the lower whorl read-write ...
First address space 0 of the 0th branch, so the address is respectively: 0, (I+1) M, (I+1) M+IM ... ((I+1) M+IM+ (I-1) M+L 3M), ((I+1) M+IM+ (I-1) M+L 2M), 1, (I+1) M+1, (I+1) M+IM+1 ... ((I+1) M+IM+ (I-1) M+L 3M+1), ((I+1) M+IM+ (I-1) M+L 2M+1), 2, (I+1) M+2 ... 2M, (I+1) M+2M ... ((I+1) M+IM+ (I-1) M+L 3M+2M), 0,2M+1, (I+1) M+2M+1 ...
The present invention proposes a kind of new convolutional interleave and conciliate interweaving method.The present invention is by carrying out the function that implementing reading and writing interweaves to storage organization RAM, and in order to save memory space and to simplify the read/write address generator, interleaver of the present invention is taked the method for write-after-read, and used ram space is carried out monoblock circulation read-write; Deinterleaver adopts to be read-reads-method write R, equally used ram space is carried out monoblock circulation read-write and shared this RAM of RS decoder.The present invention realizes RAM is carried out monoblock circulation read-write, and deinterleaver and the shared RAM of RS decoder, does not need FIFO, saves resource.
Below in conjunction with drawings and Examples the present invention is described further.
Description of drawings
Fig. 1 is convolutional deinterleaver and deinterleaver.
Fig. 2 is for regarding RAM as the annular RAM that first address and tail address join.
Fig. 3 is in the interleaver, M+1 address space of the 0th branch of M+1 wheel read-write.
Fig. 4 is in the interleaver, IM+1 the address space of read-write (I-1) individual branch.
Fig. 5 is twice read operation of deinterleaver.
Fig. 6 is in the deinterleaver, in the 2M+1 wheel to the read operation first time of (I-1) individual branch.
Fig. 7 is the fundamental diagram of interleaver.
Embodiment
In the present embodiment, I selects 12, and M selects 17.When interweaving, take ram space N=I (I+1) M/2, promptly take 1326 spaces, the operation of reading-writing that RAM is carried out taking turns.The address of read-write is produced by address generator, as shown in Figure 7, each take turns each address differ 17,34 ... 287,204.
This interleaver is made of 12 branches, and from 0 to 11, suppose that current reading and writing data of interweaving is that the RAM read/write address that participates in i bar delayed branch correspondence is A
n, next address that reads and writes data that interweaves is A corresponding to the corresponding read/write address of i+1 bar delayed branch just so
N+1, then have:
A
N+1=A
n+ 17 (i+1) when i!=11, A
n+ 17 (i+1)＜1326;
A
N+1=A
n+ 17 (i+1)-1326 when i!=11, A
n+ 17 (i+1) 〉=1326;
A
N+1=A
n+ 12 * 17+1 works as i=11, A
n+ 12 * 17+1＜1326;
A
N+1=A
n+ 12 * 17+1-1326 works as i=11, A
n+ 12 * 17+1 〉=1326;
Initial address is 0, and then Du Xie address is:
0、17、51、102、170、255、357、476、612、765、935、1122、1、18、52、103、171、256、358、477、613、766、936、1123、2、19、53、104、172、257、359、478、614、767、937、1124、……17、34、68、119、187、272、374、493、629、782、952、1139、18、35、69、120、188、273、375、494、630、783、953、1140、19、35、……203、220、254、305、373、458、560、679、815、968、1138、1325、204、221、255、306、374、459、561、680、816、969、1139、0、205、222、……。
During deinterleaving, take ram space N=I (I+3) M/2, promptly take 1530 spaces.Each take turns each address differ 221,204,187 ... 51,34.This deinterleaver is made of 12 branches, and from 0 to 11, suppose that it is A that current deinterleaving participates in the address that the RAM of i bar delayed branch correspondence reads for the first time
n, corresponding to read the address for the first time be A to i+1 bar delayed branch so
N+1, RAM is regarded as the annular RAM that first address and tail address join then to be had:
A
N+1=A
n+ 17 (12-i+1) when i!=11, A
n+ 17 (12-i+1)＜1530;
A
N+1=A
n+ 17 (12-i+1)-1530 when i!=11, A
n+ 17 (12-i+1) 〉=1530
A
N+1=A
n+ 2 * 17+1 works as i=11, A
n+ 2 * 17+1＜1530;
A
N+1=A
n+ 2 * 17+1-1530 works as i=11, A
n+ 2 * 17+1 〉=1530;
Initial address is 0, and then the address of reading for the first time is:
0、221、425、612、782、935、1071、1190、1292、1377、1445、1496、1、222、426、613、783、936、1072、1191、1293、1378、1446、1497、2、223、……34、255、459、646、816、969、1105、1224、1326、1401、1479、0、35、256......。
The address of writing is identical with the address of reading for the first time.The address B that reads for the second time
nWith the address A that reads for the first time
nDiffer 2M, i.e. 34 spaces.
B
N+1=A
n+ 17 (12-i+3) when i!=11, A
n+ 17 (12-i+3)＜1530;
B
N+1=A
n+ 17 (12-i+3)-1530 when i!=11, A
n+ 17 (12-i+3) 〉=1530;
B
N+1=A
n+ 4 * 17+1 works as i=11, A
n+ 4 * 17+1＜1530;
B
N+1=A
n+ 4 * 17+1-1530 works as i=11, A
n+ 4 * 17+1 〉=1530;
Therefore, the address of reading for the second time is:
34、255、459、646、815、969、1105、1224、1326、1411、1479、0、35、256、460、647、816、970、1106、1225、1327、1412、14801、36、257、……68、289、493、680、850、1003、1139、1258、1360、1435、1513、1513、34、69、290......。
Convolution process control of the present invention is simple, and deinterleaver and RS decoder can shared RAM, economize on resources.
Claims (2)
1. the method for a kind of convolutional interleave in the Digital Transmission realizes the convolutional interleave on the capable M of I rank, and interleaver is made of I branch, and from 0 to I-1, the address of each branch differs M, 2M, 3M ... (I-2) M, (I-1) M, IM;
Realization is carried out monoblock circulation read-write to used ram space, and the first address that reads and writes data is 0, and I branch read and write successively, and required altogether ram space is N, N=I (I+1) M/2;
Suppose that current reading and writing data of interweaving is that the RAM read/write address that participates in i bar delayed branch correspondence is A
n, next address that reads and writes data that interweaves is A corresponding to the corresponding read/write address of i+1 bar delayed branch just so
N+1, RAM is regarded as the annular RAM that first address and tail address join, then have:
A
N+1=A
n+ (i+1) M when i!=(I-1), A
n+ (i+1) M＜N;
A
N+1=A
n+ (i+1) M-N when i!=(I-1), A
n+ (i+1) M 〉=N;
A
N+1=A
n+ IM+1 is as i=(I-1), A
n+ IM+1＜N;
A
N+1=A
n+ IM+1-N is as i=(I-1), A
n+ IM+1 〉=N;
After the address ram that is produced was read a byte according to the method described above, the data with a byte write in this address again, adopted the method for reading-writing; Therefore for an address space among the RAM, during operation, will exist the data in this space, address to read earlier, i.e. output; To import data again and write in this space, address, and realize in one-period read-write operation being carried out in same address.
2. the method for a kind of convolution de-interleaving in the Digital Transmission realizes the convolution de-interleaving on the capable M of I rank, and deinterleaver is made of I branch, and from 0 to I-1, the address of each branch differs (I+1) M, IM ... 4M, 3M, 2M;
Realization is carried out monoblock circulation read-write to used ram space, and I branch read and write successively, and required altogether ram space is N, N=I (I+3) M/2;
Suppose that current deinterleaving is that i bar delayed branch is carried out the read operation first time, corresponding address ram is A
n, next deinterleaving is carried out the read operation first time to i+1 bar delayed branch so, and corresponding address ram is A
N+1, RAM is regarded as the annular RAM that first address and tail address join then to be had:
A
N+1=A
n+ (I-i+1) M when i!=(I-1), A
n+ (I-i+1) M＜N;
A
N+1=A
n+ (I-i+1) M-N when i!=(I-1), A
n+ (I-i+1) M 〉=N;
A
N+1=A
n+ 2M+1 is as i=(I-1), A
n+ 2M '+1＜N;
A
N+1=A
n+ 2M+1-N is as i=(I-1), A
n+ 2M+1 〉=N;
I bar delayed branch is carried out the read operation second time, and corresponding address ram is B
n, with A
nDiffer 2M;
Current deinterleaving is that i bar delayed branch is carried out the read operation second time, and corresponding address ram is B
n, next deinterleaving is carried out the read operation second time to i+1 bar delayed branch so, and corresponding address ram is B
N+1, then have:
B
N+1=A
n+ (I-i+3) M when i!=(I-1), A
n+ (I-i+3) M＜N;
B
N+1=A
n+ (I-i+3) M-N when i!=(I-1), A
n+ (I-i+3) M 〉=N;
B
N+1=A
n+ 4M+1 is as i=(I-1), A
n+ 4M+1＜N;
B
N+1=A
n+ 4M+1-N is as i=(I-1), A
n+ 4M+1 〉=N;
The address of the write operation of deinterleaver is identical with the address of read operation for the first time, i.e. A
n
According to the method described above, RAM is read-reads-write operation, wherein the address of write operation is identical with the address of reading for the first time, shared this RAM of deinterleaver and RS decoder.
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| CN105099599B (en) * | 2014-04-16 | 2019-12-27 | 上海澜至半导体有限公司 | Interleaving and deinterleaving method and corresponding device |
| EP3001572A1 (en) * | 2014-09-29 | 2016-03-30 | Panasonic Corporation | Interleaving by concatenation of convolutional and block interleaving |
| WO2018107476A1 (en) * | 2016-12-16 | 2018-06-21 | 华为技术有限公司 | Memory access device, computing device and device applied to convolutional neural network computation |
| CN111245447B (en) * | 2020-02-28 | 2023-07-25 | 武汉虹信科技发展有限责任公司 | Antenna data interleaving and de-interleaving method based on FPGA |
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