KR100268406B1 - Method for rearranging a decoding data of lattice decoder for fa standard 8 vbs - Google Patents

Abstract

PURPOSE: A method for rearranging decoded data of a trellis decoder for an HDTV(High Definition Television) is provided to rearrange decoded data by installing a multitude of single port RAM having a capacitance corresponding to 4 segments at an output terminal of a trellis decoder. CONSTITUTION: A multitude of single port RAM(307,308) having a capacitance corresponding to 4 segments is installed at an output terminal(310) of a trellis decoder. Decoded data of 4 segment units of the trellis decoder are stored in an upper memory(307) of the RAMs. The decoded data of 4 segment units are stored in a lower memory(308). The stored data are read from the upper memory(307). The reading operation and the storing operation are repeated each 4 segment units.

Description

Decoding Data Rearrangement Method of Lattice Decoder for High Definition TV

The present invention provides a GA standard 8 VSB (VESTIGIAL) in a system for receiving a digital transmission standard proposed for terrestrial broadcasting by GA (GRAND ALLIANCE) in the US HDTV (High Definition TELEVISION) method. SIDEBAND, Residual Side Band (hereinafter referred to as VSB). The output data and clock rate arrangement of the lattice protector. In particular, a four-segment 828-byte single port RAM is installed at the output of the lattice protector. When the decoded data is stored in the RAM, the decoded data is read at the byte clock rate, so that the decoded data in the symbol clock unit is converted into the byte clock unit and read out when the data is read. This is to rearrange the decoding data because it controls the order of the addresses.

As is well known, HDTV is more than twice the resolution and 5 times the amount of information compared to existing color TVs due to the pursuit of high-definition and large screens.It has a screen size of 30 inches or more and about 10 times the color reproducibility and CD (COMPATC DISC). It is a TV that can realize HIFI quality equivalent to).

Hereinafter, a grid protector used in a forward error corrector of a GA 8 VSB receiving system in HDTV will be described in detail.

First, we have a simple VITERBI decoding algorithm, CODE RATE R = 1/2, CONSTRAINT LENGTH K = 3, and GENERATING POLYNOMIAL.

G1 = 1 + X + X ²

G2 = 1 + X ²

The following description will be made using an example of a convolutional encoder.

The convolutional encoder is composed of a two-bit shift register 101 and two adders 102 for performing Modulo-2 addition, as shown in FIG. The outputs G1 and G2 of the decoder are determined by the state 103 and the input 103 which are the contents of the shift register 101. Fig. 2 is a trellis diagram showing the output over time.

In the lattice diagram of FIG. 2, each point represents each state that the shift register 101 may have, and the branch of the solid line indicates the transition when the input is "0", and the input having the dotted line is "." The transition when 1 "is shown, respectively. In addition, the number displayed on each branch represents the values of G1 and G2 that are output when the transition of the branch occurs. As shown in the drawing, two paths are combined in each state.

The Viterbi decoding algorithm is based on the MAXIMUM LIKELIHOOD DECODING, which selects only the probable paths of the two paths and discards the probable paths. The path selected as above is called a survivor path. Each state maintains information about survivor paths of a given length (DECISION DEPTH, or TRUNCATION DEPTH).

Decoding is also performed by selecting the most likely survivor path among the survivor paths maintained by each state and tracebacking it.

On the other hand, the grid decoder based on the Viterbi algorithm, as shown in Figure 3, the branch metric calculation unit 202 for calculating the similarity (BRANCH METRIC) between the received input code and the reference value of each branch and ; An ACS (ADD-COMPARE-SELECT) calculation device 203 for selecting a survivor route in each state and calculating a state value of the survivor route; A state value storage device (205) for storing a state value output from the ACS calculation device (203); A path storage device (PATH MEMORY) 207 for storing information on survivor paths in each state; A maximum likelihood detection device (MAXIMUM LIKELIHOOD VALUE DETECTION) 206 for detecting the most probable survivor route among each survivor route; A normalization arithmetic unit 204 for subtracting a maximum likelihood value from the arithmetic result of the ACS arithmetic unit 203; It consists of a traceback unit 208 for controlling the path storage device 207 to execute traceback, and performs decoding.

In the drawings, reference numerals 201 and 209 denote input terminals and output terminals, respectively.

In addition, in the GA 8 VSB mode, 12 symbol segment interleaving (12-SYMBOL INTRA-SEGMENT INTERLEAVING) is adopted at the transmitter side in preparation for NTSC co-channel interference (CO-CHANNEL INTER-FERENCE).

FIG. 4 illustrates a structure of a trellis coded interleaver used in the GA 8 VSB mode, and FIG. 5 illustrates an output of the trellis coded interleaver.

First, the byte data output from the CONVOLUTIONAL INTERLEAVER is processed in byte units by each of the 12 convolutional encoders. In this case, each byte unit data generates 4 symbols of encoded data through one encoder, and symbol data input to the convolutional encoder is input by 2 bits from the most significant bit.

In addition, since data of each byte unit is encoded through one convolutional encoder, twelve times of byte unit data are required to be encoded through twelve convolutional encoders. In other words, one segment is composed of 828 symbols, that is, 207 bytes of data, and is not a multiple of 12 corresponding to the 12 convolutional encoders. 12 × 69 bytes). Thus, as shown in FIG. 6, in segment 0, the first symbols 7 and 6 of the first byte data in the field are encoded by the # 0 encoder, and the first symbols 7 and 6 of the second byte are encoded by the # 1 encoder. The first symbols 7 and 6 of the 12th byte are encoded through the # 11 encoder.

Similarly, the second symbol (5, 4) of the first byte in segment 0 is encoded through the # 0 encoder, and the second symbol (5, 4) of the second byte is input to the # 1 encoder. Coded in symbol units.

On the other hand, in the segment synchronization signal section, four encoders corresponding to the synchronization signal section do not output encoded symbol data because no symbol data is input. Accordingly, as shown in FIG. 5, symbol data encoded in a normal order from the # 0 encoder to the # 11 encoder is output in the first segment of each field, whereas the symbol data from the # 4 encoder to the # 11 encoder is output in the second segment. Is output first, and then coded symbol data from the # 0 encoder to the # 3 encoder are output. In the third segment, symbol data from the # 8 encoder to the # 11 encoder is output first, and then coded symbol data from the # 0 encoder to the # 7 encoder are output.

This three-segment pattern is repeated in the field so that the data symbols after the data segment synchronization signal is inserted are separated by 12 symbols.

6 shows a multiplexing order of byte-symbol conversion and lattice coder.

7 illustrates a trellis coded deinterleaver, and each trellis decoder performs the same function as shown in FIG. 3.

In addition, each lattice decoder operates as a symbol clock, and outputs two bits of decoded data every 12 clocks after receiving symbol data of DECISION DEPTH L. Therefore, every 48 clocks, the grid deinterleaver outputs 12 bytes of decoded data in symbol clock units. That is, every 48 clocks output 12 bytes of decoded data during the last 12 clocks.

The CONVOLUTIONAL DE-INTERLEAVER, which is connected to the output of the lattice code deinterleaver, operates in the unit of byte clock (symbol clock x 4), and thus the clock rate conversion of the grid decoded data is required.

Hereinafter, the operation of the grid code deinterleaver will be described.

First, the symbol data of the first segment in the field received through the GA 8 VSB receiving system is input into a # 0 grid decoder, the second symbol data into a # 1 grid decoder, and the 12th symbol data into a # 11 grid decoder. do. That is, it is divided into 12 groups of (1, 13, 25, ...), (2, 14, 26, ...), ... (12, 24, 36, ...).

In addition, since no data is input to the four grid decoders corresponding to the input sequence in the segment synchronization signal section, the output of the grid decoder outputs invalid data (INVALID DATA) irrelevant to normal decoding. Each of the four grid decoders receives and decodes symbol data 12 clocks later.

Therefore, as shown in FIG. 6, the last symbol data of segment 0 is inputted to the # 11 lattice decoder and decoded, but the first symbol data of segment 1 is inputted to the # 4 lattice decoder rather than the # 0 lattice decoder and decoded. do. That is, the decoding order of the grid decoder in segment 1 is (# 4, # 5, ... # 0, ... # 3), which means that the last symbol data of segment 0 and segment 1 This is because a segment synchronization signal of 4 symbol clocks is inserted between the first symbol data.

Similarly, in segment 2, in the order of grid decoder (# 8, # 9, ... # 0, ..., # 7), in segment 3, again (# 0, # 1, ..., The decoding is performed in the order of # 11).

On the other hand, the format of the decoded data when the DECISION DEPTH L for determining the backtracking specification L is 22 in each lattice decoder constituting the lattice code deinterleaver shown in FIG. That is, one segment 832 symbol is 208 bytes, the data segment synchronizing signal is one byte, and the data is 207 bytes.

In addition, since the convolutional encoding on the transmitting side is performed in units of 828 bytes of 4-segment data, the decoding data format is also repeated in units of 4 segments as shown in FIG.

In Fig. 8, each number represents a byte position in the segment, and from the position, 12 bytes of decoded data are output from the 12 lattice decoders shown in Fig. 7 for 12 clocks (3 byte clocks) in symbol clock units. . That is, the decoded data in segment 0 is the byte position, and each of 12 bytes of decoded data in (4, 5, 6), (16, 17, 18), ... (196, 197, 198) is converted into the symbol clock. Output

In FIG. 8, section-1 is a section in which the decoded data output timing is less than 3 x L in each segment, and shows a section requiring rearrangement of the decoded data. As described above, this is a result of intra-segment interleaving on the transmitting side. When 12-byte data is divided into 4 byte units and named as 0, 1, and 2, respectively, in interval-1 (1, 2, 0) This is because the data is decoded in the order of (1, 2, 0), ..., which is out of order of the data on the transmitting side.

On the other hand, the section-2 is a section in which the output timing of the decoded data in each segment is larger than 3 x L, and this section corresponds to the data order on the transmitting side.

Therefore, when the output of the lattice code deinterleaver of FIG. 7 is input to the convolutional deinterleaver and processed, the original video and audio data of the transmitter cannot be restored.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems. In particular, a 4-port single-port RAM having a 4-segment capacity is provided at the output of the grid decoder, and decoded data is stored in the RAM at a symbol clock rate. After reading, the stored decoded data is read out at the byte clock rate, thereby converting the decoded data in the symbol clock unit into the byte clock unit and controlling the order of the read address when the data is read out. The present invention provides a method for rearranging decoded data of a lattice decoder for high-definition television that can rearrange decoded data.

In order to achieve the above object, Configuration 1 of the present invention "method for rearranging the decoded data of the grid decoder for high definition TV" is a single port RAM having a capacity equal to 4 segments at the output of the grid decoder in a GA 8VSB receiving system. A plurality of circuits are stored, and the decoded data output of the lattice decoder is stored in the upper memory of the RAM in units of four segments, and then the data is read from the previously stored upper memory while storing the decoded data of the next four segments in the lower memory of the RAM. Since the storage and reading operations of the memory of each RAM are performed every four segment units, the decoding data of the symbol clock unit is converted into the decoding data of the byte clock unit, and the decoding data is rearranged at the same time. It is characterized by enemy configuration.

When the decoded data output of the lattice decoder is stored in the RAM, in generating a write address, the modulo-12 symbol counter value is added to the byte counter value indicating the time of output of the decoded data in each segment. It is characterized by storing decoded data of bytes.

The decoded data rearrangement of the lattice decoder may be stored without rearrangement when the decoded data is stored in the RAM, and then rearranged when the stored decoded data is read.

On the other hand, configuration 2 of the present invention " decoding data rearrangement method for a high definition TV grid decoder " includes a single port RAM having a capacity equal to 4 segments at the output end of the grid decoder in the GA 8VSB receiving system. In this case, the data stored in the first half cycle is read out by dividing one cycle of the byte clock, and the decoded data output is stored during the next half cycle. Therefore, the decoded data of the symbol clock unit is converted into the decoded data of the byte clock unit. At the same time, rearrangement of the decoding data is characterized by its methodological structure.

When the decoded data output of the lattice decoder is stored in the RAM, in generating a write address, the modulo-12 symbol counter value is added to the byte counter value indicating the time of output of the decoded data in each segment. It is characterized by storing decoded data of bytes.

The modulo-12 symbol counter value conversion may be performed by multiplying the modulo-12 symbol counter value by 2 to add an inverting symbol clock to the lower 4 bits of the memory. It is used to write address.

The decoded data rearrangement of the lattice decoder may be stored without rearrangement when the decoded data is stored in the RAM, and then rearranged when the stored decoded data is read.

Configurations 1 and 2 of the present invention "method for rearranging the decoded data of the high-definition TV grid decoder" include one single port RAM having the same capacity (828 bytes) as the decoded data output in units of 4 segments in the grid decoder. By rearranging the decoded data output from the lattice decoder while storing or outputting the data, or storing the data without rearrangement and rearranging the decoded data at the output, the decoded data is rearranged and symbol clock unit is used. By converting the decoded data in the unit of byte clock, the output byte data order of the grid code deinterleaver and the byte data input to the grid code interleaver on the transmitter side can be matched.

1 is a diagram showing an example of the configuration of a weaving encoder.

2 is a diagram showing a lattice diagram according to the configuration of FIG.

3 is a block diagram showing the configuration of a Viterbi decoder.

4 is a diagram showing a configuration of a lattice code interleaver.

5 is a diagram showing an output data string of the lattice code interleaver.

6 is a diagram illustrating a multiplexing order of byte-symbol conversion and lattice coder.

7 is a diagram showing the configuration of a lattice code deinterleaver.

8 shows a decoded data format based on a byte counter.

9 is a diagram showing the configuration of Embodiment 1 according to Configuration 1 of the present invention "method for rearranging decoded data of a lattice decoder for high definition TV".

10 is a timing diagram showing a relationship between a byte counter, a symbol counter, and a write validity interval.

FIG. 11 is a diagram showing a configuration of Embodiment 2 according to Configuration 2 of the present invention " Method for rearranging decoded data of a lattice decoder for high definition TV "

12 is a diagram illustrating a conversion relationship between modulo-12 symbol counter values for write address generation.

<Explanation of symbols for main parts of drawing>

307, 308, 406: Single Port RAM 309, 405: Multiplexer

Hereinafter, an embodiment according to the technical idea of the configuration 1 and configuration 2 of the present invention "decoding data rearrangement method of a high-definition TV grid decoder" will be described in detail with reference to the accompanying drawings, the configuration and operation.

Example 1

Embodiment 1 is an embodiment of the configuration 1 according to the technical idea of the present invention "method of rearranging the decoded data of the grid decoder for high-definition TV", as shown in Figure 9, a single 828-byte capacity at the output of the grid decoder A method of rearranging decoded data while converting a clock rate using two port RAMs 307 and 308 is shown.

In Fig. 9, the control _2 304 and the control _3 306 are used as read and write control signals of the upper memory 307 and the lower memory 308, respectively, and the control _1 301 is the multiplexer 309. Control to select the output of the memory operating in the read mode among the outputs from the respective memories 307 and 308, and the read and write modes of the respective memories are always opposite.

In other words, while writing data to the upper memory 307, the lower memory 308 operates in the read mode, and vice versa.

In addition, the mode of each memory is switched in units of 4 segments of 828 bytes. The clock rate conversion and the rearrangement of the decoded data store the data from the upper memory 307 once the decoded data 828 bytes are stored in the upper memory 307 once, and the next decoded data 828 bytes is stored in the lower memory 308. It is executed while reading.

In the figure, reference numeral 302 denotes an address_1, 303 denotes data, 305 denotes an input terminal of address_2, and 310 denotes an output terminal.

On the other hand, when reading data from the memory, the generation of a read address differs according to the section I ("0": section_1, "1": section_2). That is, in section_1, a read address is generated in consideration of the rearrangement of the decoded data order, and in section_2, the read address is read as written.

Hereinafter, the memory read and write address generation method will be described.

Here, the generation of the address RD_addr uses the counter C _B which increases in the unit of byte clock (symbol clock x 4). That is, the interval M_1 is divided into 12 bytes and every 12 bytes are divided into 4 byte units to designate the mode M (= 0, 1, 2).

Therefore, the read address in each section is as follows.

RD_addr = C _B + I '{P × 4-P' × 8}, -------- [1]

I '= not (I), P' = not (P),

P = "1", (M + 1)% 3 ≠ 0

= "0", (M + 1)% 3 = 0

Decoded data of the lattice decoder is continuously output by 12 bytes in symbol clock units, and the output time of the decoded data according to each segment is as shown in FIG.

FIG. 10 shows the relationship between the byte counter C _B , the effective write interval WR_en, and the symbol counter C _{S. The} modulo_12 counter is used as the symbol counter.

The write address WR_addr is equal to the sum of the symbol count value and the first byte counter value C _A in each valid write interval, as shown in equation [2].

WR_addr = C _A + C _S ---------- [2]

The value shown in FIG. 8 represents C _A for generating a write address in each segment.

As described above, Embodiment 1 of Configuration 1 according to the technical idea of the present invention "Method of rearranging decoded data of a grid decoder for high definition TV" is the same capacity as the decoded data output in units of 4 segments in the grid decoder. By using two single fortrams with bytes, the decoded data is rearranged either by rearranging and outputting the decoded data output from the lattice decoder, or by storing and rearranging the data without rearrangement and rearranging it on output. Also, by converting the decoded data in the symbol clock unit into the byte clock unit, the output byte data order of the grid code deinterleaver and the byte data input to the grid code interleaver on the transmitter side can be matched. will be.

Example 2

According to the technical idea of the present invention "method of rearranging the decoded data of a high-definition TV grid decoder", the second embodiment of the configuration 2 has the same capacity as the decoded data at the decoded data output stage of the lattice decoder. It uses one single-port RAM 406 of 828 bytes having two cycles of one cycle of the byte clock to read the data stored in the RAM 406 during the first half cycle and to store the output of the decoded data during the next half cycle. It is.

First, read and write control of the memory is divided into byte clocks, and the read mode is operated in the read mode during the first half cycle and in the write mode during the next half cycle.

In FIG. 11, control_1 404 is generated from the byte clock and used for selection of addresses_1401 and _2402 and memory mode control of RAM 406. In FIG. In addition, the address_1 (401) is used as a write address of the memory, and the address_2 (402) is used as a read address of the memory. The read address is generated in the same manner as in Equation [1], and the write address is generated by converting Equation [2].

In the figure, reference numeral 403 denotes a data input terminal, 407 denotes an output terminal, and 405 denotes a multiplexer.

In addition, since the output timing of the decoded data in each segment is the same as that shown in Fig. 8, the write address is similar to that of Equation [2].

WR_addr = C _A + C _S * --------- [3]

C _S * = LSB ₄ (C _S × 2 + s_clk '),

b _v-1 b _v-2 ... b ₀ = LSB _V (b _n-1 b _n-2 ... b _v b _v-1 b _v-2 ... b _o )

s_clk '= not (s_clk).

Here, the C _A value of the formula [3] is the same as the C _A of the formula [2], and the C _S * value of the formula [3] is the convolution of the C _S value of the formula [2].

On the other hand, since the output of the grid code deinterleaver of Fig. 7 outputs 12 bytes of decoded data for 12 clocks (3 byte clocks) as a symbol clock, a write address of a memory is generated in symbol clock units as shown in equation [2]. 12 bytes of decoded data can be stored in memory.

In addition, in the second embodiment, since the data is used in the read mode during the half cycle of the byte clock (2 symbol clocks), 12 bytes of decoded data must be stored in the memory 36 for 6 symbol clocks. The relationship between the counter C _S and C _S * is shown.

As described above, Embodiment 2 of Configuration 2 according to the technical concept of the present invention "Method of rearranging decoded data of a high-definition TV grid decoder" has the same capacity as the decoded data output in units of 4 segments in the grid decoder. By using one single port RAM, the clock cycle of the byte is divided into two, and the decoded data output from the lattice decoder is stored and rearranged, or stored without rearrangement and stored and rearranged when output. The rearrangement of the decoded data and conversion of the decoded data in the symbol clock unit to the byte clock unit causes the output byte data order of the grid code deinterleaver to match the order of the byte data input to the grid code interleaver on the transmitter side. You will be able to.

This is because, while Embodiment 1 of Configuration 1 according to the technical concept of the present invention uses two 828-byte capacity single port RAM, it is difficult to implement a single chip by increasing the chip area when implementing an error correction ASIC. The difference is that the memory usage can be cut in half by dividing the byte clock by two and repeating read and write, and by changing the write address generation method.

As described above, the configuration 1 and the configuration 2 of the present invention "method for rearranging the decoded data of the grid decoder for high-definition TV" is a single port having the same capacity (828 bytes) as the decoded data output in units of 4 segments in the grid decoder. One or two RAMs are used to rearrange the decoded data by rearranging and outputting the decoded data output from the lattice decoder, or by storing the rearranged data without rearranging and rearranging the decoded data upon output. In addition, since the decoded data in the symbol clock unit is converted into the byte clock unit, the output byte data order of the grid code deinterleaver matches the byte data input to the grid code interleaver on the transmitter side. There is an effect that can be made.

Claims (7)

In the GA 8VSB receiving system, a plurality of single port RAMs having the same capacity as four segments are installed at the output of the grid decoder, and the decoded data output of the grid decoder is stored in the upper memory of the RAM in units of four segments. The data is read from the pre-stored upper memory while storing 4-segment decoded data in the lower memory of the RAM, and thus the storage and read operation of the memory of each RAM is performed every four segment units. A method of rearranging decoded data of a lattice decoder for a high-definition television, comprising converting data into decoded data in byte clock units and rearranging decoded data. The method according to claim 1, wherein when the decoded data output of the lattice decoder is stored in the RAM, a write address is generated, and a modulo-12 symbol counter value is assigned to a byte counter value indicating the time of outputting decoded data in each segment. A decoded data rearrangement method of a lattice decoder for high-definition television, characterized by summing up and storing decoded data of 12 bytes. The high-definition TV set according to claim 1, wherein the decoded data rearrangement of the lattice decoder is stored without rearrangement when the decoded data is stored in the RAM, and then rearranged when the decoded data is read. A method of rearranging decoded data of a lattice decoder. In the GA 8VSB receiving system, after installing a single port RAM with the same capacity as 4 segments at the output of the grid decoder, two cycles of one byte clock are read out and the stored data is read during the first half cycle. The method of rearranging the decoded data of the grid decoder for a high-definition TV characterized by converting the decoded data in the symbol clock unit into decoded data in the byte clock unit and rearranging the decoded data. . The method according to claim 4, wherein when the decoded data output of the lattice decoder is stored in the RAM, a write address is generated, and a modulo-12 symbol counter value is assigned to a byte counter value representing a time point of outputting decoded data in each segment. A decoded data rearranging method of a lattice decoder for high-definition television, characterized by converting and storing decoded data of 12 bytes. The method according to claim 5, wherein the modulo-12 symbol counter value conversion is performed by multiplying a modulo-12 symbol counter value by 2, adding an inverted symbol clock, and then storing only the lower 4 bits of the memory. A decoding data rearrangement method of a grid decoder for a high-definition television, characterized in that it is used for a write address of a. The high-definition TV set according to claim 4, wherein the decoded data rearrangement of the lattice decoder is stored without rearrangement when the decoded data is stored in the RAM, and is rearranged when the stored decoded data is read. A method of rearranging decoded data of a lattice decoder.

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