KR19980075613A - The path metric network device of the trellis decoder - Google Patents

Abstract

The present invention relates to a trellis decoder (TCM decoder), and more particularly, to a path metric network for storing a survivor path of each state according to a Viterbi algorithm and providing the trellis code as a path metric of a next stage, State plurality of outputting a previous path metric (PM _j (t)) of the (S _j (t)) of the survivor metric (SM _j (t)) for storage were the M symbols after the clock delay following step (t + 1) Delay memory means 70 composed of delay registers 70-0 to 70-15; The survivor metric SM _j supplied from the external addition selection comparator ACS or the survivor metric SM _j fed back from the delay memory means 70 is selected in accordance with the rearrangement control signal RE_ARRAY, And a selection means 72 composed of a plurality of multiplexers 72-0 to 72-15 input to the means 70. Since the present invention can simultaneously use up to 8 state modes while having a complexity of 16 state modes The effect of the register amount and the area gain as well as the continuous operation by the multiplexer by the re-arrangement control signal RE_ARRAY occurs in the register, so that a simple control signal generation and logic circuit can be realized.

Description

The path metric network device of the trellis decoder

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a trellis decoder (TCM decoder) for decoding a signal transmitted by a trellis code modulation (TCM) technique, and more particularly, To a path metric network device of a trellis decoder that decodes it according to a non-algorithm, stores survivor path metrics acquired for each state, and provides the survivor path metric as a previous path metric of a next stage.

Generally, a Trellis code modulation (TCM) technique is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel. Modulation technique. The TCM can obtain a significant gain in power over conventional unmodulated modulation schemes without changing the bandwidth. The TCM structure is composed of an encoder with a finite state and a non-binary modulator . On the receiver side, a received signal mixed with noise is decoded using a decoder that performs maximum likelihood decoding by soft-decision. It is known that such a TCM can obtain a power phase gain of 3 to 6 dB or more in a digital signal transmission environment having an additive white Gaussian noise (AWGN) as compared with an unencoded modulator method. In particular, the advantage of the TCM is that this gain in power is not obtained because it reduces the effective information rate as in the case of bandwidth extension or other error correcting codes. Here, the term trellis is used because it can represent a TCM codeword by a state transition diagram similar to a trellis diagram, which is a state diagram of a binary convolution. The difference between the TCM code and the convolutional code is that the TCM codeword is extended to a signal set of arbitrary size by non-binary modulation of the convolutional codeword.

Due to the gain of such encoding in the TCM, the complexity of detection of received data is deteriorated and is widely used at present, and its use range is greatly increased. One of such applications is a transmission system of High Definition television (hereinafter referred to as HDTV).

Meanwhile, in a concatenated coding scheme in which two different encoders are connected to each other in order to enhance data reliability, an inner coder generates an encoded modulated code A well-known convolutional codeword or TCM codeword is used and decoded by a decoder using a Viterbi algorithm. An outer coder is a Reed-Solomon code having T error correction capabilities. In an outer decoder, an uncorrected error is corrected again in an inner decoder to remove an error so that an error rate is almost zero. This connection coding scheme has advantages that it is possible to implement the hardware with less complexity and better performance than using one coding scheme.

The Viterbi algorithm is used for the decoding of the TCM signal. The Viterbi algorithm performs maximum likelihood decoding as described above and uses a trellis diagram to reduce the amount of computation required. Algorithm. This algorithm allows only one survivor path to exist in one state by comparing the similarity between the paths input to each state and the received signal. This process is repeated at each stage according to the time of the Trellis diagram. Therefore, the amount of computation required by the Viterbi algorithm depends on the length of the transmitted code string, but depends on the number of states.

1 is a block diagram of a trellis decoder to which a Viterbi algorithm is applied. The trellis decoder includes a branch metric calculation unit (BMU) 11, an add comparator select unit (ACS): 12, a path metric network (PMN): 13, and a survivor memory unit (SMU): 14. Here, the branch metric is a value obtained by calculating a distance between codes in a branch corresponding to a received signal, and this distance serves as a reference for signal discrimination. The metric is a Hamming distance in the case of hard-decision decoding and the Euclidean distance in the case of soft-decision. The path metric corresponds to the accumulated value of all branch metrics that the received signal has traveled up to the current state over time.

The branch metric calculation unit BMU 11 calculates a distance between the received input code and a reference value on each branch and provides the branch metric BM (t) to the addition comparison selection unit (ACS) 12.

The addition comparison selection unit (ACS) 12 calculates a path metric, which is a value obtained by accumulating all the branch metrics on the most probable path from the path input to each state S _j (t) to its state. The branch metric BM (t) provided from the branch metric calculator (BMU) 11 and the branch metric BM (t) provided from the branch metric network (PMN) 13 serve to select a path having a minimum path metric for each state. (I.e., accumulating a number of branch metrics that have been merged in the current state on the previous path metric), and adding the accumulated number of accumulated path metrics (PM (t-1)) in the current state Compares the path metrics, selects a path metric having a smaller value among the path metrics, and outputs the path metric to the survivor metric SM (t). The selected path metric is provided to the path metric network (PMN) 13, and information for tracing the selected path is provided to the survivor memory unit (SMU) 14.

The path metric network (PMN) 13 receives and stores the survivor metric SM (t) output from the ACS 12 and stores the previous path metric PM (t) t-1)) to the ACS (12).

The survivor memory unit (SMU) 14 maintains the survivor path information by the length of the survivor path, that is, the decoding depth, in order to perform reverse tracking on the survivor path of each state, and outputs the final recovered symbol according to the traceback algorithm.

An example of a trellis decoder having such a structure is a trellis decoder of a GA HDTV receiving system proposed by the Grand Alliance (GA), which is established to establish HDTV standards in the United States.

In the GA HDTV transmission system, data is transmitted in 8-level VSB mode by trellis coding and transmitted frame by frame. Referring to the frame structure of the GA HDTV system shown in FIG. 2, one frame is composed of two fields, and one field is made up of 313 segments. Each segment is composed of 4 segments of segment sync signal and 828 data + error correction symbols (Data + FEC), and the first segment of each field is assigned to a field sync signal (Field Sync) have.

In the process of generating a transmission signal, a random signal is subjected to Reed-Solomon coding, interleaved and then Trellis coded, and a Segment Sync signal and a Field Sync signal are inserted therein. Then, after inserting the pilot signal, VSB modulation is performed and the signal is transmitted to the carrier.

3 is a block diagram of a trellis coded block of a GA 8 level VSB mode. The trellis coder includes a pre-coder 30, a trellis encoder 32, and an 8-level symbol mapper 8- level symbol mappe r: 34).

The upper input bit X1 is subjected to exclusive OR operation with the previous bit delayed by 12 symbols through the precoder 30 to become an intermediate output bit Y1 and the intermediate output bit Y1 is encoded by the trellis encoder 32 Level symbol mapper 34 as it is, and is output as the input bit Z2 of the 8-level symbol mapper 34 as it is. The lower input bit (X0) is input to the trellis encoder (32) Encoded and output as the input bits (Z1, Z0) of the 8-level symbol mapper (24). Thus, Level symbols (R: -7, -5, -3, -1, -1, and +3) in the 8-level symbol mapper 34 are obtained from the trellis coder , + 5, + 7) and is transmitted as an 8-level VSB modulation signal.

On the other hand, Trellis coding has strong characteristics against white Gaussian noise (AWGN), but since the cluster error is weak, twelve trellis coded blocks of FIG. 3 are arranged in parallel to sequentially apply the input symbols to the encoder, Intra segment interleaving was performed, which is shown in FIG.

An input switch 40 for outputting data input from the outside in units of bytes on a per-symbol basis (2 bits each: X1, X0), as shown in FIG. 4; 12 trellis code blocks E1 to E12 constituted by the pre-encoder 30 and the trellis encoder 32 of FIG. 3 receiving the input data and the 12 trellis code blocks E1 to E12 output from the 12 trellis code blocks E1 to E12 Level symbol mapper 34 shown in Fig. 3 in order. It should be noted that the input switch 40 and the output switch 42 are operated in synchronization with each other.

5 is a block diagram of the trellis code deinterleaver in the GA HDTV receiving system. In the trellis code deinterleaver, the TCM codeword on the transmitting side is interleaved in units of 12 symbols. Therefore, on the receiving side, twelve trellis decoders (D1 to D12) are implemented in parallel to perform de-interleaving. Therefore, each trellis decoder receives the 12th symbol of the input symbol stream and performs decoding while deinterleaving it.

On the other hand, the TCM decoding path has two paths depending on the use of the NTSC interference cancellation filter, which is shown in FIG. 6, if an NTSC interference cancellation filter is not used, an optimal trellis decoder 65 for a Gaussian (AWGN) channel decoding in 8-state mode can be used in restoring received symbols. If an NTSC Since the input level of the signal passed through the interference elimination filter 61 is converted from the 8th level to the 15th level due to the characteristics of the transfer function of the filter, a Trellis decoder 63 for the 16-state mode decoding suitable for this purpose should be used.

As described above, in the conventional trellis decoder, an 8-state mode optimal trellis decoder 65 and a 16-state mode partial response trellis decoder 63 are separately provided depending on whether an NTSC interference cancellation filter is used, There was a problem.

5, when deinterleaving and trellis decoding are performed using twelve equal trellis decoders D1 to D12, only one decoder operates for every 12 symbol clocks, and the remaining 11 decoders it does not work. That is, 12 decoders used in the receiver do not operate at the same time every input, meaning that one decoder can be shared by time division by 12 symbols. Of course, in the case of using 12 trellis decoders, it is easy to design because the same decoder can be repeatedly implemented, but an increase in area can not be avoided. Although one trellis decoder is more difficult to implement, an area gain can be obtained. Here, when one trellis decoder is time-divisionally used in units of 12 symbols, the data must be processed so as not to be influenced by the segment sync signal. In particular, in a path metric network (PMN) that provides a path metric, the survivor metric that was previously stored should be maintained while the segment sync signal is input, and the path metric needed in the next step should be provided.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in order to solve the above-mentioned problems, and it is an object of the present invention to provide an apparatus and a method for managing a path synchronizing signal by rearranging stored data in a memory while maintaining an existing path metric while a segment synchronous signal is input Of course, it is an object of the present invention to provide a path metric network apparatus that supports a 16-state mode and an 8-state mode simultaneously while having a complexity of 16-state mode.

In order to achieve the above object, the apparatus of the present invention performs M-interlace segment interleaving to generate a trellis code stream di (1? I? M: an index for distinguishing data output from an i-th trellis encoder) In a path metric network in which a survivor metric of each state S _j (t) is decoded by a Viterbi algorithm to store a survivor metric of each state calculated in a summation comparison selection unit and provided as a previous path metric of a next step, A delay memory unit for storing the delayed data SM _j (t) and outputting the previous path metric PM _j (t) of the next step (t + 1) after the M symbol clock delay; reordering control signal (RE_ARRAY) fed back from the survivor metric (SM _j) or the delay provided by the memory unit of the external addition comparison selection part (ACS) in accordance with the input arrangement for Alternatively to the survivor metric (SM _j) is characterized in that comprises a selecting section for input to the delay memory.

1 is a block diagram of a general trellis decoder to which a Viterbi algorithm is applied,

2 is a data unit frame structure in a GA (Grand Alliance) HDTV (High Definition Television) transmission system,

FIG. 3 is a block diagram of an 8-level residual side trellis coded block in a GA HDTV transmission system;

FIG. 4 is a block diagram of a trellis code interleaver that performs intra-segment interleaving using FIG. 3;

5 is a block diagram of a trellis code deinterleaver in a GA HDTV receiving system,

FIG. 6 is a block diagram of a trellis decoder according to whether an NTSC interference cancellation filter is used or not;

7 is a configuration diagram of a path metric network apparatus according to the present invention.

Description of the Related Art [0002]

70: Selection means 70-0 to 70-15: Multiplexer

72: delay memory means 72-0 to 72-15: 12 symbol delay registers

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, a Trellis decoder conforming to the GA HDTV transmission standard will be exemplified. The GA HDTV transmission standard performs intersegment interleaving and intrasegment interleaving to improve robustness against cluster errors. The inter-segment interleaving is performed at a 1/3 depth of a data frame in units of bytes (8 bits) through an external interleaver before Trellis coding. The intra-segment interleaving is performed at intervals of 12 symbols (1 symbol = 2 bits) through twelve trellis encoders as shown in FIG. The intersegment interleaved data is input to twelve trellis encoders for intra-segment interleaving and encoding. The code stream output through the trellis code interleaver can be represented as a segment [as shown in Table 1 below.

[Table 1]

Segment Group 1 Group 2 ... Group 69 One d1, d2, d3 ... d12 d1, d2, d3 ... d12 ... d1, d2, d3 ... d12 2 d5, d6, d7 ... d4 d5, d6, d7 ... d4 ... d5, d6, d7 ... d4 3 d9, d10, d11 ... d8 d9, d10, d11 ... d8 ... d9, d10, d11 ... d8 4 d1, d2, d3 ... d12 d1, d2, d3 ... d12 ... d1, d2, d3 ... d12 5 d5, d6, d7 ... d4 d5, d6, d7 ... d4 ... d5, d6, d7 ... d4 : ... ... ... ...

In Table 1, each group is divided into twelve symbols because it is subjected to intra-segment interleaving of 12 symbols, and the index attached to each data is the same as the index of the trellis code block of FIG. That is, d1 is the data output from the first trellis code block E1, and d2 is the data output from the second trellis code block E2. The output data stream of the trellis coded block is repeated in a three-segment cycle. For example, the zeroth segment starts with data d1 output from the first trellis coded block E1 and outputs d2, d3 ... And the first segment is outputted in the order of d6, d7, ... starting from the data d5 output from the fifth trellis code block E5. And the second segment is outputted starting from the data d9 outputted from the ninth trellis code block E9 because the switch of the interleaver is switched even when four segments of the segment synchronous signal in which each segment starts are inputted It is because it is working. Therefore, the data stream shown in Table 1 must be input to the trellis decoder Di of FIG. 5 in which the indexes coincide with each other. That is, d1 is valid data for the first trellis decoder D1 and d2 is valid data for the second trellis decoder D2. Therefore, in order to decode the trellis codeword interleaved by twelve encoders with one trellis decoder according to the present invention, the data-to-viterbi algorithm generated from the same encoder must be applied. FIG. 7 is a block diagram of a path metric network apparatus according to the present invention.

FIG. 7 is a block diagram of a path metric network apparatus according to the present invention. The path memory network apparatus according to the present invention includes a delay memory unit 70 composed of a plurality of delay registers, and a selection unit 72 composed of a plurality of multiplexers. The delay memory unit 70 includes 0th to 15th delay registers 70-0 to 70-15, and each delay register is composed of 12 serial input serial output shift registers. The selector 72 selects the survivor metric SM _j or the previous path metric PM _j fed back from the delay memory 70 according to the rearrangement control signal RE_ARRAY, And a fifteenth multiplexer 72-0 to 72-15.

The operation and effect of the path metric network configured as described above will be described below.

One survivor metric calculated through an external additive comparison selection unit (ACS) exists for each state, and the survivor metric is allocated to an integer part 7 bits and a decimal part 3 bits through simulation. The path metric network PMN stores the survivor metric selected in each state and provides 12 clocks to the ACS. The reason for delaying the 12 clocks is as follows. And the data associated with itself is input to the decoder with a delay of the symbol. Therefore, the path metric network PMN requires 192 (= 16state × 12delay) 10-bit registers in the 16-state mode and requires 96 (= 8state × 12delay) 10-bit registers in the 8-state mode. Therefore, in the 8-state mode, only 96 out of the 192 registers need to be used effectively, so that it is possible to support up to eight states simultaneously with the complexity of the 16-state mode.

The 0th to 15th delay registers 70-0 to 70-15 of the delay memory unit 70 store the survivor metrics of each state from the addition comparison selection unit ACS, And outputs it to the selection unit ACS.

At this time, the data sequence stored in each delay register of the delay memory unit must be rearranged without receiving the survivor metric from the ACS for four clocks during which four clocks of the segment sync signal are input. This is because the order of data input to the decoder changes because the interleaver is switching even while the segment sync signal is being input. For example, as shown in Table 1, the first data of the first segment input to the decoder are sequentially input starting from d1 (output of the first encoder), while four symbols of the second segment are input , The first data is input in order starting from d5 (the output of the fifth encoder). Therefore, the previous path metric value provided by the path metric network must also output the path metric related to the d5 data after the synchronization signal is input.

The zeroth to fifteenth multiplexers 72-0 to 72-15 of the selector 72 select the 0th to the 15th multiplexers 72-0 to 72-15 for the 4 clocks in which the segment sync signal is input according to the reorder control signal RA_ARRAY, To 15th delay registers 70-0 to 70-15 and inputs the data to the first stage of the 0th to 15th delay registers 70-0 to 70-15. In the remaining clocks, the survivor metric provided from the outside is input and input to the first stage of the zeroth through fifteenth delay registers. Here, the rearrangement control signal RE_ARRAY has a first level (high) for four clocks for inputting a segment sync signal using a counter for counting a segment length (= 832 symbols), and other effective data is input And has a second level (low) for 828 clocks.

That is, in the 0th to 15th delay registers 70-1 to 70-15 of the delay memory unit 70, when data is not exchanged with the external device (addition comparison selection unit) during the clock period in which the segment sync signal is input The stored data sequence is rearranged. Accordingly, the valid previous path metric corresponding to the order of the currently input data for each clock is provided to the addition comparison selection unit (ACS).

While the invention has been described in connection with specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

As described above, since the path metric network of the present invention can be used in the 8-state mode while having the complexity of the 16-state mode, there is an effect of the amount of the register and the area gain. In addition, since the continuous operation is performed in the register by using the multiplexer by the re-array control signal RE_ARRAY, it is possible to realize a simple control signal generation and a logic circuit.

Claims (6)

M symbol intra segment interleaved to decode the trellis code stream di (1? I? M: an index for distinguishing data output from the i-th trellis encoder) by a Viterbi algorithm, (PM _j ) storing a survivor metric (SM _{j: j} is an index for distinguishing a state) of each state calculated in the path metric network (PM _j ) A delay that stores the survivor metric SM _j (t) of each state S _j (t) and outputs it as the previous path metric PM _j (t) of the next step t + 1 after the M symbol clock delay Memory means (70); The survivor metric SM _j supplied from the external addition selection comparator ACS or the delay memory means 70 provided from the external addition selection comparator ACS in accordance with the rearrangement control signal RE_ARRAY for rearranging the data order of the delay memory means 70 And selection means (72) for selecting the feedback input survivor metric (SM _j ) to be input to the delay memory means (70). 2. The apparatus of claim 1, wherein the delay memory means (70) comprises a plurality of delay registers (70-0 to 70-15) for storing the survivor metrics (SMj) The path metric network device of the trellis decoder. 3. The apparatus of claim 2, wherein the plurality of delay registers (70-0 to 70-15) comprise M serial input serial output shift registers for shifting data input in synchronization with each symbol clock. A path metric network device of a trellis decoder. The apparatus according to claim 1, wherein the selector (72) selects one of the plurality of delay registers (70-0 to 70-15) for four clocks during which a segment sync signal is input according to a rearrangement control signal (RA_ARRAY) And outputs the data to the first stage of the plurality of delay registers 70 - 0 to 70 - 15. In the other remaining clocks, the data supplied from the external addition comparison unit (ACS) And a plurality of multiplexers 72-0 to 72-15 for inputting the survivor metric SM _j to the first stage of the plurality of delay registers 70-0 to 70-15. The path metric network device of the decoder. The apparatus of claim 1, wherein the rearrangement control signal (RE_ARRAY) has a first level value during a clock period in which a segment sync signal is input using a counter for counting a unit segment length (= 832 symbols) Is a signal having a second level value. ≪ Desc / Clms Page number 20 > 2. The path metric network apparatus of claim 1, wherein M is 12. 12. The apparatus of claim 1,