KR19980072601A - Branch Metric Calculator - Google Patents

Abstract

The present invention relates to a trellis decoder (TCM decoder), the branch metric calculation apparatus implemented to support the branch metrics of the received symbol having a different reference level at the same time in calculating the branch metric by the Viterbi algorithm The reference level selection means 41 selects and outputs a reference level of a branch of the M-level received symbol according to the mode selection control signal MODE_SEL, and calculates an error between the M-level received symbol and the reference level. From the branch selecting means 45 and the branch selecting means 45 for selectively outputting a value output from the adding means 43 or 0 in accordance with the addition means 43 for outputting, the mode selection control signal MODE_SEL. It is composed of the absolute value calculating means 47 for taking the absolute value of the output value and outputting M branch metrics (BMi). The calculating device selects a unique reference level for a branch in each mode by using a control signal that distinguishes between 8-state and 16-state modes, and adds and compares the selection unit by calculating and providing all branch metrics for the received symbol simultaneously. By selecting and using only the branch metrics required in the branch, branch metric calculators that support multiple modes can be manufactured on a single chip to obtain minimum hardware and area efficiency.

Description

Branch Metric Calculator

The present invention relates to a trellis decoder (TCM decoder) for decoding a signal transmitted by a trellis coded modualtion technique, and more particularly, in calculating a branch metric by a Viterbi algorithm. The present invention relates to a branch metric calculation apparatus implemented to simultaneously support branch metrics of received symbols having different reference levels.

In general, the trellis coded modulation (TLM) technique is a channel encoding technique for obtaining a high coding gain in a bandwidth-limited channel. It is implemented by combining modulation techniques. TCM can achieve significant power gains over conventional uncoded modulation without changing bandwidth. The TCM structure consists of an encoder and a non-binary modulator with finite states. It is done. At the receiver side, the noisy received signal is decoded using a decoder that performs maximum likelihood decoding by soft-decision. Compared with the uncoded modulation method, the TCM is known to obtain a power gain of 3 to 6 dB or more in a digital signal transmission environment with white Gaussian noise. In particular, the advantage of TCM is that this power gain is not obtained by reducing the effective information rate as in the case of bandwidth expansion or other error correction codes. The term trellis is used here because the TCM codeword can be represented by a state transition diagram similar to the trellis diagram, which is a state diagram of binary convolutional code. The difference between the TCM code and the convolutional code is that TCM extends the convolutional codeword into a signal set having an arbitrary size by non-binary modulation.

In spite of the complexity of the received data detection because of the gain of the encoding of the TCM, it is currently widely used, and its use range is greatly increased. One application field is a transmission system for high definition television (HDTV).

On the other hand, in a concatenated coding technique in which two different coders are continuously connected to each other to improve the reliability of data, an inner coder generates an encoded modulation code. Well-known convolutional codes or TCM codewords are used, and decoding is performed by a decoder using the Viterbi algorithm. The outer coder may be a Reed-Solomon code having T error correction capabilities. The external decoder typically corrects the errors that the internal decoder did not correct to remove the error so that the error rate is nearly zero. This concatenation coding technique has the advantage of being able to implement good performance while being less complex in hardware than using one coding technique.

The Viterbi algorithm is used to decode the TCM signal, which performs the maximum likelihood decoding already mentioned and uses trellis diagrams to reduce the amount of computation required. to be. This algorithm allows only one survivor path to exist in a state by comparing the similarity between the paths input to each state and the received signal. This process is repeated at each stage of the trellis diagram over time. Therefore, the amount of computation required by the Viterbi algorithm is not dependent on the length of the transmission code string but depends on the state number.

1 is a configuration diagram of a trellis decoder to which the Viterbi algorithm is applied. The trellis decoder includes a branch metric calculation unit (BMC) 11 and an add compare select unit. (ACS): 12), path metric network (PMN): 13, and survivor memory unit (SMU): 14. Here, a metric is a value obtained by calculating the distance between codes in a branch corresponding to a received signal, and this distance serves as a reference for signal discrimination. The metric is the Hamming distance for hard-decision decoding and the Euclidean distance for soft-decision.

The branch metric calculation unit (BMC) 11 receives a received symbol and calculates a distance between a path passing through each state and a received symbol by using a trellis diagram, and compares the branch metric BMt with the result. Provided to the selection unit (ACS) 12.

The addition comparison selection unit (ACS) 12 serves to select a path having a minimum path metric among the paths input to each state at each time t, and includes a plurality of branch metric calculation units (BMC) 11 provided. The branch metric (BMt) and the previous route metric (PMt-1) provided from the route metric network (PMN) 13 are added and added (scaling a number of branch metrics merged from the current state to the previous route metric). Comparing a plurality of accumulated path metrics in, selects the path metric having the smallest value among them. The selected route metric is called a survivor path and is provided to the route metric network (PMN: 13), and the information necessary to find a reconstruction symbol by advancing the surviving path according to a traceback algorithm (Traceback Algorithm) is provided. It is provided to the survivor memory unit (SMU) 14.

The survivor memory unit SMU 14 traces back a predetermined decoding depth and outputs the last reconstructed symbol.

An example of a trellis decoder having such a structure is a trellis decoder employed in a GA HDTV reception system proposed by the Grand Alliance (GA), which was formed to establish high definition televison (HDTV) standards in the United States. Can be. In GA HDTV, a trellis coded signal is transmitted by modulating an 8-level residual sideband (VSB), and the receiving side has two decoding paths depending on whether an NTSC interference cancellation filter is used. In other words, in recovering the received symbol, if the NTSC interference cancellation filter is not used, a decoder having the same eight levels (8 states) as the encoder in the transmitter may be used. Because the input level is converted from 8 levels to 15 levels (16 states), a trellis decoder must be used.

As described above, in the conventional trellis decoder, a trellis decoder suitable for each state is separately provided to decode signals having different levels. Because the branch metric between the previous state and the current state is a value calculated from the difference between the received symbol and the reference level, the branch for calculating the 8 state branch metric because the 8 level of the 8 state and the 15 level reference value of the 16 state are different from each other. A metric calculation device and a branch metric calculation device for calculating 16 state branch metrics had to be designed respectively.

Therefore, the conventional decoder includes a device for calculating each branch metric according to different modes (8 state mode and 16 state mode) and calculates each branch metric so that a considerable amount of hardware is required. There was a problem that the cost and area are increased.

Accordingly, the present invention has been made to solve the above problems, the present invention is to select the reference level according to the mode selection control signal so that the branch metrics of the received symbols having different reference levels can be obtained at the same time It is an object of the present invention to provide a branch metric calculation device that reduces the amount of hardware and increases the area efficiency.

In order to achieve the above object, the apparatus of the present invention is a device for calculating a branch metric for decoding using a Viterbi algorithm, wherein the branch reference level of the M-level received symbol is selected and output according to a mode selection control signal. A reference level selector, an adder which calculates and outputs an error between the M-level received symbol and a reference level, a branch selector which selectively outputs a value or 0 output from the adder according to the mode selection control signal; And an absolute value calculator which takes an absolute value of the value output from the branch selector and outputs M branch metrics.

The branch metric calculation apparatus as described above has the effect of increasing hardware reduction and area efficiency by simultaneously implementing and supporting different modes in one chip, compared to the conventional manufacturing separately according to the conventional modes.

1 is a configuration diagram of a trellis decoder to which the Viterbi algorithm is applied;

2 is a block diagram of an apparatus for trellis-coding data in an GA HDTV transmission system and mapping the data into 8-level symbols;

3 is a configuration diagram of a trellis decoder in a GA HDTV receiving system;

4 is a block diagram of a branch metric calculation apparatus according to the present invention;

FIG. 5 is an exemplary circuit diagram of an 8-state / 16-state multi-mode branch metric calculation apparatus according to FIG. 4.

Explanation of symbols on the main parts of the drawings

41: reference level selector m1 to m14: memory (ROM)

41-1 to 41-7: 2 input multiplexer (MUX) 43: Adder

m15 to m22: memory (ROM)

43-1 to 43-15: 2-input adder (ADD) 45: Branch selector

45-1 to 45-2: 2-input multiplexer (MUX) 47: Absolute calculation unit

47-1 ∼ 47-15: Absolute value calculator BMi: Branch metric

RY_SYM: M-level received symbol

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, in the present specification, an embodiment of the present invention will be described by taking a trellis decoder of the GA HDTV standard as an example. To understand the trellis decoding of the GA HDTV standard, the encoding process of the trellis code is as follows.

FIG. 2 is a block diagram of an apparatus for trellis-coding data in a GA HDTV transmission system and mapping them into 8-level symbols. The trellis code and the mapping apparatus are data in symbol units (2 bits: X1, X0). To a pre-coder (20), a trellis encoder (22), and an 8-level symbol mapper (24) to output the final mapped 8-level symbol (R). Consists of.

The precoder 20 receives the input bit X1 through the first exclusive logic gate 20-1 and exclusively ORs the previous bit delayed by 12 symbols from the first D flip-flop 20-2. Y1), and the intermediate output bit Y1 does not change and corresponds to the input bit Z2 of the eight-level symbol mapper 24 as it is.

The trellis encoder 22 receives the input bit X0 and becomes the intermediate output bit Y0 as it is, and the intermediate output bit Y0 is the input bit Z1 of the eight-level symbol mapper 14. Generate. At the same time, the previous bit 12 symbols delayed from the intermediate bit Y1 and the second D flip-flop 22-1 is exclusive-ORed through the second exclusive OR gate 22-2 to form a third D flip-flop 22-. 3) is output. The third D flip-flop 22-3 also delays data by 12 symbols and feeds back the second D flip-flop 22-1, and at the same time, the input bit Z0 of the eight-level symbol mapper 24 is input. To occur.

Now, in the eight-level symbol mapper 14, an eight-level symbol (R: -7, -5, -3, -1, -1, + 3, + 5) is output according to the output three bits (Z2, Z1, Z0). , +7), and the converted symbol is transmitted with 8-level VSB modulation.

3 is a configuration diagram of a trellis decoder in a GA HDTV reception system, in which two kinds of decoders are used depending on whether an NTSC interference cancellation filter is used. The optimum response decoder 35 performs 8 state trellis decoding on the received signal transmitted at 8 levels. The partial response trellis decoder 33 receives the 15-level received symbol and performs 16 state trellis decoding. In other words, the signal transmitted at the 8th level passes through the NTSC interference cancellation filter 31, and is subjected to an exclusive logical sum operation with the signal inputted 12 clocks ago, so that the output signal 32 of the NTSC interference cancellation filter 31 is converted to the 15th level. Because it becomes. The 15 levels of the output signal 32 of the NTSC interference cancellation filter are -14, -12, -10, -8, -6, -4, -2, 0, +2, +4, +6, +8, + 10, +12, +14, and the bits used to distinguish them are 4 bits (2 ⁴ = 16 states), which requires 16 states.

The previous state and the current state determined according to the input and output signals according to FIGS. 2 and 3 are shown in Table 1 and Table 2 below. Table 1 corresponds to the case of 8 state, and Table 2 corresponds to the case of 16 state. . The input bits X1 and X0 shown in Table 1 below are symbols input to the trellis encoder of FIG. 2, and the states on the trellis are the bits Z2, Z1 and Z0 output from FIG. 2. The received bits are input to the symbol mapper and converted into reference level values (-7 to +7), respectively, and these reference levels correspond to channel symbols.

Previous state (S2'S1'S0 ') Input bit (X1 X0) Current output (Z2Z1Z0) Current state (S2S1S0) Channel symbol Decryption symbol 000 00011011 000010100110 000001100101 -7-3 + 1 +5 00011011 001 00011011 001011101111 010011110111 -5-1 + 3 + 7 00011011 010 00011011 000010100110 001000101100 -7-3 + 1 + 5 00011011 011 00011011 001011101111 011010111110 -5-1 + 3 +7 00011011 100 00011011 100110000010 100101000001 + 1 + 5-7-3 00011011 101 00011011 101111001011 110111010011 + 3 + 7-3-1 00011011 110 00011011 100110000010 101100001000 + 1 + 5-7-3 00011011 111 00011011 101111001011 111110011010 + 3 + 7-5-1 00011011

As shown in Table 1, in the decoder receiving the 8-level modulated signal, when the trellis is drawn with eight states, the progress from the previous state to the current state is four according to the input bits (X1, X0). You have a branch.

For example, four branches generated according to the input bits in one previous state S '111 may be entered when the current bit S enters X (00) and the current bit S X enters X (01). There are four cases where the current state S 110, when the input bit enters X (10), transitions to the current state S 01 1, and when the input bit enters X 11, the current state S 110.

Subsequently, in the case of the 16 states shown in Table 2, the input bits (X1, X0) are symbols input to the trellis encoder of FIG. 2, and the most significant bits (MSB) S3 ', S3 in the previous state and the current state are shown in FIG. 2 is the state of the first D flip-flop 20-2, S2 ', S2 is the state of the second flip-flop 22-1, and S1', S1 is the state of the third flip-flop 22-3. And S0 ', S0 are the state of the middle bit of the delay register 31-1 in FIG. The previous outputs Z2 ', Z1', and Z0 'and the current outputs Z2, Z1 and Z0 are bits that are input to the symbol mapper of FIG.

Previous state (S3'S2'S1'S0 ') Previous output (Z2'Z1'Z0 ') Input bit (X1 X0) Current output (Z2 Z1 Z0) Channel symbol Current State (S3S2S1S0) Decryption symbol 0000 000 (-7) 00011011 000 (-7) 010 (-3) 100 (+1) 110 (+5) 0 + 4 + 8 + 12 0000001110001011 00011011 0001 010 (-3) 00011011 000 (-7) 010 (-3) 100 (+1) 110 (+5) -40 + 4 + 8 0000001110001011 00011011 0010 000 (-7) 00011011 001 (-5) 011 (-1) 101 (+3) 111 (+7) + 2 + 6 + 10 + 14 0100011111001111 00011011 0011 010 (-3) 00011011 001 (-5) 011 (-1) 101 (+3) 111 (+7) -2 + 2 + 6 + 10 0100011111001111 00011011 0100 001 (-5) 00011011 000 (-7) 010 (-3) 100 (+1) 110 (+5) -2 + 2 + 6 + 10 0010000110101001 00011011 0101 011 (-1) 00011011 000 (-7) 010 (-3) 100 (+1) 110 (+5) -6-2 + 2 + 6 0010000110101001 00011011 0110 001 (-5) 00011011 001 (-5) 011 (-1) 101 (+3) 111 (+7) 0 + 4 + 8 + 12 0110010111101101 00011011 0111 011 (-1) 00011011 001 (-5) 011 (-1) 101 (+3) 111 (+7) -40 + 4 + 8 0110010111101101 00011011

Previous state (S3'S2'S1'S0 ') Previous output (Z2'Z1'Z0 ') Input bit (X1 X0) Output bit (Z2Z1Z0) Channel symbol Current state (S3S2S1S0) Decryption symbol 1000 100 (+1) 00011011 100 (+1) 110 (+5) 000 (-7) 010 (-3) 0 + 4-8-4 1000101100000011 00011011 1001 110 (+5) 00011011 100 (+1) 110 (+5) 000 (-7) 010 (-3) -40-12-8 1000101100000011 00011011 1010 100 (+1) 00011011 101 (+3) 111 (+7) 001 (-5) 011 (-1) + 2 + 6-6-2 1100111101000111 00011011 1011 110 (+5) 00011011 101 (+3) 111 (+7) 001 (-5) 011 (-1) -2 + 2-10-6 1100111101000111 00011011 1100 101 (+3) 00011011 100 (+1) 110 (+5) 000 (-7) 010 (-3) -2 + 2-10-6 1010100100100001 00011011 1101 111 (+7) 00011011 100 (+1) 110 (+5) 000 (-7) 010 (-3) -6-2-14-10 1010100100100001 00011011 1110 101 (+3) 00011011 101 (+3) 111 (+7) 001 (-5) 011 (-1) 0 + 4-8-4 1110110101100101 00011011 1111 111 (+7) 00011011 101 (+3) 111 (+7) 001 (-5) 011 (-1) -40-12-8 1110110101100101 00 011011

As shown in Table 2 above, when the 8-level modulated signal is converted to 15 levels through an NTSC cancellation filter to draw 16 state trellis for the received signal, the progression from the previous state to the current state is applied to the input bit. You will have four branches. The channel symbol corresponds to a value obtained by subtracting the current output Z from the previous output Z ', and the same decoding symbol as the input symbol is obtained using the previous state S', the channel symbol, and the current state S.

In Table 1 and Table 2, the channel symbols are possible under an ideal communication environment without noise, and the signals transmitted through the communication path in which the actual white Gaussian noise exists are mixed with noise. Therefore, in practice, the channel symbols are not exactly the same as the values shown in the table above, and the channel symbol values in the table are reference values for measuring the error of the received signal in performing the maximum approximate decoding by applying the Viterbi algorithm. )to be. That is, the branch metric is the received signal-reference level. If the branch of the correct path is a branch metric has a '0', due to the noise effect has a value close to '0' rather than '0'.

Here, the conventional trellis decoder separately implements a branch metric calculator that calculates four branch metrics of each state. That is, a significant amount of hardware was required to calculate 32 (= 4 branch x 8 state) branch metrics in an 8 state decoder and 64 (= 4 branch x 16 state) branch metrics in an 16 state decoder. However, as shown in Table 1, there are only eight branch metric values corresponding to eight-level reference values in eight states, and only fifteen branch metric values corresponding to fifteen-level reference values in sixteen states. Therefore, conventionally, there was a waste of repeatedly finding the same metric, and there was a waste of separately designing the TCM decoder separately from 8 states and 16 states.

Therefore, the branch metric calculation apparatus of the present invention can be used in both 8-state mode and 16-state mode using a mode selection control signal, and is designed to calculate all possible branch metrics for the received signal only once.

Branch metric calculation rules to be applied to the present invention are shown in Tables 3 and 4 below. Table 3 below is a branch metric calculation rule in 8 states, and Table 4 below is a branch metric calculation rule in 16 states.

8 state TCM branch metric Reference value Branch Metrics (BM) -7 BM1 = ∥ input + 7 ∥ -3 BM2 = ∥ input + 3 ∥ -5 BM3 = ∥ input + 5 ∥ -One BM4 = ∥ input + 1 ∥ +1 BM5 = ∥ input-1 ∥ +5 BM6 = ∥ input-5 ∥ +3 BM7 = ∥ input-3 ∥ +7 BM8 = ∥ input-7 ∥

16 state TCM branch metrics Reference value Branch Metrics (BM) 0 BM1 = ∥ input ∥ -4 BM2 = ∥ input + 4 ∥ -8 BM3 = ∥ input + 8 ∥ -12 BM4 = ∥ input + 12 ∥ +2 BM5 = ∥ input-2 ∥ -2 BM6 = ∥ input + 2 ∥ -6 BM7 = ∥ input + 6 ∥ -10 BM8 = ∥ input + 10 ∥ -14 BM9 = ∥ input + 14 ∥ +4 BM10 = ∥ input-4 ∥ +6 BM11 = ∥ input-6 ∥ +8 BM12 = ∥ input-8 ∥ +10 BM13 = ∥ input-10 ∥ +12 BM14 = ∥ input-12 ∥ +14 BM15 = ∥ input-14 ∥

As shown in Table 3 and Table 4, the branch metric is obtained as an absolute value of the difference between the input signal (input) and the reference value (channel symbol), and distinguishes whether the currently received signal is 8 state or 16 state. This allows you to choose between two levels of operation by selecting the reference level.

4 is a configuration diagram of a branch metric calculation apparatus according to the present invention, and the present invention includes a reference level selector 41, an adder 43, a branch selector 45, and an absolute value calculator 47. Consists of.

The reference level selector 41 selects and outputs a reference level of a branch according to a mode selection control signal MODE_SEL indicating whether it is an 8 state or a 16 state. The adder 43 receives the received symbol RY_SYM and calculates and outputs an error with the reference level. The branch selector 45 selectively outputs a value or 0 output from the adder 43 according to the mode selection control signal MODE_SEL. The absolute value calculator 47 takes an absolute value of the value output from the branch selector 45 and outputs a branch metric BMi.

5 is an implementation circuit diagram of an 8-state / 16-state multi-mode branch metric calculation apparatus to which FIG. 4 is applied. 5 is to calculate the branch metric corresponding to the branch index shown in Table 3 and Table 4, the reference level used below is the same as the absolute value for the reference value of the table, the sign is reversed.

The reference level selector 41 selectively selects the memory levels m1 to m14 storing a plurality of reference levels according to modes and the reference levels stored in the memories m1 to m14 according to the mode selection control signal MODE_SEL. And multiplexers 41-1 to 41-7 to output the data. The reference levels stored in the memories m1 to m14 are reference levels (3, 5, 1, -1,-) for obtaining second branch metrics BM2 to eighth branch metrics BM8 corresponding to eight state modes. 5, -3, -7 and reference levels 4,8,12, -2,2,6, for obtaining the second branch metric BM2 to the eighth branch metric BM8 corresponding to the 16 state mode. 10).

The mode selection control signal MODE_SEL is a control signal indicating whether the signal input to the decoder is 8 states or 16 stages.

The multiplexers 41-1 to 41-7 select and output a 16 state reference level when the mode selection control signal MODE_SEL is '0', and an 8 state reference level when the mode selection control signal MODE_SEL is '1'. Select to print. That is, 8 state or 16 state reference levels are selectively output in accordance with the mode selection control signal.

The adder 43 is composed of memories m15 to m22 storing reference levels, and a plurality of adders 43-1 to 43-15 for adding received symbols and reference levels. A reference level 7 for obtaining an 8 state first branch metric is stored in the memory m15, and a reference level for obtaining the 16 state 8th branch metric to a 15th branch metric in the memories m16 to m22 is provided. 14, -4, -6, -8, -10, -12, -14).

In the plurality of adders, the first adder 43-1 adds the received symbol and the first branch reference level '7' of the eight states and outputs the second and eighth adders 43-2 through 43-8. Is added to the received symbol and the reference level output from the reference level selectors 41-1 to 41-7, and outputted. The ninth to fifteenth adders 43-9 to 43-15 are received symbols and 16; The ninth to fifteenth branch reference levels '14, -4, -6, -8, -10, -12, -14 'of the states are added and output.

The branch selector 45 is composed of a multiplexer 45-1 for selectively outputting an 8 state or 16 state branch according to the mode selection control signal MODE_SEL. The eighth multiplexer 45-1 selects and outputs the output of the first adder 43-1 in the case of 8 states according to the mode selection control signal MODE_SEL, and in the case of 16 states, selects a received symbol. The first branch is output to the absolute value adding unit 47.

The ninth multiplex to fifteenth multiplexers 45-2 to 45-8 select and output '0' in the case of 8 states according to the mode selection signal MODE_SEL, and in the case of 16 states, the ninth to 15th multiplexers 45-2 to 45-8. The outputs of the fifteenth adders 43-9 to 43-15 are input to output the ninth to fifteenth branches of the sixteen state mode to the absolute value adder 47.

The absolute value calculation unit 47 receives the outputs of the multiplexers 45-1 to 45-8 and the outputs of the adders 43-2 to 43-8, respectively, and calculates the absolute values. The metrics BM1 to BM8 are output in parallel, while in the 16 state mode, 15 branch metrics BM1 to BM15 are output in parallel.

As a result, in the branch metric calculation device, in the eight state mode, the first through eighth branch metrics BM1 = ∥receive symbol +7 ∥, BM2 through the first through eighth absolute calculators 47-1 through 47-8. = ∥ receiving symbol +3 ， receiving symbol +3 ， receiving symbol +5 ， BM4 = ， receiving symbol +1 ， BM5 = ， receiving symbol -1 ， BM6 = ， receiving symbol -5 ， BM7 = ， receiving symbol- 3, BM8 =, receiving symbol -7) is output.

In the case of the 16 state mode, the first through fifteenth branch metrics (BM1 = || receive symbol ∥, BM2 = ∥receive symbol +4 ∥) through the first through fifteenth absolute value calculators 47-1 through 47-15. BM3 = ∥ receive symbol +8 ， BM4 = ， receive symbol +12 ， BM5 = ， receive symbol -2 ， BM6 = ， receive symbol +2 ， BM7 = ， receive symbol +6 ， BM8 = ， receive symbol + 10∥, BM9 = ， Receive symbol + 14 ， BM10 = ， Receive symbol −4 ， BM11 = ， Receive symbol −6 ， BM12 = ， Receive symbol −8 ， BM13 = ， Receive symbol −10 ∥, BM14 = ∥ receiving symbol -12, BM15 = ∥ receiving symbol -14) is output.

If the branch metric calculation unit provides all the branch metrics for any received symbol in parallel through the above operation, the addition comparison selector selects and uses the corresponding branch metric because the unique branch metric of each state is determined. It can be.

In this embodiment, the present invention and the conventional branch metric are compared in terms of hardware. While the conventional device manufactures 8 state / 16 state modes separately according to the state mode, four branch metrics are generated for each state. In the case of 8 states, 32 adders and absolute calculators were used, and in 16 states, 64 adders and absolute calculators were required. However, while the present invention supports both 8-state and 16-state modes, only 15 multiplexers, adders, and absolute calculators are sufficient to calculate all branch metrics for a symbol simultaneously.

Although the invention has been described herein only in connection with specific embodiments, those skilled in the art will be able to make various modifications without departing from the spirit and scope of the invention as defined in the following claims.

As described above, the branch metric calculation apparatus of the present invention uses a control signal for distinguishing the 8-state mode and the 16-state mode to select a reference level for the branch in each mode, and all the branch metrics for the received symbol. Simultaneously calculate and use only the necessary metrics in the addition comparison selector, there is an effect to obtain the minimum hardware and area efficiency by making two modes in one chip.

Claims (12)

An apparatus for calculating a branch metric for decoding using a Viterbi algorithm, comprising: reference level selecting means (41) for selecting and outputting a reference level of a branch of an M-level received symbol according to a mode selection control signal MODE_SEL; An adder 43 for calculating and outputting an error between an M-level received symbol and a reference level, and a branch selector for selectively outputting a value or 0 outputted from the adder 43 according to a mode selection control signal MODE_SEL. Branch metric calculation apparatus comprising an absolute value calculating means 47 for taking the absolute value of the value output from the branch selecting means 45 and outputting the M branch metrics BMi. . The branch metric calculation apparatus according to claim 1, wherein the mode selection control signal MODE_SEL is a control signal for distinguishing M-level received symbols determined according to the number of states. 2. The apparatus of claim 1, wherein the M-level received symbol (RY_SYM) is a trellis coded signal. 4. The apparatus of claim 3 wherein M is an integer of at least two. 2. The memory device of claim 1, wherein the reference level selector 41 stores memories m1 to m14 storing a plurality of reference levels according to modes, and the memories m1 to m14 according to the mode selection control signal MODE_SEL. And a plurality of multiplexers (41-1 to 41-7) for selectively outputting a reference level stored in the branch). 2. The memory of claim 1, wherein the adder 43 outputs from the memories m15 to m22 storing a plurality of reference levels according to modes, the received symbol RY_SYM and the reference level selecting means 41. A second plurality of calculations of an error between a reference level and a calculation of an error between the first plurality of adders 43-2 to 43-8 and the reception symbol RY_SYM and the reference level provided from the memories m15 to m22. And branch adders (43-1, 43-9 to 43-15). 4. The M-level received symbol RY_SYM receives a trellis coded signal such that an 8-level signal (= 8 state) or a trellis coded signal uses an NTSC interference cancellation filter. The branch metric calculation device of claim 15, wherein the signal level is a 15 level (= 16 state) signal converted into a 15 level. 8. The method of claim 7, wherein the first branch metric in the branch metric calculation for the eight-level received symbol is (BM1 = || receive symbol +7 ∥), and the second branch metric is (BM2 = ∥ receive symbol +3 ∥). The third branch metric is (BM3 = ∥ receive symbol +5 ∥), the fourth branch metric is (BM4 = ∥ receive symbol +1 ∥), and the fifth branch metric is (BM5 = ∥ receive symbol −1 ∥) The 6th branch metric is (BM6 = ∥ receive symbol -5 ∥), the 7th branch metric is (BM7 = ∥ receive symbol -3 ∥), and the 8th branch metric is (BM8 = ∥ receive symbol -7 ∥) Branch metric calculation device, characterized in that. 8. The method of claim 7, wherein the first branch metric in the branch metric calculation for the 15th level (= 16 state) received symbol is (BM1 = || receive symbol ∥), and the second branch metric is (BM2 = ∥ receive symbol +4. ), The third branch metric is (BM3 = ∥ receive symbol +8) The fourth branch metric is (BM4 = ∥ receive symbol + 12), and the fifth branch metric is (BM5 = ∥ receive symbol-2 ∥ ), The sixth branch metric is (BM6 = ∥ receive symbol +2 ∥), the seventh branch metric is (BM7 = ∥ receive symbol +6 ∥), and the eighth branch metric is (BM8 = 수 received symbol +10 ∥). ), The ninth branch metric is (BM9 = ∥ receive symbol +14 ∥), the tenth branch metric is (BM10 = ∥ receive symbol -4 ∥), and the eleventh branch metric is (BM11 = ∥ receive symbol -6). ), The twelfth branch metric is (BM12 = ∥ receive symbol -8 ∥), the thirteenth branch metric is (BM13 = 신 received symbol −10 ∥), and the 14th branch Trick (BM14 = ∥ ∥ received symbol -12), and the 15 branch metrics (BM15 = ∥ ∥ received symbol -14) branch metric calculator, characterized in that. The branch metric calculation apparatus according to claim 1, wherein the branch metric for each mode is selectively calculated by using the mode selection control signal MODE_SEL to perform Viterbi decoding. The apparatus of claim 1, wherein the branch metric according to each mode is selectively calculated and trellis decoded using the mode selection control signal MODE_SEL. The branch metric calculation apparatus of claim 1, further comprising a decoder that receives the mode selection control signal MODE_SEL and supports two or more modes.