GB2330994A

GB2330994A - Traceback processor for use in trellis decoder

Info

Publication number: GB2330994A
Application number: GB9816512A
Authority: GB
Inventors: Heon Jekal
Original assignee: Daewoo Electronics Co Ltd
Current assignee: WiniaDaewoo Co Ltd
Priority date: 1997-10-31
Filing date: 1998-07-29
Publication date: 1999-05-05
Also published as: KR19990035418A; GB9816512D0

Abstract

The invention concerns a trace-back processor in a survivor memory unit of a trellis decoder. The processor combines both a maximum likelihood response mode through a Gaussian channel and a partial response mode through a partial response channel. Prior art trace-back processors have two separate units to achieve this. The invention of this application performs both processes in the same series of memory units, 50-1 to 50-15, in order to minimise complexity. All the memory units, 50-1 to 50-15, are used for the partial response, whereas only some of the units, 50-1 to 50-10, are used for the maximum likelihood response. The number of memory units used is equal to the decoding depth.

Description

A TRACEBACK PROCESSOR FOR USE IN A TCM DECODER The present invention relates to a TCM decoder for decoding signals encoded by a trellis-coded modulation (TCM); and, more particularly, to a traceback processor for decoding trellis code data in both 8 state mode and 16 state mode.

Recently, there has been increasing interest in a certain type of combined modulation and coding scheme, called trelliscoded modulation (TCM), that can achieve a coding gain without any bandwidth expansion in a bandwidth-limited channel. The TCM involves the use of a finite-state encoder and a nonbinary modulator. Therefore, as compared with a conventional modulation, the TCM can achieve net coding gains of 3 to 6 Db over an uncoded case, in the presence of an additive white Gaussian noise(AWGN).

In a process implementing a concatenated coding by connecting two different coders, e.g., an inner and an outer coders, to enhance data reliability, a well known convolutional encoder or a TCM encoder is used as the inner coder and data encoded by the inner coder is decoded by a trellis decoder employing a Viterbi algorithm, while a Reed Solomon coder can be used as the outer coder. The outer coder corrects errors which have not been remedied at the inner coder to thereby minimize the rate of errors. This concatenated coding technique achieves more advanced implementation with a much less complex hardware than a coding technique having only one coding process.

At a receiving end, the TCM data is decoded using a trellis decoder. The trellis decoder is a maximum likelihood decoder that provides a forward error correction. Trellis decoding is used in decoding a sequence of encoded symbols, e.g., a bit stream. The bit stream can represent encoded information in telecommunication transmission through various media with each set of bits representing a symbol instant.

In the decoding process, the trellis decoder works back through a sequence of possible bit sequences at each symbol instant to determine which of the bit sequences could most likely have been transmitted. The possible transitions from a bit at one symbol instant or state to a bit at a next or subsequent symbol instant or state are limited. Each possible transition from one state to another can be shown graphically and defined as a branch. A sequence of interconnected branches defines a path. Each state can transit only to a limited number of next states upon receiving a next bit in the bit stream. Thus, certain paths survive during the decoding process and the other paths do not. By eliminating those transition paths that are not permissible, computational efficiency can be improved in determining those paths most likely to survive. The trellis decoder typically defines and calculates a branch metric associated with each branch and employs this branch metric to determine which paths will survive and which paths will not.

A branch metric is calculated at each symbol instant for each possible branch. Each path has an associated metric, an accumulated value, that is updated at each symbol instant.

For each possible transition, the accumulated value for a next state is obtained by selecting the smallest of the sums of the branch metrics for different possible transitions and the path metrics from the previous states.

While several paths may survive at transition from one symbol instant to a next symbol instant, there is only one path accumulated with a minimum value. A sequence of symbol instants is referred to as a trace-back. The number of symbol instants tracing back through the trellis that extends a path with the minimum accumulated value defines the length, or decoding depth D, of a trace-back. The individual state in the trellis associated with the minimum accumulated value in a trace-back is translated into most likely bits that could have been transmitted in that symbol instant. The bits are referred to as a decoded symbol.

Referring to Fig. 1, there is shown a schematic block diagram of a conventional trellis decoder including a branch metric calculation unit (BMU) 11, an add-compare-select unit (ACS) 12, a path metric network(PMN) 13, and a survivor memory unit(SMU) 14.

The branch metric calculation unit 11 receives a sequence of transmitted symbols and calculates branch metrics, i.e., distances between branches associated with each state and the transmitted symbol. The branch metrics are provided to the add-compare-select unit 12. The add-compare-select unit 12 chooses a path having a minimum path metric among the paths corresponding to each state. Specifically, the add-compareselect unit 12 adds the branch metrics provided from the branch metric calculation unit 11 to corresponding previous path metrics from the path metric network 13; and compares candidate path metrics, i.e., the sums of the branch metrics and the corresponding previous path metrics with one another to thereby choose a new path metric having a smallest value.

The selected path metric is provided to the path metric network 13 as a new path metric for each state and information for tracing back on the selected path is coupled to the survivor memory unit 14. The survivor memory unit 14 stores the information from the add-compare-select unit 12 as the length of a survivor path, i.e., a decoding depth in order to decode the transmitted symbols and outputs decoded data by tracing back to the survivor path based on a trace-back algorithm.

An exemplary trellis decoder having the above structure is a decoder used in a GA HDTV receiving system proposed by a Grand Alliance (GA). The GA HDTV transmission system encodes data in an 8-level vestigial sideband modulation (VSB) mode and transmits the coded data on a frame-by-frame basis. The decoder in GA HDTV has two different paths depending on whether a National Television System Committee (NTSC) interference rejection filter is used or not. If the NTSC interference rejection filter is not used, a maximum likelihood response trellis decoder that performs 8-state mode decoding for a real channel with the AWGN is only utilized in order to restore input symbols. On the other hand, in the event the NTSC interference rejection filter is used, the output signals of the filter are changed from 8 to 15 levels according to the transfer function of the filter and, therefore, a partial response trellis decoder which performs 16 state mode decoding should be utilized.

Referring to Fig. 2 representing a data frame structure used in the GA HDTV transmission system, a frame consists of two fields and each field is divided into 313 segments. Each segment includes a segment synchronization signal of 4 symbols and 828 (data + forward error correction symbol(FEC))'s and a first segment of each field is allotted to a field synchronization signal.

The trellis coding has a strong characteristic against the AWGN but a weak characteristic against a group error and, therefore, input symbols may be sequentially inputted to 12 trellis coding blocks which are connected in parallel so that the input symbols may be 12 symbol intra-segment interleaved.

Since TCM codes have been interleaved by a unit of 12 symbols at the trellis code interleaver of a GA HDTV receiving system, the trellis code deinterleaver must involve 12 number of trellis decoders D1 to D12 connected in parallel in order to deinterleave transmitted data. Accordingly, each of the trellis decoders deinterleaves to decode every 12th symbol sequentially inputted.

Referring to Fig. 3, there is shown a block diagram of the conventional survivor memory unit (SMU) 14, wherein the SMU 14 includes a data delay processor 70 and a traceback processor 74. The data delay processor 70 receives the determination vector DVi of the survivor path for each state from the add-compare-select (ACS) unit 12 to store same therein and, after a delay for predetermined clocks, provides the determination vectors DVi's with a same index among the saved determination vectors at a same time, wherein an index i is equal to an index of intra-segment interleaved data dj The traceback processor 74 carries out both an optical response traceback, i.e., a maximum likelihood response traceback, algorithm for the 8 state mode and a partial response traceback algorithm for the 16 state mode by using the determination vectors DVi's fed from the data delay processor 70 so as to obtain the maximum likelihood response decoded symbol and a partial response decoded symbol; and provides either the maximum likelihood response decoded symbol or the partial response decoded symbol based on a mode selection signal (MODE~SEL).

Referring to Fig. 4, there is illustrated a block diagram of the traceback processor 74 shown in Fig. 3, which contains a first and a second operation modules 41 and 42 and a mode multiplexor (MODE MUX) 43. The first operation module 41 has a plurality of processing elements 41-1 to 41-15 for calculating the partial response decoded symbol by tracing back a determination vector of the 16 state mode for the partial response channel as far as the decoding depth thereof.

The second operation module 42 has a multiplicity of processing elements 42-1 to 42-10 for calculating the maximum likelihood decoded symbol by tracing back a determination vector of the 8 state mode for the maximum likelihood response channel as far as the decoding depth thereof. The MODE MUX 43 provides either the partial response decoded symbol fed from the 1st operation module 41 or the maximum likelihood decoded symbol fed from the 2nd operation module 42 based on the MODE~ SEL signal. Each of 16 input multiplexors la to 14a and lb to 10b in the processing elements selects one determination vector (X1, X0) among 16 determination vectors based on the current state of the corresponding processing element and, therefore, each 16 input multiplexor requires two 16:1 multiplexors.

Since, however, either the first operation module or the second operation module is selected based on the MODE~SEL signal at the traceback processor, the functions of the first and the second operation modules are partially overlapped, thereby unnecessarily increasing the area occupied by a number of multiplexors.

An object of the present invention is to at least partially mitigate the problems of the prior art.

An embodiment of the present invention provides a traceback processor for decoding trellis code data with a minimum number of storage devices in both 8 state mode and 16 state mode in a smallest area with a complexity of only 16 state mode.

In accordance with the present invention, there is provided a traceback processor of a survivor memory unit (SMU) for use in a TCM decoder with both a maximum likelihood response decoding mode through a Gaussian channel and a partial response decoding mode through a partial response channel, wherein the SMU includes a data delay processor for storing determination vectors of survivor path metrics, thereby providing each set of the determination vectors in parallel, and a traceback processor for receiving a mode selection signal, the mode selection signal representing either the maximum likelihood response decoding mode or the partial response decoding mode, and obtaining decoded symbols based on said each set of the determination vectors by a traceback algorithm selected by the mode selection signal, the traceback processor comprising: M processing elements in series, M being the decoding depth for the partial response decoding mode, wherein each (i)th processing element traces back a current state for one decoding depth based on said each set of the determination vectors and the mode selection signal to provide a previous state to an (i+l)st processing element as a new current state, i being an integer ranging from 1 to M-l; an (N)th processing element, N being an integer smaller than M and being another decoding depth for the maximum likelihood response decoding mode, further outputs a maximum likelihood response decoded symbol of the maximum likelihood response decoding mode; and an (M)th processing element outputs a partial response decoded symbol of the partial response decoding mode; and a mode selector for selecting either the maximum likelihood response decoded symbol or the partial response decoded symbol based on the mode selection signal.

The above and other objects and features of the present invention will become apparent from the following description of preferred embodiments given in conjunction with the accompanying drawings, in which: Fig. 1 shows a block diagram of a conventional trellis decoder applied with a Viterbi algorithm; Fig. 2 presents a data frame in a transmission system of Grand Alliance High Definition Television (GA HDTV); Fig. 3 describes a block diagram of a conventional survivor memory unit (SMU) for use in 16/8 state mode; Fig. 4 illustrates a traceback processor shown in Fig.

3.

Fig. 5 provides a block diagram of a traceback process in accordance with the present invention; and Figs. 6A to 6D represent a detailed block diagram of each of the processing elements shown in Fig. 5.

A preferred embodiment of the present invention is illustrated for the design of a trellis decoder for decoding trellis code data encoded according to a transmission specification of the Grand Alliance High Definition Television (GA HDTV).

Referring to Fig. 5, there is illustrated a block diagram of the traceback processor in accordance with the present invention, which comprises an operation module 50 and a first mode selection module 52. The operation module 50 has a plurality of processing elements 50-1 to 50-15 in serial for calculating the decoded symbol by tracing back a determination vector of either the 16 state mode for the partial response channel or the 8 state mode for the maximum likelihood response channel based on a mode selection (MODE~SEL) signal as far as the decoding depth thereof. The mode selection module 52 provides either the partial response decoded symbol or the maximum likelihood decoded symbol based on the MODE SEL signal.

If the MODE SEL signal represents 16 state mode, the operation module 50 traces back the determination vectors of 16 state mode for the partial response channel as far as the decoding depth 15 thereof. Each of the 14 processing elements 50-1 to 50-14 receives a determination vector (X1 (12k) X0(12k)) fed in parallel from a data delay processor, e.g., the data delay processor 70 shown in Fig. 3, and calculates a previous state S(t-(k+l)) to be provided to the next processing element, wherein k is an integer between 0 and 13.

The last processing element 50-15 receives lower bits X0(12x14) from the data delay processor and calculates the partial response decoded symbol (X1(t-15), X0(t-15)) by the use of a previous state S(t-14) and the lower bits X1(12x14).

According to the traceback algorithm in the 16 state mode, the previous state (S'3, '2 S'1' 'o may be determined by a logical operation of the current state (S3, S2, 1' So) and the determination vector (X1, S'o) as follows: (S3,S2,S1,S0) = (S3#X1,S1#S0,S2,X0) Eq. 1.

If the MODE SEL signal represents 8 state mode, the operation module 50 traces back the determination vectors of 8 state mode for the maximum likelihood response channel as far as the decoding depth 10 thereof. Each of the 9 processing elements 50-1 to 50-9 receives a determination vector (X1(12k), X,(12k)) fed in parallel from the data delay processor and calculates a previous state S(t-(k+l)) to be provided to the next processing element, wherein k is an integer between 0 and 8. The 10th processing element 50-10 receives lower bits X0(12x9) from the data delay processor and calculates the maximum likelihood response decoded symbol (X1(t-10), X0(t-10)) by the use of a previous state S(t-9) and the lower bits X1 (12x9). According to the traceback algorithm in the 8 state mode, the previous state (S'2, S'1, S'0) may be determined by a logical operation of the current state S1, S0) and the determination vector (X1, X0) as follows: (S2,S1,S0) = (S2#X1,X0#S0,S1) Eq. 2.

Referring to Figs. 6A to 6D, there are illustrated detailed blocks of processing elements for tracing back the determination vector according to Eqs. 1 and 2. Fig. 6A shows each of a 1st to a 9th processing elements 50-1 to 50-9 of the operation module 50; Fig. 6B represents a 10th processing element 50-10 thereof; Fig. 6C presents each of an 11th to a 14th processing elements 50-11 to 50-14 thereof; and Fig. 6D illustrates a 15th processing element 50-15 thereof.

As shown in Fig. 6A, each of the 1st to the 9th processing elements includes a 4-bit memory 161, two 16 input multiplexors 162-1 and 162-2, a previous state calculator 163 and a 2nd mode selector 164, wherein the 4-bit memory is for storing the current state (S3, S2, S1, So) ; a 16 input multiplexor 162-1 is for selecting one of 16 higher determination vectors X0's fed from the data delay processor based on the current state (S3, S2' S"So) from the 4-bit memory 161; the other 16 input multiplexor 162-2 is for selecting one of 16 lower determination vectors X1's fed from the data delay processor based on the current state (S3, S2, Sl, S0) from the 4-bit memory 161; the previous state calculator 163 is for calculating a previous state (S'3r '2' S'1, S'0) according to the Eqs. 1 and 2 based on the current state (S3, S2' S1, S0) from the 4-bit memory 161 and the selected determination vector (X1, X0) selected at the two 16 input multiplexors 162-1 and 162-2; and the 2nd mode selector 164 is for selecting one of the two previous states for the 16 state mode and the 8 state mode fed from the previous state calculator 163 based on the MODE~SEL signal.

The previous state calculator 163 has 4 exclusive-OR gates XOR~1 to XOR~4, wherein a 1st exclusive-OR gate XOR~1 thereof receives a 3rd bit S3 of the current state and a lower bit X1 of the determination vector; a 2nd exclusive-OR gate XOR 2 thereof receives both a 1st bit S1 and a 0th bit So of the current state; a 3rd exclusive-OR gate XOR~3 receives a 2nd bit S2 of the current state and the lower bit X1 of the determination vector; and a 4th exclusive-OR gate XOR~4 receives the 0th bit So of the current state and a higher bit X0 of the determination vector. So the 1st to the 4th exclusive-OR gates XOR~1 to XOR~4 output 'S3#X1', 'S1#S0', 'S2#X1' and 'S0#X0', respectively.

In the meantime, the 2nd mode selector 164 has 4 multiplexors MUX1 to MUX4, wherein each of the 4 multiplexor contains two input terminals, i.e., 16 state and 8 state input terminals. The 16 state input terminal of each multiplexor receives a 16 state input signal, while the 8 state input terminal thereof receives an 8 state input signal. That is to say, a 1st multiplexor MUXl receives both an output 'S3#X1' of the 1st exclusive-OR gate for the 16 state input signal and '0' for the 8 state input signal. A 2nd multiplexor MUX2 receives both an output 'S1#S0' of the 2nd exclusive-OR gate for the 16 state input signal and another output 'S2eX1, of the 3rd exclusive-OR gate for the 8 state input signal. A 3rd multiplexor MUX3 receives both the 2nd bit 'S2' of the current state for the 16 state input signal and an output 'S0#X0' of the 4th exclusive-OR gate for the 8 state input signal. A 4th multiplexor MUX4 receives both the higher bit 'X0, of the determination vector for the 16 state input signal and the 1st bit of the current state for the 8 state input signal.

Accordingly, if the MODE SEL signal indicates the 16 state mode, each multiplexor of the 2nd mode selector 164 selects the 16 state input signal so that the 2nd mode selector 164 provides a previous state (S'3, S'2' S'1, S'0) = (S3#X1, S1#S0, S2, X0) for the 16 state mode according to the Eq. 1 and, if otherwise, each multiplexor thereof selects the 8 state input signal so that the 2nd mode selector 164 provides a previous state (S'2, 5,i' o) = (S2oX1, X0eS0, for the 8 state mode according to Eq. 2.

Since all states converge on a state by tracing back themselves as far as the decoding depth according to a traceback algorithm, it does not matter from which state the traceback is started. A starting state for the traceback, i.e., the 4-bit memory 161 of the 1st processing element 50-1 is preferable to be assigned as "0000".

As shown in Fig. 6B, the 10th processing element includes a 4-bit memory 261, two 16 input multiplexors 262-1 and 262-2, a previous state calculator 263 and a 2 bit memory 264, wherein the function and the operation of the 4-bit memory 261 and the two 16 input multiplexors 262-1 and 262-2 are similar to those of the 4-bit memory 161 and the two 16 input multiplexors 162-1 and 162-2 shown in Fig. 6A.

The 2-bit memory 264 is for storing the selected determination vector (X1, X0) to be provided to the 1st mode selector 52, wherein the selected determination vector (X1, X0) just corresponds to the maximum likelihood response decoded symbol (X1(t-10), X0(t-10)) with the decoding depth 10 for the 8 state mode.

The previous state calculator 263 is for calculating a previous state (S'3, S'z, S'1, S'0) = (S3eX1, S1#S0, SZ' X0) of the 16 state mode according to the Eq. 1 based on the current state (S3, S2, S"So) from the 4-bit memory 261 and the selected determination vector (X1, X0) selected at the two 16 input multiplexors 262-1 and 262-2. That is to say, the previous state calculator 263 has 2 exclusive-OR gates XOR~5 to XOR~6, wherein a 5th exclusive-OR gate XOR~5 thereof receives a 3rd bit S3 of the current state and a lower bit X1 of the determination vector; and a 6th exclusive-OR gate XOR~6 thereof receives both a 1st bit S1 and a 0th bit So of the current state so that the 5th and the 6th exclusive-OR gates XOR~5 and XOR~6 output 'S3#X1' and 'S1#S0', respectively.

Accordingly, a previous state s(t-10) = (S'3, S'2, S'1, Sto) = (S3oX1, S1#S0, S2, X0) for the 16 state mode according to Eq. 1 may be provided to the 11th processing element 50-11.

As shown in Fig. 6C, each of the 11th to the 14th processing elements includes a 4-bit memory 361, two 16 input multiplexors 362-1 and 362-2 and a previous state calculator 363, wherein the operations of the 4-bit memory 361, the two 16 input multiplexors 362-1 and 362-2 and the previous state calculator 363 are same as those of the 4-bit memory 261 and the two 16 input multiplexors 262-1 and 262-2 and the previous state calculator 263 shown in Fig. 6B. Accordingly, a previous state (S'3, S'2, S'1, S'0) = (S3#X1, S1#S0, S2, X0) for the 16 state mode according to Eq. 1 may be provided.

As shown in Fig. 6D, the 15th processing element 50-15 includes a 4-bit memory 461, a 16 input multiplexor 462 and a 2-bit memory, wherein the 4-bit memory 461 is for storing a current state (S3, S2' S1, S0) ; the the 16 input multiplexor 462 is for selecting one lower bit X1 of the 16-bit determination vector X1(168) fed from the data delay processor based on the current state from the 4-bit memory 461; and the 2-bit memory 463 is for storing the determination vector (X1, X0) , X1 being the selected lower bit X1 and X0 being the lowest bit So of the current state.

The 15th processing element 50-15 stores the previous state (S'3(t-14), S'2 (t-14), S'1 (t-14) , S'0(t-14)) fed from the 14th processing element 50-14 as a current state in the 4-bit memory 461; and selects the lower bit X1, which corresponds to the current state stored in the 4-bit memory 461, among 16-bit of determination vector X1 (168), wherein the selected one bit X1 and a lowest bit So of the current state just correspond to the last decoded symbol (X1(t-15), X,(t-15)) with the decoding depth 15 for the 16 state mode.

In the 16 state mode, 14 previous states are calculated based on Eq. 1 in the 1st to the 14th processing elements 50-1 to 50-14, respectively, and 15 determination vectors (X1, X0) are detected in the 1st to 15th processing elements 50-1 to 50-15. In the 8 state mode, 9 previous states are calculated based on Eq. 2 in the 1st to the 9th processing elements 50-1 to 50-9, respectively, and 10 determination vectors (X1, X0) are detected in the 1st to the 10th processing elements 50-1 to 50-10. Therefore the MODE SEL signal is only used in the 1st to the 9th processing elements 50-1 to 50-9.

As described above, the traceback processor in accordance with the present invention has a minimum number of storage and multiplexing devices in both 8 state mode and 16 state mode in a smallest area with a complexity of only 16 state mode by reducing a number of multiplexors.

While the present invention has been described with respect to certain preferred embodiments only, other modifications and variations may be made without departing from the scope of the present invention as set forth in the following claims.

Claims

Claims 1. A traceback processor of a survivor memory unit (SMU) for use in a trellis-coded modulation (TCM) decoder with both a maximum likelihood response decoding mode through a Gaussian channel and a partial response decoding mode through a partial response channel, wherein the SMU includes a data delay processor for storing determination vectors of survivor path metrics, thereby providing each set of the determination vectors in parallel, and a traceback processor for receiving a mode selection signal, the mode selection signal representing either the maximum likelihood response decoding mode or the partial response decoding mode, and obtaining decoded symbols based on said each set of the determination vectors by a traceback algorithm selected by the mode selection signal, the traceback processor comprising M processing elements in series, M representing a decoding depth for the partial response decoding mode, wherein an (i)th processing element traces back a current state for one decoding depth based on said each set of the determination vectors and the mode selection signal to generate a previous state and provides same to an (i+l)st processing element as a new current state, i being an integer ranging from 1 to M-l; an (N)th processing element, N being an integer smaller than M and being another decoding depth for the maximum likelihood response decoding mode, further outputs a maximum likelihood response decoded symbol of the maximum likelihood response decoding mode; and an (M)th processing element outputs a partial response decoded symbol of the partial response decoding mode; and a mode selector for selecting either the maximum likelihood response decoded symbol or the partial response decoded symbol based on the mode selection signal.
2. The processor as recited in claim 1, wherein each of the 1st to the (N-l)st processing elements includes: a memory for storing a previous state fed from a previous processing element as a current state (S3, S2' S1' S0) ; a multiplexor for selecting one determination vector (X1, X0) among said each set of the determination vectors based on the current state (S3, S2, S1, S0) ; a previous state calculator for calculating both a previous state for the partial response decoding mode (S'3, S'2, $S'1, S'0) = (S3#X1, S1#S0, S2, X0) and another previous state for the maximum likelihood response decoding mode S'1, S'0) = (S2#X1, X0#S0, S1) based on the current state (S3, S2, S1, S0) and the determination vector (X1, X0); and means for selecting either of the previous states of the partial response decoding mode and the maximum likelihood response decoding mode based on the mode selection signal, thereby providing the selected previous state to a next processing element.
3. The processor as recited in claim 2, wherein said previous state calculator has 4 exclusive-OR gates, said 4 exclusive-OR gates outputting S3oX1, S1#S0, S2oX1 and X0#S0, respectively.
4. The processor as recited in claim 3, wherein the current state of the 1st processing element is (0, 0, 0, 0).
5. The processor of any preceding claim, wherein the (N)th processing element includes: a memory for storing a previous state fed from a previous processing element as a current state (S3, S2, S1' So) a multiplexor for selecting one determination vector (X1, X0) among said each set of the determination vectors based on the current state (S3, S2, S1, S0) ; a previous state calculator for calculating both a previous state for the partial response decoding mode (S'3, S'2, S'1, S'0) = (S3#X1, S1#S0, S2, X0) based on the current state (S3, S2, Slr S0) and the determination vector (X1, X0) thereby providing the previous state to a next (N+1) st processing element; and a memory for storing the determination vector (X1, X0) selected at the multiplexor.
6. The processor as recited in claim 1, wherein each of the (N+l)st to the (M-l)st processing elements includes: a memory for storing a previous state fed from a previous processing element as a current state (S3, S2, S1, So) a multiplexor for selecting one determination vector (X1, X0) among said each set of the determination vectors based on the current state (S3, S2, S1' S0) ; and a previous state calculator for calculating both a previous state for the partial response decoding mode (S'3r S'2, S'1, S'0) = (S3#X1, S1#S0, S2, X0) based on the current state (S3, S2' S1, S0) ) and the determination vector (X1, X0), thereby providing the previous state to a next processing element.
7. The processor of any preceding claim, wherein the (M) th processing element includes: a memory for storing a previous state fed from a previous processing element as a current state (S3, S2, S1' S0) ; a multiplexor for selecting one determination vector X1 among said each set of the determination vectors based on the current state (S3, S2, S1, S0) ; and a memory for storing the 0th bit of the current state and the determination vector X1 selected at the multiplexor.
8. A processor constructed and arranged substantially as herein described with reference to or as shown in Figures 5 and 6 of the accompanying drawings.