KR19990035418A - A survival path reverse tracking device for trellis code data - Google Patents

Abstract

The present invention relates to a survival path traceback apparatus for trellis code data.

The apparatus of the present invention is characterized in that a traceback processor of a survival data memory unit (SMU) capable of supporting both 16-state mode and 8-state mode in decoding trellis code data, And a first mode selection unit 50 for selecting and outputting the partial response restoration symbol or the optimum response restoration symbol outputted by the operation unit 50 according to the mode selection signal MODE_SEL, (Not shown). Therefore, unlike the conventional backtracking processor in which the processing modules are separately designed for each mode in order to support the two modes, the present invention can reduce the chip area by integrating the processing modules into one processing module, There is an advantage in that it is not necessary to calculate.

Description

An apparatus for tracking back survivor path of trellis-coded data,

The present invention relates to a trellis decoder (TCM decoder) for decoding a signal transmitted by a trellis code modulation (TCM) technique. In particular, the present invention relates to a trellis decoder The present invention relates to a survivor path traceback apparatus of trellis code data storing a set of decision vectors and finding an optimal path by a backtracking algorithm and finally outputting a maximum likelihood decoded symbol.

Generally, trellis code modulation (TCM) technique is a channel coding technique for obtaining a high coding gain in a bandwidth-limited channel, Technology and modulation technology. The TCM can obtain a significant gain in power over conventional unmodulated modulation schemes without changing the bandwidth. The TCM structure is composed of an encoder with a finite state and a non-binary modulator do. On the receiver side, a received signal mixed with noise is decoded using a decoder that performs maximum likelihood decoding by soft-decision. It is known that such a TCM can obtain a power phase gain of 3 to 6 dB or more in a digital signal transmission environment having an additive white Gaussian noise (AWGN) as compared with an unencoded modulator method. The term " trellis " is used here because it can represent a TCM codeword by a state transition diagram similar to a trellis diagram that is a state diagram of a binary convolution. The difference between the TCM code and the convolutional code is that the TCM codeword is extended to a signal set of arbitrary size by non-binary modulation of the convolutional codeword.

Despite the complexity of reception data detection due to the gain of such encoding in the TCM, it is widely used at present, and its use range is greatly increased. One of such applications is a transmission system of High Definition television (hereinafter referred to as HDTV).

The Viterbi algorithm is used to decode the TCM signal. The Viterbi algorithm performs maximum likelihood decoding as mentioned above and uses a trellis diagram to reduce the amount of computation required. Algorithm. This algorithm allows only one survivor path to exist in one state by comparing similarities between the paths input to each state and the received signal. This process is repeated at each stage according to the time of the Trellis diagram. Therefore, the amount of computation required by the Viterbi algorithm depends on the number of states, which depends on the length of the transmitted code stream.

FIG. 1 is a block diagram of a trellis decoder to which a Viterbi algorithm is applied. The trellis decoder includes a branch metric calculation unit (BMU) 11, an add comparator select unit (ACS) ) 12, a path metric network (PMN) 13, and a survivor memory unit (SMU) 14.

The branch metric calculation unit BMU 11 receives the received symbols and calculates a distance between the received symbol and a path passing through each state and outputs the resultant branch metric BMt to the additive comparison selection unit 12, . The additive comparison selection unit ACS 12 selects a path having a minimum path metric among the paths input to each state S _j (t) every time t, and the branch metric calculation unit BMU 1) provided from the path metric network (PMN) 13 and adds the branch metric BM (t) provided from the path metric network (PMN) 13 to the previous path metric PM (t-1) Accumulates a plurality of branch metrics merged in the state), compares the accumulated plurality of path metrics in the current state, and selects a path metric having a smaller value among them. The selected path metric is provided to the path metric network (PMN) 13, and information for backtracking the selected path is provided to the survivor data memory unit (SMU). The survivor data memory unit (SMU) 14 maintains the survival path information by the length of the surviving path for reverse tracking for decoding, that is, the decoding depth, and tracks backward according to the traceback algorithm And finally outputs the recovered symbol.

An example of a trellis decoder having such a structure is a trellis decoder employed in the GA HDTV receiving system proposed by the Grand Alliance (GA), which is formed to establish a high definition television (HDTV) standard in the United States. . In GA HDTV, a trellis coded signal is modulated by 8 levels of residual sideband (VSB) and the receiving side has two decoding paths depending on whether NTSC interference cancellation filter is used or not. That is, in order to recover the received symbol, an optimal trellis decoder for Gaussian (AWGN) channel decoding the 8-state mode can be used if an NTSC interference cancellation filter is not used. The input level is converted from 8 levels to 15 levels (16 states). Therefore, a trellis decoder for a partial response channel that performs 16 state mode decoding suitable for the input level should be used.

Meanwhile, in the GA HDTV transmission system, data is trellis encoded in 8-level VSB mode and is transmitted in units of frames. Referring to FIG. 2, a frame structure of a GA HDTV system will be described. Field, and one field (Field) is made up of 313 segments. Each segment is composed of 4 segments of segment sync signal and 828 data + error correction symbols (Data + FEC), and the first segment of each field is assigned to a field sync signal (Field Sync) have.

Trellis coding is strongly resistant to white Gaussian noise (AWGN), but it is weak in cluster error. Therefore, twelve trellis coded blocks are arranged in parallel and input symbols are sequentially applied to an encoder to perform intra-segment interleaving interleaving. Also, in the trellis code deinterleaver of the GA HDTV receiving system, since the TCM codeword on the transmitting side is interleaved in units of 12 symbols, 12 trellis decoders must be implemented in parallel on the receiving side to perform deinterleaving. Therefore, each trellis decoder receives the 12th symbol of the input symbol stream and performs decoding while deinterleaving it.

However, if a Trellis decoder suitable for each state is separately provided and 12 identical Trellis decoders are used in order to decode signals having different levels, the cost and area for designing are increased, A trellis decoder capable of supporting 8-state mode and 16-state mode simultaneously is designed.

3 is a block diagram of a survival data memory device (SMU) for performing survival path storage and backward tracking, which is comprised of a data delay processing section 70 and a backtrace processor 74. The data delay processing unit 70 receives and stores the decision vector DVi of the survival path surviving in each state from the addition comparison selection unit ACS and stores the decision vector DVi having the same index i And simultaneously outputs the decision vectors DVi. Here, i represents 12 symbol units. The backtrace processor 74 performs an optimum response backtrace algorithm or a partial response backtracking algorithm using the decision vectors DVi provided from the data delay processing unit 70, and at the same time, according to the mode selection signal MODE_SEL And selectively outputs the optimal response recovery symbol or the partial response recovery symbol.

FIG. 4 is a block diagram of the backtrace processor of FIG. 3, which includes a first calculator 41, a second calculator 42, and a mode selector 43. The first calculation unit 41 is composed of a plurality of processing elements 41-1 to 41-15 for calculating a partial response recovery symbol by tracing a received symbol for a partial response channel back to a decoding depth, 42 consists of a number of processing elements 42-1 through 42-10 that backtrack the received symbols for the optimal channel to the decoding depth to compute the optimal response recovery symbol. The mode selector 43 selects the partial response recovery symbol or the optimal response recovery symbol according to the mode selection signal MODE_SEL and outputs a restored symbol according to the mode. Here, the mode selection signal MODE_SEL is a control signal indicating whether the partial response channel reception mode or the optimum channel reception mode.

The 16 input multiplexers 1a to 14a and 1b to 10b in the processing elements 41-1 to 41-15 and 42-1 to 42-10 are connected to the 16 decision vectors outputted from the data delay processing unit 70 to the ability to select one of the (X _1, X _0), in fact the 16-input multiplexer (1a ~ 14a, 1b ~ 10b ) are respectively 16: 1 multiplexer are implemented in two. Therefore, four 16: 1 multiplexers (2 in 16 states and 2 in 8) are required for each stage except for the fifteenth processing element 41-15 in the 16-state mode.

However, since only one of the states is output according to the mode selection signal MODE_SEL in the actual operation, if the back-tracking processor is divided into the partial response channel reception mode and the optimal channel reception mode as described above, There was a problem to be done.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a survival path reverse tracking device for a trellis code data capable of reducing a chip area of a survival data memory structure capable of supporting both 16- And the like.

According to an aspect of the present invention, there is provided an apparatus including a data delay processing unit for maintaining survival path information by a decoding depth and outputting a decision vector, and a backtrace processor for outputting a symbol (SMU) capable of supporting a partial response channel 16 state mode and an optimal channel 8 state mode at the same time, wherein the backpropagation processor is configured to generate a partial response channel for a partial response channel and a received symbol for an optimal channel, restore tracking station to the decoding depth symbol (X _1, X ₀₎ becomes the M processing module for calculating the in series configured computing section, and the mode according to the selection signal (MODE_SEL) restore the partial response symbol or restore the optimal response symbol And a first mode selection unit for selectively outputting the first mode selection signal.

1 is a block diagram of a general trellis decoder to which a Viterbi algorithm is applied,

2 is a data unit frame structure in a GA (Grand Alliance) HDTV (High Definition Television) transmission system,

3 is a configuration diagram of a survival data memory device capable of supporting both the conventional 16/8 state mode,

4 is a block diagram of the traceback processor of FIG. 3;

5 is a block diagram of a backtrace processor in accordance with the present invention;

6 is a detailed block diagram of the processing module of the operation unit of FIG.

DESCRIPTION OF THE REFERENCE NUMERALS

50: operation units 50-1 to 50-15:

52: first mode selector 161, 261, 361, 461: 4-bit memory

162-1, -2,262-1, -2,362-1, -2,462: 16 input multiplexers

163, 263, 363: previous state calculation unit XOR_1 to XOR_8: exclusive OR gate

164: second mode selection unit MUX1 to MUX4: two-input multiplexer

264,463: 2-bit memory

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the present specification, a Trellis decoder conforming to the GA HDTV transmission standard will be exemplified.

First, the survivor data memory unit (SMU) of the trellis decoder finds one optimal path by a traceback algorithm, and then outputs a maximum likelihood decoded symbol as an output. That is, in the survivor data memory unit SMU, the previous state is continuously obtained by using the decision vector and the current state provided from the ACS, and is advanced by the decoding depth, and then the last decoded symbol bit (X1X0). Here, the decoding depth is 15 in the 16-state mode and 10 in the 8-state mode.

FIG. 5 is a block diagram of a backtrace processor according to the present invention. The backtracking processor includes an operation unit 50 and a first mode selection unit 52. The arithmetic unit 50 calculates a recovered symbol by tracing a partial response received symbol (16 state mode) or an optimum response received symbol (8 state mode) back to a decoding depth according to a mode selection signal (MODE_SEL) (50-1 to 50-15). The first mode selector 52 selects a partial response recovery symbol or an optimal response recovery symbol according to the mode selection signal MODE_SEL and outputs a restored symbol according to the mode. Here, the mode selection signal MODE_SEL is a control signal indicating whether the partial response channel reception mode or the optimal channel reception mode.

First, in the 16-state mode, the arithmetic unit 50 tracks the received partial response channel back to the decoding depth 15, and each of the fifteen processing modules 50-1 to 50-15 transmits the data delay processing unit (K + 1)) from the parallel vector X ₁ (12k) and X ₀ (12k) output from the parallel processing circuit 70 the outputs of the processing module 15 (120-15) final decoded symbols _{X 1 (t-15) X} 0 (t-15) through. in this case, the equation to obtain the previous state of the backtracking algorithm in the 16-state mode for as shown in equation 1, the current state (S3, S2, S1, S0) from the previous state (S'3, S'2, S'1 to a logical combination of the input decision vector _{(X 1, S '0)} , S'0) is determined.

Previous state _{(S '3, S' 2} , S '1, S' 0) = (S 3 ⊕X 1, S 1 ⊕S 0, S 2, S '0)

Next, in the 8-state mode, the arithmetic unit 50 tracks back the symbols received from the optimum response channel to a decoding depth of 10. In each of the 10 processing modules 50-1 to 50-10, the data delay processing unit (K + 1)) from the decision vector (X ₁ (12k), X ₀ (12k)) output from the processor 70 And outputs the final decoded symbol X ₁ (t-10) X ₀ (t-10) through the tenth processing module 50-10. Here, the equation for obtaining the previous state in the backtracking algorithm in the 8- as shown in equation (2), the current state _{(S 2, S 1, S} 0) and a decision vector (X _1, X ₀₎ to a logical combination of the previous state _{(S '2, S' 1} , S '0) input Is determined.

The previous state (S ' ₂ , S' ₁ , S ' ₀ ) = (S ₂ ⊕X ₁ , X ₀ ⊕S ₀ , S ₁ )

Next, the structure of the processing module that satisfies Equations (1) and (2) will be described with reference to FIG.

FIG. 6A shows the first to ninth processing modules 50-1 to 50-9 of the arithmetic unit 50 shown in FIG. 5, FIG. 6B shows the tenth processing module 50-10 , FIG. 6C shows the eleventh to fourteenth processing modules 50-11 to 50-14, and FIG. 6D shows the fifteenth processing module 50-15.

Referring to FIG. 6A, the first to ninth processing modules 50-1 to 50-9 include a 4-bit memory 161 for storing current states S ₃ , S ₂ , S ₁ , S ₀ , A 16-input multiplexer 162-1 for receiving the current state of the 4-bit memory 161 as a control signal and selecting one of the 16 decision vectors X ₀ output from the data delay processing unit, A 16-input multiplexer 162-2 for receiving the current state of the 4-bit memory 161 as a control signal and selecting one of the 16 decision vectors X ₁ output from the data delay processing unit, The above equations (1) and (2) are calculated using the states (S ₃ , S ₂ , S ₁ , S ₀ ) and the decision vectors (X ₁ , X ₀ ) selected through the multiplexers Previous state _{(S '3, S' 2} , S '1, S' 0) input to the previous state calculating unit 163, and the mode selection signal (MODE_SEL) for outputting a control signal Receiving is comprised of a second mode selecting unit 164 for selecting and outputting one of the previous state of the 16-state mode and an 8-state mode in which the output from the previous-state calculating unit 163.

The first exclusive OR gate XOR_1 of the previous state calculator 163 performs a XOR operation on the current state S ₃ and the decision vector X ₁ and the second exclusive OR gate XOR_2 outputs the current states S ₁ and S ₀ The third exclusive OR gate XOR_3 performs the exclusive OR operation on the current state S ₂ and the decision vector X ₁ and the fourth exclusive OR gate XOR_ 4 performs the exclusive OR operation on the current state S ₀ and the decision vector X ₀ , .

Accordingly, the previous state S ' ₃ bits input to the first multiplexer MUX1 of the second mode selection unit 164 becomes 0 with the output of the first exclusive OR gate XOR_1, and the output of the second multiplexer MUX2 Previous state S to be input, _two-bit output of the second exclusive OR gate (XOR_2) and the third and the output of the exclusive-OR gate (XOR_3), the third previous state S to be input to the multiplexer (MUX3), ₁ bit is the current State S ₂ bits and the fourth exclusive OR gate XOR_ 4 and the previous state S ' ₀ bit input to the fourth multiplexer MUX 4 becomes the decision vector X ₀ and the current state S ₁ . That is, the previous state of the 16-state mode is input to the first input terminal of the first to fourth multiplexers MUX1 to MUX4 of the second mode selection unit 164, and the previous state of the 8-state mode is input to the second input terminal do. Thus, the second mode selecting unit 164 is a mode select signal (MODE_SEL) therefore 16 when the state mode multiplexer (MUX1 ~ MUX4), a first input select signal to the previous state (S _'3, S' _2, S of If the outputs' _1, S _'0), and 8-state mode, select the second input signal of the multiplexer (MUX1 ~ MUX4), and outputs the previous state _{(S' 2, S '1} , S' 0).

In this case, regardless of which state the backtracking is initially started by the backtracking algorithm, if the backtracking algorithm proceeds to the decoding depth, it converges into one state. Therefore, the start state is set to " 0 " in the 4-bit memory 161 of the first processing module 50-1.

6B, the tenth processing module 50-10 includes a 4-bit memory 261, 16 input multiplexers 262-1 and 262-2, a previous state calculator 263, and a multiplexer And a 2-bit memory 264 for storing the selected crystal vector X ₀ , X ₁ bits through a plurality of memory cells 262-1, 262-2. The same components as those of the processing module of FIG. 6A have the same function.

The 10th processing module 50-10 includes 8 decision vectors X ₁ 108 and X ₀ 108 output in parallel from the data delay processing unit 70 in FIG. Bit memory 261 in the 4-bit memory 261 is selected. At this time, the selected bits X ₁ and X _{0 correspond} to the last recovered symbols X ₁ (t-10) and X ₀ (t-10) of the 8-state mode, and the 2-bit memory 264 stores this value To the first mode selection unit (52). That is, in the 8-state mode, the previous state is traced back to the decoding depth 10 to obtain the recovered symbols X ₁ and X ₀ .

On the other hand, to perform the 16-state mode, the tenth processing module 50-10 obtains and outputs the previous states S ' ₃ , S' ₂ , S ' ₁ , S' ₀ according to Equation 1 . That is, the fifth exclusive OR gate XOR_5 of the previous state calculator 263 performs the XOR operation on the current state S ₃ and the decision vector X ₁ , and the sixth exclusive OR gate XOR_6 compares the current states S ₁ and S Quot; ₀ " Thus previous state S _'3 bits are the current values exclusive-or operation of a state S ₃ and determining vector X _1, S' ₂ bits are the value exclusive-or operation of the S ₁ and S _0, S _'1 bit Becomes the same value as the current state S ₂ bits, and the S ' ₀ bit becomes the same value as the decision vector X ₀ (= S' ₀ ).

6C, the eleventh to fourteenth processing modules 50-11 to 50-14 include a 4-bit memory 361, 16-input multiplexers 362-1 and 362-2, and a previous state calculator 363, and the same components as those of the processing module of FIG. 6A have the same role. The eleventh to fourteenth processing module (50-11 - 50-14) has the formula (1) according to the previous state _{(S '3, S' 2} , S '1, S' 0) to perform 16-state mode And outputs it.

6D, the fifteenth processing module 50-15 includes a 4-bit memory 461 and a current state of the 4-bit memory 461 as a control signal, A 16-input multiplexer 462 for selecting one of the four decision vectors X ₁ and a 2-bit memory 463 for storing the current state S ₀ and the decision vector X ₀ , X ₁ bits selected via the multiplexer 462, .

Wherein the processing module 15 (50-15) comprises a processing module 14 before the output from the (50-14) state _{(S '3 (t-14} ), S' 2 (t-14), S '1 (t- the state of the 4-bit memory 461 is of _{16-bit): 14), S '0} (t-14)) receives the four-bit memory (store 461), and 16 determine vector (X1 (168) provides a And selects a corresponding decision vector. At this time, the selected bit X ₁ and the last bit S ₀ (= X ₀ ) of the 4-bit memory 461 correspond to the immediately recovered symbols X ₁ (t-15) and X ₀ (t-15). That is, in the 16-state mode, the previous state is traced back to the decoding depth 15 to obtain the recovered symbols X ₁ and X ₀ .

As described above, in the 16-state mode, the 14 previous states must be calculated using Equation 1 using the first through fifteenth processing modules 50-1 through 50-15, X1, S'0 must be found 14 times. In the 8-state mode, only the first to tenth processing modules 50-1 to 50-10 are used to perform the state calculation and X1 and X0 extraction nine times, respectively. Therefore, it can be seen that the mode selection signal MODE_SEL for distinguishing the modes is used for the first to ninth processing modules 50-1 to 50-9 shown in FIG. 6A.

While the invention has been described in connection with specific embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims.

As described above, the apparatus of the present invention finds a path by a backtracking algorithm and finally outputs a maximum likelihood decoded symbol. The apparatus includes a processing module for a partial response channel reception mode and an optimal channel reception mode, By designing a single processing module without designing it separately, it is possible to reduce a 16: 1 multiplexer occupying a large area, and there is no need to calculate a previous state for each mode.

Claims (7)

A data delay processing unit 70 for maintaining the survival path information by a decoding depth and outputting a decision vector, and a backtrace processor 74 for outputting the finally restored symbol in accordance with the backtrace algorithm, A survival data memory device (SMU) capable of simultaneously supporting a state mode and an optimal channel 8 state mode, The backtrace processor 74 Partial response channel received symbol and each tracking station to the decoding depth with respect to the received symbols for optimum channel for the recovered symbols (X _1, X ₀₎ of M processing modules (50-1~50-15) for calculating is connected in series (50); And And a first mode selection unit (52) for selectively outputting the partial response recovery symbol or the optimum response recovery symbol according to a mode selection signal (MODE_SEL). Tracking device. 2. The apparatus of claim 1, wherein the M corresponds to a decoding depth of a received symbol for a predetermined partial response channel. 2. The apparatus of claim 1, wherein the first to the (N-1) th processing modules (50-1 to 50-9) among the M processing modules (50-1 to 50-15) A memory 161 for storing the current state (S ₃ , S ₂ , S ₁ , S ₀ ); Receiving the plurality of decision vectors (X _1, X ₀₎ output from the data delay processing part 70, a multiplexer (162-1,162-2) for selecting a determined vector corresponding to the current state of the memory 161; Using the current state of the memory 161 and the decision vectors output from the multiplexers 162-1 and 162-2, _{(S '3, S' 2} , S '1, S' 0) = (S 3 ⊕X 1, S 1 ⊕S 0, S 2, S '0) (S ' ₃ , S' ₂ , S ' ₁ , S' ₀ ) for the partial response channel using the rule, (S ' ₂ , S' ₁ , S ' ₀ ) = (S ₂ ⊕X ₁ , X ₀ ⊕S ₀ , S ₁ ) A previous state calculation unit 163 for calculating the previous state (S ' ₃ , S' ₂ , S ' ₁ , S' ₀ ) for the optimum response channel using the rule and outputting it to the memory of the next stage processing module; And A second mode selection unit 164 that receives the mode selection signal MODE_SEL as a control signal and selects and outputs one of the 16 state mode and the 8 state state output from the previous state calculation unit 163 And the survivor path traceback device of the trellis code data. 4. The apparatus according to claim 3, wherein N is a value corresponding to a decoding depth of a received symbol for a predetermined optimum response channel, and N is an integer smaller than M. 2. The apparatus of claim 1, wherein the N < th > processing module (50-10) of the M processing modules (50-1 through 50-15) A memory 261 for storing the current state (S ₃ , S ₂ , S ₁ , S ₀ ); Receiving the plurality of decision vectors (X _1, X ₀₎ output from the data delay processing part 70, a multiplexer (262-1,262-2) for selecting a determined vector corresponding to the current state of the memory 261; Using the current state of the memory 261 and the decision vectors output from the multiplexers 262-1 and 262-2, _{(S '3, S' 2} , S '1, S' 0) = (S 3 ⊕X 1, S 1 ⊕S 0, S 2, S '0) A previous state calculation unit 263 for calculating the previous state (S ' ₃ , S' ₂ , S ' ₁ , S' ₀ ) for the partial response channel using the rule and outputting it to the memory of the next stage processing module; And The multiplexer (262-1,262-2) for determining the selected vector X _1, trellis survivor path traceback unit of code data, characterized in that it comprises a memory 264 for storing the X ₀ through bit. The apparatus of claim 1, wherein the (N + 1) th to (M-1) th processing modules (50-11 to 50-14) of the M processing modules (50-1 to 50-15) A memory 361 for storing the current state (S ₃ , S ₂ , S ₁ , S ₀ ); Receiving the plurality of decision vectors (X _1, X ₀₎ output from the data delay processing part 70, a multiplexer (362-1,362-2) for selecting a determined vector corresponding to the current state of the memory 361; And Using the current state of the memory 261 and the decision vectors output from the multiplexers 262-1 and 262-2, (S ' ₂ , S' ₁ , S ' ₀ ) = (S ₂ ⊕X ₁ , X ₀ ⊕S ₀ , S ₁ ) (S ' ₃ , S' ₂ , S ' ₁ , S' ₀ ) for the partial response channel using the rule and outputs it to the memory of the next stage processing module Wherein the survivor path traceback device of the trellis code data is characterized by: 2. The apparatus of claim 1, wherein the M < th > processing module (50-15) of the M processing modules (50-1 through 50-15) A memory 461 for storing the current state (S ₃ , S ₂ , S ₁ , S ₀ ); A multiplexer 462 receiving a plurality of decision vectors X ₁ output from the data delay processing unit 70 and selecting a decision vector corresponding to a current state of the memory 461; And And a memory (463) for storing a current state S ₀ and a decision vector X ₁ bit selected through the multiplexer (462).