KR100258234B1 - Trellis code modulation - Google Patents

Abstract

PURPOSE: A device for storing an existence path of trellis code data is provided to remove an influence of a segment synchronizing signal and to minimize the area. CONSTITUTION: The twelve registers(51-1-51-12) are operated by being enabled and being synchronized at a clock in accordance with an enable signal(SENA). A multiplexer(52) selects an input(OUT_0) from the exterior or an output of the twelfth register(51-12) in accordance with a count control signal(C832) and transmits to the first register(51-1). The count control signal(C832) indicates the number of counting a unit segment length 832 symbol by starting a count when each segment is started. A segment synchronizing signal is inputted during four clocks being started each segment initially. A deciding vector of a segment from an adding comparing selecting unit is inputted during the remainder 828 clocks. The count control signal(C832) becomes the "high" state for the four clocks while a segment synchronizing signal of the fourth symbols is inputted to the twelfth symbol delay register for removing an influence of a segment synchronizing signal. The register enable signal(SENA) becomes the "high" state during a unit segment 832 symbol section including a segment synchronizing signal of fourth symbol, and enables the registers(51-1-51-12). The registers(51-1-51-12) are enabled in all sections of each segment 832 symbol.

Description

An apparatus for storing survivor path of trellis-coded data

The present invention relates to a trellis decoder (TCM decoder) for decoding a signal transmitted by a trellis code modulation (TCM) technique, and in particular, a survival data path provided from an additive comparison selection unit (ACS). A survival path storage device of trellis coded data storing a decision vector which is a set of?

In general, the trellis code modulation (TCM) technique is a channel encoding technique for obtaining a high coding gain in a bandwidth-limited channel. It is implemented by combining a technique with a modulation technique. TCM can achieve significant power gains over conventional uncoded modulation without changing bandwidth. The TCM structure consists of an encoder and a non-binary modulator with finite states. do. At the receiver side, the received signal mixed with noise is decoded using a decoder that performs maximum likelihood decoding by soft-decision. These TCMs are known to achieve power gains of 3-6 GHz or more in a digital signal transmission environment with white Gaussian Nosie (AWGN) compared to uncoded modulation. The term "trellis" is used here because the TCM codeword can be represented by a state transition diagram similar to the trellis diagram, which is a state diagram of binary convolutional code. The difference between the TCM code and the convolutional code is that the TCM codeword is non-binary modulated with the convolutional codeword and extended to a signal set having an arbitrary size. In spite of the complexity of the received data detection because of the gain of the encoding of the TCM, it is currently widely used, and its use range is greatly increased.

The Viterbi algorithm is used to decode the TCM signal, which performs the maximum likelihood decoding already mentioned and uses trellis diagrams to reduce the amount of computation required. Algorithm This algorithm ensures that only one survivor path exists in a state by comparing the similarity between the paths input to each state and the received signal. This process is repeated for each stage of the trellis diagram over time. Therefore, the amount of computation required by the Viterbi algorithm does not depend on the length of the transmitted code string but depends on the state number.

FIG. 1 is a block diagram of a trellis decoder to which the Viterbi algorithm is applied. The trellis decoder includes a branch metric calculation unit (BMU) 11 and an add comparator select unit (ACS). 12), a path metric network (PMN) 13, and a survivor memory unit 14 (SMU).

The branch metric calculation unit (BMU) 11 receives a received symbol, calculates a distance between a path passing through each state and the received symbol, and adds the branch metric (BMt) as a result to the addition comparison selecting unit (ACS) 12. To provide. The addition comparison selection unit (ACS) 12 selects a path having a minimum path metric among paths input to each state S _j (t) every time t, and the branch metric calculation unit BMU The number of branch metrics BM (t) provided from: 11 and the previous route metric PM (t-1) provided from the route metric network PMN: 13 are added together (i.e., the current route metric to the current route metric). Accumulating a plurality of branch metrics merged in the state), and comparing a plurality of accumulated path metrics in the current state, and selecting a path metric having a smaller value among them. The selected route metric is provided to the route metric network (PMN) 13, and information for backtracking the selected route is provided to the survival data memory unit SMU 14. The survival data memory unit (SMU) 14 maintains the survival path information as long as the length of the survival path back tracked for decoding, that is, the decoding depth, and back traces according to a traceback algorithm. Output the last recovered symbol.

An example of a trellis decoder having such a structure is a trellis decoder employed in a GA HDTV reception system proposed by the Grand Alliance (GA), which was formed to establish high definition televison (HDTV) standards in the United States. Can be. In GA HDTV, a trellis coded signal is transmitted by modulating an 8-level residual sideband (VSB), and the receiving side has two decoding paths depending on whether an NTSC interference cancellation filter is used. In other words, to recover the received symbol, if the NTSC interference cancellation filter is not used, an optimal trellis decoder for 8 state mode decoding with Gaussian (AWGN) channel can be used, and the signal passing through the NTSC interference cancellation filter is filtered. Since the input level is converted from 8 levels to 15 levels (16 states) due to the propagation function of, the trellis decoder for partial response channel with 16 state mode decoding suitable for this should be used.

Meanwhile, in the GA HDTV transmission system, data is trellis-coded in an eight-level VSB mode and transmitted in units of frames. Referring to FIG. 2, a frame structure of the GA HDTV system is described. It consists of a field, and one field consists of 313 segments. Each segment is composed of 4 symbol segment sync signal and 828 data + error correction symbols (Data + FEC), and the first segment of each field is assigned to field sync signal (Field Sync). have.

Since trellis coding is strong against white Gaussian noise (AWGN) but weak against cluster errors, 12 trellis code blocks are arranged in parallel and the interleaved input symbols are sequentially applied to the encoder through a switch. Symbol intrasegment interleaving processing is performed. In addition, in the trellis code deinterleaver of the GA HDTV reception system, since the TCM codeword on the transmitter side is interleaved in units of 12 symbols, the reception side should implement 12 trellis decoders in parallel to perform deinterleaving. Accordingly, each trellis decoder receives and deinterleaves every 12th symbol of the input symbol string and performs decoding.

However, if a separate trellis decoder suitable for each state is used separately and 12 identical trellis decoders are used as described above to decode signals having different levels, cost and area are increased in design. To this end, we designed a trellis decoder that can support both 8 and 16 state modes.

That is, FIG. 3 is a configuration diagram of a survival data memory device (SMU) that performs survival path storage and traceback, and includes a data delay processor 30 and a traceback processor 34. The data delay processor 30 receives and stores the decision vector DVi of the surviving paths surviving in each state from the addition comparison selecting unit ACS, and has the same index i among the stored decision vectors after a predetermined clock delay. Outputs the decision vectors DVi simultaneously. Here, i represents 12 symbol units. The backtracking processor 34 performs an optimal response backtracking algorithm or a partial response backtracking algorithm using the decision vectors DVi provided from the data delay processing unit 30, and at the same time, according to a mode selection signal MODE_SEL. An optimal response recovery symbol or a partial response recovery symbol is selectively output.

The data delay processing section 30 includes register groups 31-1 to 31-15 for holding the X1 bit in the decision vector DV = X1, X0 finally determined in each state from the addition selection comparison section ACS, and X0. It consists of register groups 32-1 to 32-14 holding bits. The X1 register group is connected in series with a first a register 31-1 that delays X1 by one clock and outputs the second a-15a registers 31-2 through 31-15 that delays X1 by 12 clocks. The register group X0 includes the first register 32-1 for delaying X0 by one clock and the second registers 32-2 to 32-14 for delaying and outputting X0 by 12 clocks. Data connected in series and simultaneously output from each register unit are provided to the traceback processor 34 and input to the next register.

The decision vectors output in parallel to the traceback processor 34 should be decision vectors for data output from the same code block among the 12 trellis code blocks during encoding. However, the intrasegment interleaver continues to switch for 12 trellis decoders during 4 clocks of the segment sync signal, but the trellis decoder is disabled, so 12 If the symbols are shifted by symbol, output data of the same encoder cannot be obtained. Therefore, in the 12 symbol delay register sections 31-2 to 31-15, 32-2 to 32-14, the segment synchronization is performed so that the data encoded by the same encoder (that is, data having the same index) is positioned every 12 clocks. The effect of segment sync should be eliminated.

FIG. 4 is a detailed circuit diagram of the 12 symbol delay register sections 31-2 to 31-15, 32-2 to 32-14 of FIG. 3, and includes 12 registers 40-1 to 40-12 and the registers. It consists of twelve multiplexers 42-1 to 42-12 for selecting input and output data. According to the enable signal SENA and the count control signal C832, the registers 40-1 to 40-12 store the contents of a register located every 12 clocks during the next one clock after all four symbols of the segment sync signal are input. The contents of the registers are rearranged to be the data (same index) of the same encoder. That is, the data order stored in the register is changed only for one clock after all of the segment sync signals are input. Otherwise, the data is right-shifted and stored in the order of input.

As described above, in order to remove the influence of the segment synchronization signal by rearranging the contents of the 12 symbol delay register, a multiplexer for selectively transferring input data of 12 registers has been connected to each register. However, since the use of 12 multiplexers has a problem in that the design area is large, it is necessary to configure a circuit which occupies a small area while performing the same operation.

Accordingly, an object of the present invention is to provide a survival path storage device of trellis code data which minimizes the area while removing the influence of the segment synchronization signal.

The apparatus of the present invention for achieving the above object, the M symbol intrasegment interleaving process through the M trellis encoder to trace back the trellis coded signal stream to the decoding depth using the decision vector and the current state In decoding, the M vector for storing the decision vector and storing the decision vector while the 12 symbol delay registers of the data delay processing unit for parallel outputting the decision vector encoded by the same encoder every 12 clocks to the backtracking processor are serially connected to each other. And a multiplexer that selects an external input or an output of the Mth register according to the count control signal C832 and transfers the selected register to the first register.

1 is a block diagram of a general trellis decoder to which the Viterbi algorithm is applied;

2 is a diagram of a data unit frame structure in a GA (Grand Alliance) High Definition Television (HDTV) transmission system;

3 is a configuration diagram of a survival data memory device (SMU) of a trellis decoder that performs survival path storage and backtracking;

4 is a detailed configuration diagram of a 12 symbol delay register unit of FIG. 3;

5 is a configuration diagram of a 12 symbol delay register unit of a survival path storage device of trellis code data according to the present invention.

＊ Explanation of symbols for main parts of drawing

30: data delay processor 34: backtracking processor

31-1: Register 1a 32-1: Register 1b

31-2 to 31-15: 2a to 15a register section 32-2 to 32-14: 2b to 14b register section

51-1 to 51-12: 16-bit D flip-flop (register) 52: 2-input multiplexer

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, a code stream output through a trellis code interleaver in a GA HDTV transmitter may be expressed as shown in Table 1 below.

Segment Group 1 Group 2 … Group 69 #One d1, d2, d3... d12 d1, d2, d3... d12 … d1, d2, d3... d12 #2 d5, d6, d7... d4 d5, d6, d7... d4 … d5, d6, d7... d4 # 3 d9, d10, d11... d8 d9, d10, d11... d8 … d9, d10, d11... d8

In Table 1, each group is divided into 12 symbol units because 12 symbol intra-segment interleaving is performed. The index of each data is the same as the index of the trellis code block. That is, d1 is data output from the first trellis code block E1 and d2 is data output from the second trellis code block E2. The output data stream of the trellis code block is repeated in three segment periods. For example, the first segment includes d2, d3, d4,..., Starting with the data d1 output from the first trellis code block E1. The second segment is output in order, and the second segment is data d5 to d6, d7, d8,... Output from the fifth trellis code block E5. The third segments are output in order, and the third segments are outputted from the ninth trellis code block E9. The data d9, d10, d12, d1,... The output is in order. This is because the interleaver switch operates even while four symbols of the segment sync signal are input. Therefore, the data stream shown in Table 1 should be input to the trellis decoder Di having the same index. That is, d1 is valid data for the first trellis decoder D1, d2 is valid data for the second trellis decoder D2, and d3 is data valid for the third trellis decoder D3.

On the other hand, the survival data memory unit (SMU) of the trellis decoder shown in FIG. 3 finds one optimal path by a traceback algorithm, and then outputs the maximum likelihood decoded symbol as an output. Export. That is, the survival data memory unit SMU continuously obtains the previous state by using the decision vector and the current state provided from the addition selection comparison unit ACS, proceeds the decoding depth, and then decodes the last decoded symbol bit. Will output (X1X0).

For this purpose, the survival data memory unit (SMU) must maintain the survival path information as much as the decoding depth, and the data delay processing unit (30 in FIG. 3) plays this role to store the decision vector (DVi) of each state's survival path. At the same time, the decision vectors DVi having the same index i among the stored decision vectors are output in parallel to the backtracking processor 34. At this time, the data input immediately after the segment synchronization signal is input at the decoder is changed into three segment periods as shown in Table 1 above. For example, after the first data d1 (output from the first encoder E1) of segment # 0 is transmitted from the last data d12 (output from the twelfth encoder E12), the first data of the next segment # 1 is d1 (the first data). D5 (the output of the fifth encoder E5), rather than the output of one encoder E1). That is, when shifted by 12 symbols in the input data order, output data of the same encoder cannot be obtained. Therefore, the 12-symbol delay register unit must adjust so that data encoded by the same encoder (that is, data having the same index) is located every 12 clocks.

Fig. 5 is a block diagram showing the configuration of a 12 symbol delay register section of a survival path storage device of trellis code data according to the present invention. The multiplexer 52 selects input / output data of one register. The registers 51-1 to 51-12 are enabled according to the enable signal SENA to operate in synchronization with the clock CLK, and the multiplexer 52 is externally connected in accordance with the count control signal C832. The input OUT_0 or the output of the twelfth register 51-12 is selected and transferred to the first register 51-1.

The count control signal C832 indicates the number of counting symbols of the unit segment length 832 by starting counting at the beginning of each segment, and a clock in which a segment sync signal is input during the first four clocks of each segment. For the remaining 828 clocks, it corresponds to a clock to which the decision vector DVi of the segment is input from the addition comparison selecting unit ACS. The count control signal C832 becomes a 'high' state for 4 clocks in which the 4-bit segment sync signal is input to the 12-symbol delay register to remove the influence of the segment sync signal, and the register enable signal SENA is The registers 51-1 to 51-12 are enabled in a 'high' state during the unit segment 832 symbol period including the four-symbol segment synchronization signal.

Accordingly, the registers 51-1 to 51-12 are enabled in all sections of each segment 832 symbol, and the count control signal C832 is 'low' during the 828 clock except for the segment synchronization signal. 51-1) receives the input (OUT_0) from the outside through the multiplexer 52, shifts and stores the decision vector stream of the segment in the order in which they are input, and during the interval of 4 clock segment synchronization signal input, Since the count control signal C832 is 'high', the output of the twelfth register 51-12 is input to the first register 51-1 through the multiplexer 52, and the contents of the register are shifted four times and stored. .

That is, during the segment sync signal period, the 1-signal delay register receives the sync signals SYNC1 to SYNC4 of each segment from the add comparison selector ACS, and transfers them to the backtracking processor (34 in FIG. 3). Transmits the data shifted from the register to which the last register 51-12 is connected to the front end through the multiplexer 52 to the first register 51-1 and to the backtracking processor 34 at the same time. At this time, since the data transferred to the backtracking processor is not valid data, the backtracking processor should not operate. In addition, the 12-signal delay register outputs a decision vector (DVi) having the same index (i) in parallel for each clock and receives a decision vector (DVi) of the segment for 828 clocks except for the segment synchronization signal section. Can be provided.

As described above, the apparatus of the present invention stores the output of the last register in the first register during the four clocks in which the segment sync signal is input, thereby shifting the register contents by 4 bits, thereby eliminating the influence of the segment sync signal with the minimum area. It can work.

Claims (2)

In the M symbol intrasegment interleaving process through M trellis encoders, the trellis coded signal stream is traced back to a decoding depth using a decision vector and a current state. The 12 symbol delay register of the data delay processor 30 which stores the decision vector and outputs the decision vector encoded by the same encoder in parallel to the backtracking processor 34 every 12 clocks M registers 51-1 to 51-12, which are connected in series with each other and store decision vectors; And And a multiplexer 52 which selects an input from the outside or an output of the M th register 51-12 according to the count control signal C832 and transfers it to the first register 51-1. Survival path storage of trellis code data. The survival path storage of trellis code data according to claim 1, wherein the count control signal C382 has a first level in a section in which a segment synchronization signal is input, and a second level in other sections. Device.