KR100744505B1 - Viterbi decoder - Google Patents

Abstract

The present invention relates to a Viterbi decoder in a receiving system capable of receiving a plurality of enhanced data encoded at different code rates. In particular, the present invention proposes an enhanced / main integrated Viterbi decoder or an enhanced dedicated Viterbi decoder, wherein the Viterbi decoder is composed of a positive decoder and a negative decoder in consideration of the polarity inversion of the enhanced symbol. It is done. In the positive decoder and the negative decoder, the decoding performance of the enhanced symbol processor and the trellis encoder of the transmitter can be performed at once without performing two steps.

E8-VSB, Viterbi, Enhanced

Description

Viterbi decoder

1 is a block diagram of a transmission system according to the present invention

2 is a configuration block diagram of a receiving system according to the present invention;

FIG. 3 is a detailed block diagram of the enhanced channel decoder and demultiplexer of FIG. 2. FIG.

4A is a detailed block diagram of the E8-VSB convolutional encoder of FIG. 1.

4B is a detailed block diagram of the enhanced symbol processor of FIG. 4A.

4C is a diagram illustrating a data flow when a symbol input to the enhanced symbol processor of FIG. 4B is a main symbol;

FIG. 4D is a diagram illustrating a data flow when a symbol input to the enhanced symbol processor of FIG. 4B is an enhanced symbol.

5A is a diagram illustrating an enhanced symbol processor and a trellis coder connected in the case of a main symbol;

5B is a diagram illustrating an enhanced symbol processor and a trellis coder connected in the case of an enhanced symbol;

5C is a diagram illustrating an example in which a post decoder and a pre code are canceled in a state in which an enhanced symbol processor and a trellis coder are concatenated in the case of an enhanced symbol;

6 is a state transition diagram of an enhanced symbol and a main symbol;

7A shows a state transition diagram of a 1/4 enhanced symbol when the repeated 1/4 enhanced symbol is the same.

FIG. 7B shows a state transition diagram of a 1/4 enhanced symbol when the repeated 1/4 enhanced symbols are different from each other. FIG.

8 is a diagram for explaining an example of polarity inversion of an enhanced symbol.

9 illustrates an example of a process of calculating a path metric for an enhanced symbol and a main symbol;

10A to 10E illustrate examples of control signals input to a Viterbi decoder.

11 is a block diagram of an enhanced / main integrated Viterbi decoder according to the first embodiment of the present invention.

12A to 12C show examples of an input string and an output string of a Viterbi decoder.

13 is a diagram for performing reordering of an enhanced symbol.

14 is a block diagram illustrating an enhanced dedicated Viterbi decoder according to a second embodiment of the present invention.

Explanation of symbols for main parts of the drawings

611,811 branch metric calculation unit

612,812: ACS part of the positive decoder

613,813: ACS section of negative decoder

614,814: polarity inversion estimator

615,815: path history of the positive decoder

616,816: path history section of the negative decoder

617,817: decision selector 618: post decoder

619: output mux 818: enhanced symbol reordering unit

The present invention relates to a receiving system capable of receiving a plurality of enhanced data encoded at different code rates, and more particularly, to a Viterbi decoder.

In the United States, the ATSC (Advanced Television Systems Committee) 8VSB (Vestigial Sideband) transmission method was adopted as a standard in 1995, and broadcasted since the second half of 1998.In Korea, the same ATSC 8VSB transmission method is used as the standard. Adopted and currently broadcasting.

The ATSC 8VSB transmission method was basically set up to target high-definition video. However, there is a demand for a transmission standard for a system capable of more stable reception with lower image quality, or a system capable of data communication that requires more stable reception than a video signal due to the nature of the contents. In addition, these additional transmission specifications are defined to the extent that they do not adversely affect the system receiving the existing ATSC 8VSB signal, and in the receiver of the new specification, the existing ATSC 8VSB signal and the enhanced 8-VSB signal of the new specification (hereinafter referred to as E8-VSB) to receive all.

Therefore, the E8-VSB system adds a new service while accepting the existing 8VSB system as it is, and the newly added service enables improved reception than the existing service. In addition, the existing service is also affected by the added service to show a more stable reception performance.

The overall structure of a transmitter and a receiver conforming to the E8-VSB standard has been proposed by the present applicant, and FIG. 1 shows a block diagram of the transmission system and FIG. 2 shows a block diagram of the reception system.

That is, the transmission system can transmit MPEG-4 video or various additional data (for example, program executable file, stock information, etc.) that are widely used recently through enhanced data, and can also use existing MPEG-2 video and Dolby sound data. You can also send.

Hereinafter, for convenience of description, an existing MPEG-2 image is defined as main data or normal data. In this case, the enhanced data is subjected to additional error correction encoding compared to the main data. The enhanced data and the 1/2 enhanced data of the enhanced data mean data in which encoding is further performed at 1/2 code rate and 1/4 code rate, respectively, compared to the main data. Therefore, this enhanced data has a much better reception performance than the main data due to noise and multipath interference occurring in the channel. In particular, the enhanced data encoded at 1/4 code rate is 1 / It has better performance than 1/2 enhanced data encoded at 2 code rates.

Referring to FIG. 1 schematically, the transmission system is as follows.

In FIG. 1, the main and enhanced multiplex packet processing unit 111 multiplexes 1/2 enhanced data and 1/4 enhanced data in packet units, and then multiplexes the multiplexed enhanced data and main data in segment units. The output is then output to the first encoder 112.

The first encoder 112 includes a randomizer 112-1, a Reed-Solomon encoder 112-2, and a byte interleaver 112-3 at output terminals of the main and enhanced multiplexed packet processor 111. It is connected sequentially. The first encoder 112 having the above configuration sequentially performs data randomization, Reed Solomon encoding, and data interleaving on the data packets output from the main and enhanced multiplex packet processing units 111, and then the convolutional encoder. Output to (Convolutional Coder) 113.

The convolutional encoder 113 converts the data in units of bytes interleaved and output from the first encoder 112 into symbols, and then performs convolution encoding on only the enhanced data symbols, and then converts the symbols into units of bytes. The data is converted to data and then output to the first decoder 114.

The first decoder 114 includes a byte deinterleaver 114-1, a Reed-Solomon parity remover 114-2, and a derandomizer 114-3 at an output terminal of the convolutional encoder 113. It is connected sequentially. The first decoder 114 having such a configuration sequentially performs data deinterleave, Reed Solomon parit removal, and derandomize operations on the data of the byte unit output from the convolutional encoder 113. Output to 8VSB transmitter 100.

The 8VSB transmitter 100 has the same structure as that of the conventional ATSC 8VSB transmission system, and includes an ATSC renderer 101 (can be omitted), an ATSC Reed Solomon encoder 102, an ATSC byte interleaver 103, and a trellis encoder ( 104), multiplexer 105, pilot inserter 106, VSB modulator 107, and RF converter 108.

That is, the Reed Solomon data in which the Reed Solomon parity is removed by the first decoder 114 adds a 20-byte parity code to the data while passing through the ATSC Reed Solomon encoder 102 and the ATSC byte interleaver 103. Encoding and data interleaving to reverse the order of the data are performed. The interleaved data is input to the trellis encoder 104. At this time, if the interleaved data is enhanced data, the null bit of the enhanced data is applied to the lower bit input terminal of the trellis encoder 104, and the information bit including information about the enhanced data is the trellis encoder. Is applied to the upper bit input of 104.

The trellis encoder 104 precodes data input with the upper bits, and outputs the data input with the lower bits to the multiplexer 105 by trellis encoding the data. The multiplexer 105 multiplexes the trellis coded symbol sequence, the field synchronizing signal, the segment synchronizing signal, and the map information, and the pilot inserter 106 inserts the pilot signal therein and outputs it to the VSB modulator 107. do. The VSB modulator 107 modulates the pilot signal-inserted signal into an 8 VSB signal of an intermediate frequency band and outputs the RF signal to the RF converter 108. The RF converter 108 converts the VSB modulated signal into an RF band signal and transmits the same through an antenna. In this case, the map information is inserted in the field synchronization interval, and includes main / enhanced data multiplexing information related to the multiplexing rule and the number of transport packets of the enhanced data.

Referring to FIG. 2, a reception system for receiving a signal transmitted by E8-VSB modulation in a transmission system is described as follows.

That is, when the E8-VSB modulated RF signal is received through the antenna, the tuner 201 selects only the RF signal of the desired channel by tuning, converts it into an IF signal, and outputs the IF signal to the IF mixer 202. The IF mixer 202 down-converts the IF signal output from the tuner 201 to a baseband signal and outputs the demodulator 203. The demodulator 203 performs equalization after VSB demodulating the baseband signal. Output to unit 204 and map information recovery unit 205.

The map information recovery unit 205 restores the transmitted E8-VSB map information of the current field and outputs the same to the equalizer 204 and the E8-VSB channel decoder / demultiplexer 206. In addition, the map information recovery unit 205 generates information indicating the attribute of each symbol of the VSB signal according to the E8-VSB map information of the current field, and thus the equalizer 204 and the E8-VSB channel decoder / inverse. Output to the multiplexer 206. That is, the map information recovery unit 205 distinguishes whether it is a main symbol (that is, a general 8VSB symbol, also called a normal symbol) or an enhanced symbol, and encodes at a 1/2 code rate in the case of an enhanced symbol. E8-VSB symbol attribute information indicating whether a symbol is encoded or encoded at a 1/4 code rate is generated and output to the equalizer 204 and the E8-VSB channel decoder / demultiplexer 206. In this case, the E8-VSB symbol attribute information is operated by being connected to one equalized VSB symbol input to the Viterbi decoder of the E8-VSB channel decoder / demultiplexer 206.

The equalizer 204 compensates for the channel distortion included in the VSB demodulated signal by receiving the output of the E8-VSB channel decoder / demultiplexer 206 and the output of the map information recovery unit 205 of the subsequent stage. The signal is output to the E8-VSB channel decoder / demultiplexer 206. That is, the equalizer 204 performs improved equalization using the output of the map information recovery unit 205, and the E8-VSB channel decoder / demultiplexer 206 can perform channel decoding suitable for the currently received mode. have.

3 is a detailed block diagram of the E8-VSB channel decoder / demultiplexer 206. A separate data path exists to receive enhanced data in addition to main data. That is, the received signal is decoded or separated in the corresponding mode by using the E8-VSB map information and the E8-VSB symbol attribute information indicating the multiplexing information of the currently received E8-VSB signal. Both (MPEG TPS # 1), 1/2 Enhanced Stream (MPEG TPS # 2) and 1/4 Enhanced Stream (MPEG TPS # 3), which are enhanced VSB streams, can be received. In this case, the mode refers to any one of main data, 1/4 enhanced data, and 1/2 enhanced data which are existing ATSC 8VSB data.

Referring to FIG. 3, the main data decoder 300 that receives the equalized VSB symbol and decodes the main data (MPEG TPS # 1) and the enhanced data are separated and decoded, and then 1/2 enhanced data (MPEG) is further decoded. TPS # 2) and an enhanced data decoding unit 310 that is divided into 1/4 enhanced data (MPEG TPS # 3).

The main data decoder 300 includes a Viterbi decoder / data deinterleaver 301, an ATSC byte deinterleaver 302, an ATSC RS decoder 303, and an ATSC data derandomizer 304. .

That is, the main symbol equalized by the equalizer 204 is the Viterbi decoder / 12-way deinterleaver 301 of the main data decoder 300, the ATSC byte deinterleaver 302, like the existing 8VSB channel decoder. It is decoded into a main stream (MPEG TPS # 1) via an ATSC RS decoder 303 and an ATSC data derandomizer 304. That is, since the main symbol is notified by the E8-VSB data attribute generator as the main symbol, it can be received along the path of the conventional channel decoding scheme as described above.

However, in the case of the E8-VSB signal, since the main data and the enhanced data are multiplexed, this causes two changes in the channel decoder. One is that the Viterbi decoder needs to perform decoding for each attribute based on the attributes of the VSB symbol, and the other is that there must be a separate data path for the enhanced VSB (EVSB) stream.

The enhanced data decoder 310 is a data path for receiving and decoding the EVSB stream. The enhanced data decoder 310 includes an ATSC RS parity remover 311, an ATSC data derandomizer 312, a null bit remover 313, Enhanced data deinterleaver 314, enhanced RS decoder 315, enhanced packet demultiplexer 316, main and enhanced (M / E) mux packet processor 317, and two 164-to- 188 packet conversion section (318,319).

Referring to the E8-VSB channel decoder / demultiplexer 206 of FIG. 3 configured as described above, the E8-VSB symbol equalized by the equalizer 204 and the E8-VSB symbol attribute information generated by the map information recovery unit 205 are described. Is synchronized to the Viterbi decoder / 12-way deinterleaver 301.

In this case, since the equalized symbol input to the Viterbi decoder / 12-way deinterleaver 301 is mixed with the main symbol and the enhanced symbol, the Viterbi decoder is enhanced with the main symbol by E8-VSB symbol attribute information. The symbols are separated and Viterbi decoding is performed accordingly. In addition, 12-way deinterleaving is performed along with the Viterbi decoding to output a byte unit result to the ATSC data deinterleaver 302. The value determined during the decoding process in the Viterbi decoder is fed back to the equalizer 204. The ATSC byte deinterleaver 302 deinterleaves the data in byte units output from the Viterbi decoder / 12-way deinterleaver 301.

That is, the ATSC byte deinterleaver 302 performs deinterleaving on the output of the Viterbi decoder / 12-way deinterleaver 301 in the reverse process of the ATSC byte interleaver of FIG. . The packet data output from the ATSC byte deinterleaver 302 is input to the ATSC RS parity remover 311 of the ATSC RS decoder 303 and the enhanced data decoder 310.

The ATSC RS decoder 303 performs RS decoding on the output of the ATSC byte deinterleaver 302 and outputs it to the ATSC data derandomizer 304. When the ATSC RS decoded data is derandomized by the ATSC data derandomizer 304, the main signal, that is, MPEG TPS # 1, is finally output. In other words, the enhanced streams are ignored by the MPEG decoder because they are seen as meaningless null packets when observed in the existing MPEG TP streams. Therefore, only the MPEG TP streams of the main VSB are received without error.

The ATSC RS parity remover 311 of the enhanced data decoder 310 removes the ATSC RS parity portion from the packet data output from the ATSC byte deinterleaver 302 and outputs the ATSC RS parity part to the ATSC data derandomizer 312. do.

The ATSC data derandomizer 312 performs a derandomizer on the data from which the ATSC RS parity portion is removed and outputs the derandomizer to the null bit removing unit 313.

The null bit removing unit 313 removes all the data in the byte unit output from the ATSC data derandomizer 312 in the case of the main data byte, and removes the null bit in the case of the 1/2 enhanced data byte. Remove and print 2 bytes as one byte. In the case of a 1/4 enhanced data byte, 4 bytes are output as one byte by removing repeated bits and null bits. Here, E8-VSB bytes outputted from the main and enhanced (M / E) mux packet processing unit 317 are the main data bytes, 1/2 enhanced data bytes, and 1/4 enhanced data bytes for each byte. Classify by attribute information.

The enhanced data deinterleaver 314 performs deinterleaving on data in EVSB byte units composed of all meaningful bits output from the null bit removing unit 313, and then outputs the data to the enhanced RS decoder 315. do. The enhanced RS decoder 315 decodes the deinterleaved data and outputs the decoded data to the enhanced packet demultiplexer 316.

The enhanced packet demultiplexer 316 enhances the enhanced RS decoded data by 1/2 of 164 bytes using the E8-VSB map information and the field synchronization signal output from the map information recovery unit 205. Separate into data packets and 1/4 enhanced data packets. The separated 1/2 enhanced data packet is output to the first packet converter 318, and the 1/4 enhanced data packet is output to the second packet converter 319.

The first packet converter 318 divides the 1/2 enhanced data packet inputted into the packet of 164 byte unit into the packet of 188 byte unit without changing the data (MPEG TPS # 2), and the second packet converter 319. ) Outputs a 1/4 enhanced data packet, which is input in a packet of 164 bytes, divided into packets of 188 bytes without changing data (MPEG TPS # 3).

An object of the present invention is to provide a Viterbi decoder for performing Viterbi decoding on an enhanced symbol and a main symbol in a receiving system.

Another object of the present invention is to provide an enhanced / main integrated Viterbi decoder capable of Viterbi decoding both an enhanced symbol and a main symbol in a receiving system.

It is still another object of the present invention to provide an enhanced dedicated Viterbi decoder that performs Viterbi decoding only on enhanced symbols in a receiving system.

In order to achieve the above object, the Viterbi decoder according to the present invention has the following features.

. The decoding of the enhanced symbol processor and the trellis encoder of the transmitter is performed in a Viterbi decoder at once without performing two steps.

. Two positive and negative decoders are used to estimate the polarity inversion of the enhanced symbols, and the minimum path metrics of the two decoders are compared to determine whether the polarity is reversed.

. In the enhanced / main integrated Viterbi decoder, both the enhanced symbol and the main symbol having different state transitions can be decoded. For this purpose, the control signal related to the attribute of the input symbol is received from the E8-VSB data attribute generator.

. The 1/4 enhanced symbol is decoded by collecting two symbols.

. The enhanced / main integrated Viterbi decoder receives both the enhanced symbol and the survivor of the main symbol from the path history unit and outputs the final decoding result of the enhanced symbol and the main symbol.

. The enhanced dedicated Viterbi decoder receives only the enhanced symbol from the path history part and minimizes the adverse effect of the main symbol on the enhanced symbol. Therefore, the decoding performance of the enhanced symbol can be maximized.

. Since the sequence of symbols in the enhanced dedicated Viterbi decoder output is not the same as the sequence of input symbols, buffers are used for reordering.

. The branch metric calculation unit, the ACS unit, and the polarity inversion estimator can be shared among 12 Viterbi decoders.

. Each decoding field of the ACS section and the path history section outputs the determination value for the 8-level and feeds it back to the channel equalizer system.

The following is a hardware implementation of such a feature. A Viterbi decoder according to an embodiment of the present invention includes a first enhancement data encoded at a first code rate and a second enhancement coded at a second code rate in a transmission system. In the Viterbi decoder of the receiving system for performing the Viterbi decoding after receiving the demodulation and channel equalization by multiplexing the transmitted data and the main data,

A positive decoder that assumes that the polarity of the input symbol is not inverted and performs a Viterbi decoding from the corresponding branch metric value and outputs a decoding determination value;

A negative decoder that assumes that the polarity of the input symbol is inverted and performs a Viterbi decoding from the corresponding branch metric value and outputs a decoding determination value;

A polarity inversion estimator for estimating polarity inversion of an input symbol and outputting a result; And

And a decision selector which selects a decoding decision value output from the positive decoder or the negative decoder according to the result of the polarity inversion estimator and outputs the last upper and lower bits.

The positive and negative decoding units perform Viterbi decoding in units of two symbols when the input symbol is determined as a symbol encoded at a second code rate, and the second code rate is 1/4 code rate.

The positive and negative decoders perform Viterbi decoding considering only the same path for two symbols when it is determined that the input symbol is a symbol encoded at a second code rate and the repeated bits are identical after being randomized at the transmitting side. It is characterized by.

The positive and negative decoders perform Viterbi decoding by considering only different paths during two symbols when it is determined that the input symbol is a symbol encoded at a second code rate and repeated bits are different from each other after being transmitted at the transmitting side. It is characterized by.

The positive decoder is

 Assuming that the sign of the input symbol is not inverted, the corresponding branch metric value is calculated from the input symbol, and for each branch, for each branch, add the branch metric and the path metric of the previous state associated with that branch, and the smaller of them. An ACS unit that selects and stores a value and outputs it with the survivor and path selection information at this time;

It receives the survivor and path selection information of each state and maintains the path history for the decoding length, and selects the state having the smallest value among the minimum path metric values of each state, And a path history section for outputting the survivor before the time as a decoding decision value.

The negative decoder is

Assuming that the polarity of the input symbol is reversed, the corresponding branch metric value is calculated from the input symbol, and for each branch, add the branch metric and the path metric of the previous state associated with the branch, and the smaller of the two branches. After selecting and saving the ACS unit to output along with the survivor, path selection information at this time,

It receives the survivor and path selection information of each state and maintains the path history for the decoding length, and selects the state having the smallest value among the minimum path metric values of each state, And a path history section for outputting the survivor before the time as a decoding decision value.

The corresponding path of the decoder that is not selected as the path metric value of each state of the decoder selected by the polarity signal estimated by the polarity inversion estimator during the symbol period causing the polarity inversion of the enhanced symbol. And updating a metric value.

The path history unit of the positive and negative decoders may update the path history of the decoder that is not selected as the path history of the decoder selected by the polarity signal estimated by the polarity inversion estimation unit during the symbol period causing the polarity inversion of the enhanced symbol. It features.

If the input selector is an enhanced symbol, the decision selector outputs a value corresponding to an upper bit before the enhanced symbol processing on the transmitting side of the decoding determination value output from the path history unit of the decoder corresponding to the polarity signal as an upper bit. The lower bit is characterized by outputting a dummy bit.

The decision selector performs post-decoding on a value corresponding to the most significant bit after trellis coding on the transmitting side of the decoding decision value output from the path history section of the decoder corresponding to the polarity signal if the input symbol is the main symbol. And outputting the lower bit, as the lower bit, outputs the value corresponding to the lower bit before the enhanced symbol processing on the transmitting side as it is.

The polarity inversion estimator compares the smallest value of the path metric values of each state calculated by the positive decoder with the smallest value of the path metric values of each state calculated by the negative decoder. And outputting a polarity signal corresponding to the decoder having the same.

The ACS unit and the polarity inversion estimator in the positive and negative decoders can be shared among N Viterbi decoders in the receiving system.

The ACS unit of the positive and negative decoders further includes a feedback processing unit for feeding back the reference output level of the survival path selected in the state having the smallest value among the path metric values of each state for channel equalization, wherein the positive signal is positive according to the polarity signal. The feedback unit selects and feeds back a reference output level output from the ACS unit of the decoding unit or the negative decoding unit.

The path history unit of the positive and negative decoder further includes a feedback processing unit for feeding back a decoding determination value for channel equalization for each decoder, wherein the path history unit outputs the positive decoder or the negative decoder according to the polarity signal. And selecting and feeding back a decoding decision value.

Viterbi decoder according to another embodiment of the present invention includes a branch metric calculation unit for calculating each branch metric value between the input symbol and n preset reference output levels; Assuming that the polarity of the input symbol is not inverted, a corresponding branch metric value is input from the branch metric calculation unit, and for each branch, two branch branches are added together with the corresponding branch metric and the path metric of the previous state connected with the branch. An ACS unit of a positive decoder which selects and stores a small value among them and outputs it with a survivor and path selection information at this time; It receives the survivor of each state and the path selection information from the ACS of the positive decoder and maintains the path history for the length of the decoder, and also traces the state having the minimum path metric to trace the survivor before the decoder. A path history section of the positive decoder outputting the decoding decision value; Assuming that the polarity of the input symbol is inverted, a corresponding branch metric value is input from the branch metric calculation unit, and for each branch, two branch branches are added, and the corresponding branch metric and the path metric of the previous state connected with the branch are added. An ACS unit of a negative decoder for outputting together with the survivor and the path selection information at this time after selecting and storing a small value; It receives the survivor of each state and the path selection information from the ACS of the negative decoder and maintains the path history for the length of the decoder, and also traces the state having the minimum path metric to trace the survivor before the decoder. A path history section of the negative decoder outputting the decoding decision value; A polarity inversion estimator for estimating polarity inversion of an input symbol and outputting a result; A decision selector for selecting and outputting a decoding decision value output from a path history part of a positive decoder or a path history part of a negative decoder according to a result of the polarity inversion estimator; And an output unit configured to output an upper bit and a lower bit from a decoding determination value output from the decision selector according to whether an input symbol is an enhanced symbol or a main symbol, and thus an enhanced / main integrated Viterbi is configured. It is done.

Viterbi decoder according to another embodiment of the present invention includes a branch metric calculation unit for calculating each branch metric value between the input symbol and n preset reference output levels; Assuming that the polarity of the input symbol is not inverted, a corresponding branch metric value is input from the branch metric calculation unit, and for each branch, two branch branches are added together with the corresponding branch metric and the path metric of the previous state connected with the branch. An ACS unit of a positive decoder which selects and stores a small value among them and outputs it with a survivor and path selection information at this time; It receives the survivor of each state and the path selection information from the ACS of the positive decoder and maintains the path history for the length of the decoder, and also traces the state having the minimum path metric to trace the survivor before the decoder. A path history section of the positive decoder outputting the decoding decision value; Assuming that the polarity of the input symbol is inverted, a corresponding branch metric value is input from the branch metric calculation unit, and for each branch, two branch branches are added, and the corresponding branch metric and the path metric of the previous state connected with the branch are added. An ACS unit of a negative decoder for outputting together with the survivor and the path selection information at this time after selecting and storing a small value; It receives the survivor of each state and the path selection information from the ACS of the negative decoder and maintains the path history for the length of the decoder, and also traces the state having the minimum path metric to trace the survivor before the decoder. A path history section of the negative decoder outputting the decoding decision value; A polarity inversion estimator for estimating polarity inversion of an input symbol and outputting a result; A decision selector for selecting and outputting a decoding decision value output from a path history part of a positive decoder or a path history part of a negative decoder according to a result of the polarity inversion estimator; And a reordering unit for reordering and outputting values corresponding to the upper bits before the enhanced symbol processing on the transmitting side among the decoding decision values output from the decision selecting unit in the same order as the input symbol string using the buffer. It is characterized in that the decoder is configured.

Other objects, features and advantages of the present invention will become apparent from the following detailed description of embodiments taken in conjunction with the accompanying drawings.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention that can specifically realize the above object will be described. At this time, the configuration and operation of the present invention shown in the drawings and described by it will be described as at least one embodiment, by which the technical spirit of the present invention and its core configuration and operation is not limited.

The present invention relates to an implementation of a Viterbi decoder which performs decoding according to the property of an E8-VSB symbol among an enhanced channel decoder and a demultiplexer of a reception system.

In this case, the reception system of the present invention performs the decoding on the convolutional encoder 113 and the trellis encoder 104 of the transmission system in two steps without performing the decoding in two stages.

11 is a block diagram illustrating a Viterbi decoder according to the first embodiment of the present invention, which is an embodiment of an enhanced / main integrated Viterbi decoder.

11 shows a branch metric calculation unit 611, an addition-compare-selection (ACS) unit 612 of a positive decoder, an ACS unit 613 of a negative decoder, a polarity inversion estimator 614, and a positive decoder. A path history section 615, a path decoder section 616 of the negative decoder, a decision selector 617, a post decoder 618, and an output mux 619. FIG.

14 is a block diagram of a Viterbi decoder according to a second embodiment of the present invention, which is an embodiment of an enhanced dedicated Viterbi decoder.

14 shows a branch metric calculation unit 811, an addition-compare-selection (ACS) unit 812 of a positive decoder, an ACS unit 813 of a negative decoder, a polarity inversion estimation unit 814, and a positive decoder. Path history section 815, negative decoder path history section 816, decision selector 817, and enhanced symbol rearrangement section 818.

Before describing the above-described details and differences of the Viterbi decoders according to the first and second embodiments of the present invention, the convolutional encoder 113 of the transmission system of FIG. The trellis encoder 104 and the relationship between the two will be described.

1.Connecting Enhanced Symbol Processor with Trellis Encoder

FIG. 4A is a detailed block diagram of the convolutional encoder 113 and includes a 12-way symbol interleaver 401, an enhanced symbol processor 402, and a 12-way symbol deinterleaver 403.

In FIG. 4A, the 12-way symbol interleaver 401 converts data input in byte units into symbol units (consisting of two bits of X2 and X1), performs interleaving, and outputs the interleaved symbols to the enhanced symbol processor 402.

The enhanced symbol processor 402 bypasses the 12-way symbol deinterleaver 403 if the input data is a main symbol. On the other hand, if it is an enhanced symbol, symbol processing is performed on only the data X2 input as the upper bit and output to the 12-way symbol deinterleaver 403, and the data X1 input as the lower bit is discarded. The 12-way symbol deinterleaver 403 deinterleaves the data output from the enhanced symbol processor 402 again, converts the data into byte units, and outputs the data to the first decoder 114.

4B is a detailed block diagram of the enhanced symbol processing unit 402. The adder 411 adds the data X2 inputted to the higher bits and the data fed back from the register 414 to the mux 412.

The mux 412 selects the output of the adder 411 if the input symbol is the main symbol, and selects the data X2 input as the higher bit if it is an enhanced symbol and outputs the data to the registers 413 and 414 and the adder 415. .

The register 413 delays the output of the mux 412 by one symbol and outputs the result to the adder 415. The adder 415 adds the output of the mux 412 and the output of the register 413 to a higher bit. Output as (X2 '). Here, the register 413 is a kind of delay, and the same applies to other registers.

The register 414 feeds back the adder 411 by delaying the output of the mux 412 by one symbol.

The mux 416 selects an output of the register 417 if the input symbol is a main symbol, and selects an output of the register 420 if the input symbol is a main symbol, and outputs the output to the register 417.

The register 417 delays the output of the mux 416 by one symbol, outputs it to the adder 418, and simultaneously feeds back the mux 416.

The adder 418 adds the data X2 inputted to the upper bits and the output of the register 417 and outputs the result to the mux 419.

The mux 419 selects an output of the register 420 if the input symbol is a main symbol, and selects an output of the adder 418 and outputs the output to the register 420 if the input symbol is a main symbol.

The register 420 delays the output of the mux 419 by one symbol and outputs the result to the mux 421 and feeds back the muxes 417 and 419.

The mux 421 selects the data X1 input as the lower bit and outputs the lower bit X1 'if the input symbol is the main symbol, and selects the output of the register 420 if the symbol is an enhanced symbol. X1 ').

There are 12 enhanced symbol processors 402 configured as described above in the E8-VSB convolutional encoder 113. In the enhanced symbol processor 402, symbol processing varies according to whether an input symbol is a main symbol or an enhanced symbol. That is, the selection signal input to the muxes 412, 416, 419, 421 in FIG. 4B, that is, the M / E flag is a main symbol or a 1/2 code rate or a 1/4 code rate. Tells whether it is an enhanced symbol to be encoded.

4C is a diagram illustrating a data path in an enhanced symbol processor when an input symbol is a main symbol. That is, if the input symbol is the main symbol, the data X1 input as the lower bit is bypassed to X1 'as it is through the mux 421, and the data X2 input as the upper bit is added to the adder 411, the mux 412, Bypass through registers 413 and 414, and adder 415 to X2 '. That is, the adder 411 and the register 414 have a pre coder structure, the adder 415 and the register 413 have a post decoder structure, and the precoder and the post decoder are inverse processes. The result of both blocks is therefore canceled. Therefore, the data X2 input as the higher bit has the effect of bypassing to X2 'as it is.

4D is a diagram illustrating a data path in an enhanced symbol processor when an input symbol is an enhanced symbol.

That is, if the input symbol is an enhanced symbol, the data X2 input as the higher bit is post-decoded by the post decoder composed of the register 413 and the adder 415 and output to X2 '. In addition, the data X2 input as the higher bits is convolutionally coded in a convolutional encoder consisting of a register 417, an adder 418, and a register 420, and the parity bit generated therein is output as X1 '. At this time, the data X1 input as the lower bit is discarded.

FIG. 5 illustrates a state in which the enhanced symbol processor and the trellis coder are concatenated. In reality, although a plurality of blocks exist between the enhanced symbol processor and the trellis encoder in the transmission system, the enhanced channel decoder and the demultiplexer of the reception system assume that the two blocks are concatenated and perform decoding.

As shown in FIG. 5, the trellis encoder 104 has a structure in which a precoder 510 is connected to an upper bit and a convolutional encoder 520 is connected to a lower bit, and two input bits X2 and X1 are provided. The encoding is performed to output three output bits C2, C1, and C0.

That is, the data X2 input as the higher bit is precoded by the precoder 510 to become the output bit C2. The data X1 input as the lower bit is bypassed to the output bit C1 as it is, and is encoded by the convolutional encoder 520, and the parity bit generated here becomes the output bit C0. That is, the output bit C0 is determined by the value stored in the register M0.

5A illustrates a structure in which an enhanced symbol processor and a trellis coder are concatenated when a main symbol is input. As shown in FIG. 7C, if the input symbol is the main symbol, the two bits X2 and X1 inputted are bypassed to X2 'and X1' as they are and are input to the trellis encoder 104. That is, the upper bit X2 input to the enhanced symbol processor 402 is input to the precoder 510 of the trellis encoder 104 as it is. The lower bit X1 input to the enhanced symbol processor 402 is input to the convolutional encoder 520 of the trellis encoder 104 as it is.

5B illustrates a structure in which an enhanced symbol processor and a trellis coder are connected when an enhanced symbol is input. As shown in FIG. 7D, the data X1 inputted in the lower bits is discarded, and the data X2 inputted in the upper bits passes through the post decoder and is output as X2 'to the trellis encoder 104. In addition, the data X2 input as the higher bit is convolutionally coded in the convolutional encoder, and the parity bit generated here is output to the trellis encoder 104 as X1 '.

That is, the upper bit X2 ′ that is post-decoded and output from the enhanced symbol processor 402 is input to the precoder 510 of the trellis encoder 104, and is convoluted by the enhanced symbol processor 402. The lower bit (X1 '), which is subjected to the LOS encoding, is input to the convolutional encoder 520 of the trellis encoder 104.

In this case, since the post decoder of the enhanced symbol processor 402 and the precoder of the trellis encoder 104 applied to X2 of the enhanced symbol are inverse processes, the results of the two blocks are canceled, as shown in FIG. 5C. X2 is bypassed as it is to C2.

Accordingly, the Viterbi decoder of the reception system of the present invention may decode the Viterbi decoding algorithm using the general symbols of FIGS. 5A and 5C in the case of the main symbol and the enhanced symbol, respectively.

2. State transition and decoding of enhanced and main symbols

6 shows a state transition diagram of an enhanced symbol and a main symbol.

That is, in the case of the enhanced symbol, registers M3, M2, M1, and M0 of the encoder are defined as states in FIG. 5C, and thus, all 16 states exist. In the case of the main symbol, M3 and M2 maintain the value changed from the previous enhanced symbol as it is, and as shown in FIG. 6, the state transition pattern is repeated four times. That is, in the case of the main symbol, the input data X2 and X1 are bypassed to the trellis encoder 104 in the enhanced symbol processor 402 as shown in FIG. 5A.

As shown in FIG. 6, it can be seen that the state is shifted by the input bit X2 in the case of the enhanced symbol, whereas the state is shifted by the input bit X1 in the case of the main symbol. This is because in the case of enhanced symbols, input bit X1 is discarded as shown in FIG. 5C, and input bit X2 passes through four registers M3, M2, M1, and M0. In the case of the main symbol, the input bit X1 passes through the registers M1 and M0 as shown in FIG. 5A.

In this case, the enhanced symbol is further divided into a 1/2 enhanced symbol and a 1/4 enhanced symbol.

However, when the input symbol is an enhanced symbol, the enhanced symbol processor of FIG. 4B processes the same regardless of whether it is a 1/2 enhanced symbol or a 1/4 enhanced symbol.

The difference between the 1/4 enhanced symbol and the 1/2 enhanced symbol is that the input bits are repeated twice for a 1/4 enhanced symbol in a null bit expander in the transmission system. However, the repeated 1/4 enhanced symbols may be randomly changed by the data randomizer and may be the same or different from each other. And since the receiving system knows the behavior of the randomizer, it can know whether they are the same or different.

FIG. 7A illustrates a state transition when the repeated 1/4 enhanced symbols are the same, and FIG. 7B illustrates the state transition when the repeated 1/4 enhanced symbols are different. In the case of a 1/4 enhanced symbol, Viterbi decoding should be performed in units of two symbols in order to obtain additional coding gain in the Viterbi decoder.

If the repeated 1/4 enhanced symbols in FIG. 7A pass through the randomizer and are the same, Viterbi decoding is performed considering only the same paths for two symbols. For example, in the case of the state 0000, only the paths X2 is 1 and the paths 0 are both considered during the two symbols, and different paths are excluded from the decoding process. This can increase the reliability of decoding.

In contrast, as shown in FIG. 7B, when the 1/2 enhanced symbol repeated in the null bit expander passes through the randomizer and is different from each other, Viterbi decoding is performed considering only different paths during the two symbols. For example, in the case of state 0000, only paths in which X2 is 0-> 1 or 1-> 0 during two symbols are considered and the same paths are excluded from the decoding process.

3. Invert Enhanced Symbol

In the transmission system to which the enhanced mode is added, the output of the E8-VSB convolutional encoder 113 is not directly input to the trellis encoder 104 as shown in FIG. 1 in order to maintain compatibility with the existing ATSC 8VSB receiver. Input to the trellis encoder 104 through the process of. The series of processes here includes an ATSC data byte deinterleaver 114-1, an RS parity byte remover 114-2, an ATSC RS encoder 102, and an ATSC data byte interleaver 103.

In the enhanced symbol processor 402, the main symbol is bypassed, and further encoding is performed only on the enhanced symbol, because the parity byte calculated by the ATSC RS encoder 112-2 does not correspond to the changed data packet. In the conventional ATSC 8VSB receiver, if RS decoding is performed, an enhanced data packet is treated as an error. Therefore, in order to maintain compatibility with the existing ATSC 8VSB receiver, the ATSC RS encoder 102 performs ATSC RS encoding again with the output of the E8-VSB convolutional encoder 113 to recalculate the parity bytes. It goes through a series of processes.

However, when the recalculated parity byte is converted into a symbol and input to the trellis encoder 104 and encoded by the precoder, the enhanced symbol may not be bypassed as it is, but the polarity may be reversed.

8 illustrates an example of polarity inversion of an enhanced symbol. In FIG. 8, compatibility processing means a series of processes for maintaining compatibility as described above. In FIG. 8, P denotes an MSB in two bits when an ATSC RS parity byte added to an enhanced data packet is converted to a symbol, E denotes an MSB of the enhanced symbol, and M denotes an MSB of the main symbol. P 'is the MSB of the ATSC RS parity symbol, which is recalculated through the compatibility processing unit. That is, P is recalculated to P 'by the compatibility processor.

In FIG. 8, for convenience of explanation, the adder 411, the mux 412, the registers 413, 414, and the adder 415 of the enhanced symbol processing unit 402 of FIG. 4B are blocked to be referred to as a precoder bypass unit.

In this case, it is assumed that data is input in order of P, M, and E to the precoder bypass unit of the enhanced symbol processor 402. In FIG. 8, initial values of the registers R0, R1, and R2 are all 0, and the P symbol is regarded and processed as the main symbol in the enhanced symbol processor 402. In this case, the output (X2 ') of the precoder bypass portion of the enhanced symbol processor 402 is made in the order of P, M, and P + M + E, and this is the free of the trellis encoder 104 via the compatibility processing portion. It is input to the coder 510. Therefore, the output C2 of the precoder 510 of the trellis encoder 104 consists of P ', P' + M, and P '+ P + E.

As a result, P '+ P + E is output without being bypassed in the case of an enhanced symbol. At this time, when P 'and P are the same, E' is bypassed as P '+ P + E = E, but when they are different, the value of E is inverted and output. If C2, the MSB, is inverted among the output 3 bits of the trellis encoder 104, the mapping of the 8-level VSB signal is performed as follows (-7 <=> +1, -5 <=> +3, -3 <=> +5, -1 <=> +7).

That is, the VSB modulator 107 maps the 8-level modulation value corresponding to the three output bits C2, C1, and C0 output from the trellis encoder 104 and outputs the mapping. For example, if C2C1C0 value is 000, it is mapped to -7, 011 to -1, and 100 to +1.

Therefore, the original C2C1C0 value should be 000. If the C2 value is reversed to 100, -7 will be mapped to +1.

Therefore, in the Viterbi decoder of the receiving system, it is necessary to estimate whether the polarity inversion of the bit C2 output from the trellis encoder of the transmitter in the case of enhanced symbols. In the present invention, this is called as polarity inversion of the enhanced symbol.

4. Branch Metric Calculator

The Viterbi algorithm is an algorithm that selects the path with the highest probability by estimating the probability of the state transition path over time of the trellis encoder.

A branch metric is a value obtained by calculating the probability of each branch on a state transition diagram at a current time, and the accumulation of branch metrics over time is called a path metric.

The branch metric can be obtained by calculating the Euclidean distance between the output level of each branch and the input signal of the Viterbi decoder. At this time, since the enhanced symbol and the main symbol received by the receiving system are 8-level signals, the branch metric calculation unit calculates the Euclidean distance of the input signal for the 8 reference levels as shown in Equation 1 below. The value BM (b) is obtained.

In Equation 1, r _n is a signal input to the Viterbi decoder at time n, and L _b corresponds to a reference eight-level VSB signal.

5. ACS section

A path metric is a cumulative value of a branch metric as a probability value corresponding to a path of a state transitioning over time, that is, a path. In the Viterbi decoder, the Accumulate / Compare / Select (ACS) section calculates and compares each path metric that is merged for each state, and then compares them with the smallest path metric value. Select the path). That is, the ACS unit adds a corresponding branch metric and a path metric of a previous state connected to the branch for each branch, and selects and stores a small value among them.

9 illustrates an example of a process of calculating a route metric. In FIG. 9, a process of calculating a path metric of a state 0000 in the case of an enhanced symbol and a main symbol, respectively, has been described as an example.

ACS operations on enhanced symbols

In the case of the enhanced symbol, as shown in (a) of FIG. 9, the previous state (time t-1) that can be merged into the state 0000 at time t is state 0000 and state 1000, respectively. At this time, if 0 is input to the input X2 of the enhanced symbol processor 402 in the state 0000 at time t-1, the reference 8 level value output from the trellis encoder 104 becomes -7 when the polarity inversion does not occur. If a polarity reversal has occurred, it becomes +1, forming a path that transitions to state 0000 at time t.

On the other hand, when state 1 of time t-1 is input to X2 and polarity inversion does not occur, +1 is output as a reference 8 level value, and if polarity inversion occurs, -7 is output, and state 0000 of time t is output. Form a path to transition.

That is, when the polarity inversion does not occur, the branch metric value of the path that transitions from the state 0000 of the time t-1 to the state 0000 of the time t becomes (input signal-(-7)) ² . On the contrary, when the polarity inversion occurs, the branch metric value of the path that transitions from the state 0000 of the time t-1 to the state 0000 of the time t becomes (input signal − (+ 1)) ² . The state 0000 at time t then adds the calculated branch metric value and the accumulated previous path metric value. At the same time, the branch metric value and the previous path metric value are similarly added to another path merged to the state 0000 of the time t, that is, a path that transitions from the state 1000 of the time t-1 to the state 0000 of the time t. Then, the addition result of the two paths merged into the state 0000 at time t is compared, and the path having the smaller value is selected as the survival path.

Therefore, the method for calculating the path metric of the state 0000 at time t is as follows.

First, the current path metric value is obtained by adding the branch metric value and the path metric value of time t-1 to the two branches merged from the time t to the state 0000.

Second, the two current path metric values are compared to select a path having the smaller path metric value as a survival path. The path metric value is then updated with the path metric value of the selected path for the next ACS calculation.

Third, the survivor and the path selection information of the selected path are output to the path history unit.

Here, the survivor becomes the input X2 bit of the enhanced symbol processor 402.

For the enhanced / main integrated Viterbi decoder of FIG. 11 to be described later, the C2 bit is additionally included as a survivor and output to the path history unit.

ACS operation of main symbol

In the case of the main symbol, as shown in (b) of FIG. 9, the previous state (time t-1) which can come to the state 0000 at time t is state 0000 and state 0010, respectively. At this time, if 0 is input to the input X1 of the enhanced symbol processor 402 in the state 0000 of the time t-1, the level value output from the trellis encoder 104 depends on the input X2 of the trellis encoder 104. 7 or +1, forming a path to state 0000 at time t.

On the other hand, if 1 is input to X1 in the state 0010 of time t-1, it becomes -3 or +5 according to the input X2 and forms a path to state 0000 of time t.

Thus, the path metric for state 0000 at time t is calculated as follows.

First, in each path (that is, branch) of state 0000, two output levels are possible according to X2. Therefore, the branch metric values are compared to select a smaller value, and the C2 bit corresponding to the selected level is output.

Second, the current path metric value is obtained by adding the branch metric value selected in the first step and the path metric value accumulated at time t-1 for the two paths merged to the state 0000 at time t.

Third, the two current path metric values obtained in the second step are compared to select a path having the smaller path metric value as a survival path. The path metric value is then updated with the path metric value of the selected path for the next ACS calculation.

Fourth, the survivor and the path selection information of the selected path are output to the path history unit. The survivor here contains the X1 of the selected path and the C2 bit of the first step. The C2 bit is the MSB of the output of the trellis encoder 104, which is later decoded into X2 bits via post decoding. That is, in the case of the main symbol, the survivor of each state has two bits, C2 and X1.

In FIGS. 12A and 12B, an example of calculating and updating the cumulative path metric of the state 0000 has been described. However, the cumulative path metric is calculated based on the state transition diagrams of the symbols input in the same manner for the other states. Calculate and update

Description of the input control signal

Since the enhanced symbol and the main symbol have different state transitions, the ACS unit needs an E / M flag indicating whether the currently input symbol is an enhanced symbol or a main symbol. In addition, among the enhanced symbols, an H / Q flag indicating whether it is a 1/2 enhanced symbol or a 1/4 enhanced symbol is required. In the case of the 1/4 enhanced symbol, a PNEQ flag is needed to indicate whether the bits repeated in the null bit expander are the same after the ATSC data renderer. Meanwhile, in order to estimate the polarity reversal of the above-described enhanced symbol, a FLIP signal indicating a time point of an ATSC RS parity symbol added to an enhanced data segment is also required.

The four control signals described above, that is, the E / M flag, the H / Q flag, the PNEQ flag, and the FLIP signal, are E8-VSB symbol attribute information output from the map information recovery unit in the receiving system.

In summary, the inputs required by the ACS section are the E / M flag, the H / Q flag, the PNEQ flag, the FLIP signal, and the branch metric values for eight levels. In addition, like the Viterbi decoder of the conventional ATSC 8T-VSB receiver, a control signal indicating the interval of the field sync signal and the segment sync signal is required. After that, the control signal indicating the field sync signal and the segment sync signal are excluded from the description.

Since there are 12 enhanced symbol processors and 12 trellis encoders in the transmission system, 12 Viterbi decoders are required in the receiving system.

FIG. 10 illustrates an example of control signals input to any one Viterbi decoder among 12 Viterbi decoders. In FIG. 10, M denotes a main signal, H denotes a 1/2 (Half) enhanced symbol, and Q denotes a 1/4 (Quarter) enhanced symbol. P denotes a symbol obtained by converting an ATSC RS parity byte added to an enhanced data packet.

In addition, if the E / M flag is high, it means that the current input symbol is an enhanced symbol, and if it is low, it is a main symbol. The H / Q flag is a signal valid only in a period that is an enhanced symbol. If the level is low, the H / Q flag indicates a 1/2 enhanced symbol and a high 1/4 symbol. The PNEQ signal is a valid signal only in case of a 1/4 enhanced symbol, and its level changes in units of two symbols. If the signal level is low, the repeated 1/4 enhanced data is changed to a different value by the ATSC renderer. If the signal is high, it means that the signal is changed to the same value. The FLIP signal is a signal indicating a time point that causes an inversion of the polarity of the enhanced symbol and is high during the ATSC RS parity symbol period added to the enhanced data packet.

ACS operations on quarter enhanced symbols

In the case of the ACS operation of the 1/4 enhanced symbol, the basic principle is the same as that of the 1/2 enhanced symbol, but the ACS unit operates differently for each two symbols. That is, if the E / M flag is high and the H / Q flag is high, it means a 1/4 enhanced symbol. In this case, the ACS operation is performed for each two symbols according to the PNEQ signal. The decoding process by the PNEQ signal has been described in detail in "2. State transition and decoding of an enhanced symbol and a main symbol".

Sharing the ACS section of 12 Viterbi decoders

Like the existing ATSC 8T-VSB Viterbi decoder, the ACS unit needs to share 12 Viterbi decoders to share hardware for add, compare and select operations. The hardware sharing is possible because 12 Viterbi decoders operate one by one instead of simultaneously. The 12 Viterbi decoders are each implemented with a positive decoder and a negative decoder, and the positive decoder and the negative decoder are each implemented with 16 states, so the total number of path metrics required is (12 x). 2 x 16) pieces.

6. Polarity Inversion Estimation of Enhanced Symbols

In the case of the enhanced symbol, since polarity inversion may occur as described above, it is necessary to estimate whether the polarity is inverted. To estimate this polarity reversal, compare the path metric when decoding assuming that no polarity reversal has occurred and the path metric when decoding assuming that polarity reversal has occurred. Follow the results.

Therefore, two decoders are required to estimate whether the enhanced symbol is inverted in polarity. The decoder that decodes assuming that inversion does not occur hereinafter is called a positive decoder, and the decoder that decodes assuming that inversion has occurred is called a negative decoder.

The process of estimating the polarity inversion of the enhanced symbol is as follows.

First, obtain the minimum path metric values in the ACS section of the positive decoder and the negative decoder, respectively. Here, the minimum path metric value means the smallest value among the minimum path metric values of each state at time t.

Second, the minimum path metric values of the positive decoder and the negative decoder are compared and the polarity signal of the decoder having the smaller value is output. For example, if the minimum path metric value of the positive decoder is less than the minimum path metric value of the negative decoder, the polarity signal becomes +. In other words, it is a signal for selecting a positive decoder.

Third, in the period in which the FLIP signal is high, the path metric values of each state of the decoder that are not selected by the polarity signal are overwritten with the corresponding path metric values of the selected decoder to perform an ACS operation. For example, assuming that the selected decoder is a positive decoder, the path metric values of each state of the positive decoder are overwritten with the path metric values of each corresponding state of the negative decoder.

In this case, if a positive decoder is selected, it is assumed that the polarity inversion does not occur. If a negative decoder is selected, it is assumed that the polarity inversion occurs.

In addition, a polarity inversion estimator for estimating polarity inversion may be shared among 12 Viterbi decoders.

7. Path History Unit

The Viterbi algorithm maintains the path history for a length of decoding depth by storing the survivor of the selected survival path in each state during the ACS process.

The path history unit receives a polarity (signal for selecting a positive decoder and a negative decoder) signal output from the polarity inversion estimator and a state number having a minimum path metric output from the ACS unit, and reverses the path history of the corresponding state. Trace-back to output the final decision.

Similarly to the ACS section, the path history section updates the path history after overwriting the path history of the decoder selected by the polarity signal in the section where the FLIP signal is high, with the path history of the unselected decoder.

Enhanced / Main Integrated Viterbi Decoder

According to the general Viterbi decoding process, since the symbols input to the Viterbi decoder are mixed with the enhanced symbols and the main symbols, the enhanced symbols and the survivors of the main symbols are stored in the same order in the path history section. The decoder then becomes an enhanced / main integrated decoder that decodes both the enhanced and main symbols. The final output of the decoder then comes out in the same order with a delay of the decoder input.

In Viterbi decoder, there are 16 states in total, and for each state, two bits of survivor must be output from the ACS unit and stored for the length of the decoder length. Therefore, memory (16 x decoder x 2 bits) is needed. . In addition, since the history of the positive and negative decoders must be maintained separately, as much memory as (2 x 16 x decoder x 2 bits) is required. On the other hand, since 12 Viterbi decoders are required, finally (12 x 2 x 16 x decoder x 2 bits) memory is required.

11 is a block diagram illustrating an enhanced / main integrated Viterbi decoder according to the first embodiment of the present invention described above.

The branch metric calculation unit 611 calculates eight branch metrics by calculating the input symbols, the eight reference output levels, and each Euclidean distance, and then obtains the ACS unit 612 of the positive decoder and the ACS unit of the negative decoder. Output to (613).

At this time, the eight-level reference value used to calculate the branch metric with the input symbol is -7, -5, -3, -1, + 1, + 3, + 5, + 7. Here, -7, -5, -3, -1 are reference output level values when the C2 bit is 0, and +1, +3, +5, +7 are reference output level values when the C2 bit is 1.

In the case of the enhanced symbol, polarity reversal may occur as described above. That is, when 0 is input to the input X2 of the enhanced symbol processor 402 in the state 0000 at time t-1, the reference eight-level value output from the trellis encoder 104 becomes -7 when no polarity inversion occurs. When the polarity reversal occurs, it becomes +1 and forms a path that transitions to the state 0000 at time t. Therefore, the branch metric value is different when there is a polarity inversion on the same path and when it does not.

Therefore, in the ACS 612 of the positive decoder, the branch metric value when the polarity inversion does not occur is received from the branch metric calculation unit 611, and the E / M, H / Q, FLIP, PNEQ, etc. are received from the map information recovery unit. ACS operation is performed by receiving the control signal. In the ACS 613 of the negative decoder, the branch metric value when the polarity inversion occurs is input from the branch metric calculation unit 611, and the E / M, H / Q, FLIP, PNEQ, etc. are received from the map information recovery unit. ACS operation is performed by receiving control signal of.

That is, the ACS units 612 and 613 of the positive decoder and the negative decoder add the corresponding branch metric and the path metric of the previous state connected with the branch to each of the two branches for each state, and select and store a small value among them. The survivor and path selection information are output to the path history sections 615 and 616 of the positive decoder and the negative decoder. For example, if the input symbol is an enhanced symbol, the survivor for each state becomes X2, C2 bits, and if the main symbol is X1, C2 bits.

 Also, the ACS units 612 and 613 of the positive decoder and the negative decoder select the smallest value among the path metric values of each state as the minimum path metric value and output the minimum path metric value to the polarity inversion estimator 614 and have the minimum path metric. The state numbers are output to the path history sections 615 and 616 of the positive decoder and the negative decoder.

According to the present invention, in the symbol period (FLIP is high) that causes the polarity inversion of the enhanced symbol, the state of each state of the decoder that is not selected as the path metric of each state of the selected decoder according to the polarity estimated by the polarity inversion estimator 614. The ACS operation is performed after the path metric is overwritten.

The polarity inversion estimating unit 614 receives a minimum path metric from the ACS units 612 and 613 of the FLIP control signal, the positive decoder, and the negative decoder, and estimates the polarity inversion. For example, if it is determined that the minimum path metric value output from the ACS unit 612 of the positive decoder is smaller than the minimum path metric value output from the ACS unit 613 of the negative decoder, it is determined that the polarity reversal has not occurred and is large. If it is determined, it is determined that the polarity reversal has occurred, and then the discrimination result (Polarity) is output to the ACS units 612 and 613 of the positive decoder and the negative decoder, and the path history units 615 and 616 of the positive decoder and the negative decoder.

The path history units 615 and 616 of the positive decoder and the negative decoder provide control signals such as E / M, H / Q, FLIP, and PNEQ, and state numbers having survivors, path selection information, and minimum path metric values of respective states. Receives the input and maintains the path history for the length of the decoder. In addition, the state corresponding to the minimum path metric of each decoder is traced back, and the survivor as long as the decoding field is output to the decision selector 617 as a decoding decision value.

Also, the path history sections 615 and 616 of the positive decoder and the negative decoder overwrite the path history of the decoder not selected by the polarity signal in the section where FLIP is high, with the path history of the selected decoder.

The decision selecting unit 617 selects a decoding determination value of the decoder selected by the polarity signal of the polarity inversion estimating unit 614 and outputs it to the post decoder 618 and the output mux 619. For example, when the positive decoder is selected by the polarity inversion estimation unit 614, the decoding decision value output from the path history unit 615 of the positive decoder is selectively output.

The C2 bit of the decoding determination value is output to the post decoder 618, and the X2 or X1 bit is directly output to the output mux 619.

That is, since the main symbol is pre-coded at the transmitter, post-decoding, which is a reverse process thereof, must be performed. In this case, the post decoder 618 performs post decoding on the C2 bit without outputting the main symbol from the enhanced symbol and outputs the result to the output mux 619.

In the case of an enhanced symbol, the output mux 619 outputs an X2 bit that is not a post-decoded result as an upper bit and a dummy bit as a lower bit, that is, an X1 bit. In the case of the main symbol, the X1 bit is output as the lower bit, and the post-decoded result is output as the upper bit.

Enhanced Dedicated Viterbi Decoder

The enhanced symbol has a significant difference in performance after decoding because additional convolutional coding is performed compared to the main symbol. However, when the enhanced symbol and the main symbol are mixed and input to the path history part, the number of the enhanced symbols in the predetermined decoding field is small, thereby reducing the effective decoding length of the enhanced symbol. This causes a problem that the decoding performance of the enhanced symbol is degraded by the main symbol. This problem is larger when the amount of enhanced data multiplexed with the main data is smaller. Therefore, in order to minimize the effect of the main symbol on the enhanced symbol, it is necessary to secure an effective symbol of the enhanced symbol by inputting only the enhanced symbol in the path history part. Since the determination of the enhanced symbol is performed only for the X2 bit, the memory required in the path history part is (12 x 2 x 16 x decoder x 1 bit).

However, since the path history unit of the enhanced dedicated Viterbi decoder operates only when the input survivor is an enhanced symbol, the order of the final decoded and output symbols differs from the order of the symbols of the Viterbi decoder input.

12 illustrates this phenomenon by way of example. FIG. 12A illustrates a sequence of input symbols input to any one of 12 Viterbi decoders. In FIG. 12, E denotes an enhanced symbol, M denotes a main symbol, and a number after E or M denotes a time index. FIG. 12 (b) shows the symbol string finally output from the enhanced / main integrated Viterbi decoder, and as described above, it can be seen that the decoding determination values are output in the same order as the input symbol string after the predetermined decoding field. Fig. 12C shows a procedure in which the decoding decision of the enhanced dedicated Viterbi decoder is output. As can be seen from (c) of FIG. 12, since eight enhanced symbols must be input to the path history part in order to make a determination on the input E1 (assuming decoding field = 8), the determination on E1 is performed when E17 is input. It is possible. Also, at the Viterbi decoder input terminal, E1 E2 E3 E4 followed by M5 M6 M7 M8 symbol, followed by E9 E10 E11 E12 symbol. Can be. This is because the path history portion of the enhanced dedicated Viterbi decoder operates only in the enhanced symbol.

Therefore, the decoding decision of the enhanced dedicated Viterbi decoder should be ordered in the same order as the symbol string of the input through re-ordering.

13 illustrates re-ordering the output with the enhanced symbols decoded. Since the decoding decision output from the path history section of the 12 Viterbi decoders is serially output in a time division manner, the demux decodes the decision value decoded in the corresponding FIFO according to the Way signal (signal indicating the number of decoders of the 12 decoders). Save it. In this case, since the FIFO buffers only enhanced symbols, the demux operates only in a section in which the E / M flag is high. The first MUX1 also operates only in a section in which the E / M flag is high and receives a way signal to output the output of the corresponding FIFO. In FIG. 13, the E / M flag and the way signal used in the first mux MUX1 have a predetermined time delay than the signal used in the demux. Meanwhile, the E / M flag used in the second mux2 is the same as that of the first mux, and the output of the first mux is multiplexed in the section where the E / M flag is high, and the dummy ( dummy) outputs data or multiplexes the output of the main dedicated Viterbi decoder. In the case of multiplexing the dummy data, an enhanced symbol and a main symbol are output in separate paths at the final output of the Viterbi decoder. When the main symbol is multiplexed, the enhanced symbol and the result of decoding the main symbol are output in one path.

14 is a block diagram of an enhanced dedicated Viterbi decoder according to a second embodiment of the present invention.

Since the branch metric calculation unit 811 and the polarity inversion estimation unit 814 are the same as the enhanced / main integrated decoder of FIG. 12, detailed descriptions thereof will be omitted. The operation of the ACS units 812 and 813 of the positive decoder and the negative decoder is also the same as that of the integrated decoder, but in the case of the enhanced symbol dedicated decoder, the survivor outputting to the path history unit includes only one bit of X2. Therefore, the memory required in the path history section 815, 816 is a total (12 x 2 x 16 x decoder x 1 bit).

In addition, the enhanced dedicated Viterbi decoder further includes an enhanced reordering unit 818 for reordering described with reference to FIGS. 12 and 13.

Since the main dedicated Viterbi decoder is the same as the Viterbi decoder of the conventional ATSC 8T-VSB receiver, the description thereof will be omitted.

8. Decision Feedback to the Channel Equalizer System

The channel equalizer system used in the receiving system performs channel equalization using a decision on eight-levels. Compared to making an judgment using an 8-level slicer, the decision value obtained by performing Viterbi decoding is more reliable. Therefore, the present invention can improve the performance of channel equalization by feeding back the 8-level decision performed in the Viterbi decoder to the channel equalization system.

Judgment feedback in ACS section

The ACS section of the Viterbi decoder finds the state with the minimum path metric and feeds back the output level (one of the eight-levels) of the selected path to the channel equalization system. In this case, one of the output level of the ACS unit of the positive decoder and the negative decoder is selected and fed back to the channel equalization system according to the polarity signal of the enhanced inversion estimation unit of the polarity symbol. This conceptually corresponds to the decision feedback of a Viterbi decoder with zero decoding.

Judgment feedback at each decoder

As the determination value of the Viterbi decoder increases to a certain extent, the reliability of the determination increases. However, as the decoding length increases, the time delay until the decoding decision increases. Each time the decoding length of the Viterbi decoder increases by 1, the time delay of the decision feedback increases by 12 symbol times. However, in the channel equalizer system, if the path history unit feeds back the decoding decision for each decoding field, the decision value with the highest reliability can be used within the allowable time delay.

To this end, when outputting the survivor from the ACS unit of the Viterbi decoder, information about the output level of the selected path, that is, three bits of C2C1C0 should be added. The route history unit stores this and maintains the history corresponding to the decoding time. In each trace-back stage, a survivor having a minimum path metric is output and fed back to the channel equalizer system.

In the channel equalizer system, since both the enhanced symbol and the main symbol should receive decision feedback and have a low decision delay, it is preferable to feed back based on the enhanced / main integrated Viterbi decoder. To this end, C2C1C0 is additionally output when the survivor is output from the ACS unit of FIG. 11. In addition, the path history unit stores two bits of C2C1C0 in addition to the existing two bits, finds a state having the minimum path metric input from the ACS unit, and outputs C2C1C0 from each decoder to feed back to the channel equalizer system. Of course, the feedback output from the positive decoder and the feedback output from the negative decoder should be selected by the polarity signal of the polarity inversion estimator.

On the other hand, the terms used in the present invention (terminology) are terms defined in consideration of the functions in the present invention may vary according to the intention or practice of those skilled in the art, the definitions are the overall contents of the present invention It should be based on.

The present invention is not limited to the above-described embodiments, and can be modified by those skilled in the art as can be seen from the appended claims, and such modifications are within the scope of the present invention. .

The effect of the Viterbi decoder of the reception system according to the present invention described above is as follows.

First, both the enhanced symbol and the main symbol can be Viterbi decoded.

Second, in the case of an enhanced symbol, decoding performance of an enhanced symbol processor and a trellis coder of a transmitter can be decoded at once.

Third, among the enhanced symbols, the 1/2 enhanced symbol and the 1/4 enhanced symbol can be divided and decoded, and the reliability of the 1/4 enhanced symbol decoding is higher than the reliability of the 1/2 enhanced symbol decoding.

Fourth, it is possible to estimate whether the polarity of the enhanced symbol is reversed.

Fifth, by implementing the enhanced dedicated Viterbi decoder, it is possible to minimize the adverse effect of the main symbol on the decoding performance of the enhanced symbol.

Sixth, channel equalization performance can be improved by feeding back the determination of the 8-level performed in the Viterbi decoder to the channel equalizer system.

Those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention.

Therefore, the technical scope of the present invention should not be limited to the contents described in the embodiments, but should be defined by the claims.

Claims (30)

A first ACS unit that assumes that the polarity of the input symbol is not inverted and outputs the survivor and path selection information of each state by performing an ACS operation on the input symbol according to an attribute of the input symbol; A second ACS unit that assumes that the polarity of the input symbol is inverted and outputs a survivor and path selection information of each state by performing an ACS operation on the input symbol according to an attribute of the input symbol; A first path history unit which receives the survivor and path selection information of each state from the first ACS unit and traces back a state having a minimum path metric as a decoding decision value by outputting a survivor as long as a decoding station; A second path history unit which receives the survivor and path selection information of each state from the second ACS unit and traces back a state having a minimum path metric, and outputs a survivor as long as a decoding station as a decoding decision value; A polarity inversion estimator for estimating polarity of an input symbol and outputting an estimated polarity signal; And And a decision selector for selecting and outputting one of decoding decision values output from the first and second path history parts according to the polarity signal of the polarity inversion estimator. The method of claim 1, The symbol attribute input to the first and second ACS units may be a first indication flag indicating whether the input symbol is a main symbol or an enhanced symbol, or the input symbol is an enhanced symbol encoded at a 1/2 code rate. A second indication flag indicating whether or not an enhanced symbol coded at 1/4 code rate, a third indication flag indicating whether the input symbol is recalculated RS parity, and an enhanced symbol coded at 1/4 code rate And at least one of the fourth indication flags indicating whether the two bits of have the same value or different values after data rendering. The method of claim 2, wherein the first and second ACS unit A Viterbi decoder, if the input symbol is a symbol encoded at a 1/4 code rate, ACS is performed in units of two symbols. The method of claim 2, wherein the first and second ACS unit A Viterbi decoder, characterized in that the ACS is performed considering only the same paths for two symbols when the input symbols are encoded at a 1/4 code rate and the repeated bits are confirmed to be the same after data randomization. The method of claim 2, wherein the first and second ACS unit A Viterbi decoder, characterized in that the ACS is performed considering only different paths during two symbols when the input symbols are encoded at a 1/4 code rate and the repeated bits are confirmed to be different after data randomization. The method of claim 1, The first ACS unit assumes that the polarity of the input symbol is not inverted and receives the corresponding branch metric value and the property of the input symbol, and thus, the branch metric and the path of the previous state connected to the branch for two branches for each state. Viterbi decoder characterized by adding the metric, select a small value of the metric and save it, and then outputs the survivor and the path selection information. The method of claim 1, The second ACS unit assumes that the polarity of the input symbol is inverted, receives a corresponding branch metric value and an attribute of an input symbol, and corresponds to the corresponding branch metric and the path metric of the previous state connected to the branch for each branch. Viterbi decoder characterized in that after adding and selecting a small value of the stored and then output the survivor and the path selection information. The method of claim 1, wherein the first and second ACS unit And updating the path metric values of the first and second ACS units by using the path metric values at the previous time of the ACS unit corresponding to the polarity signals estimated by the polarity inversion estimator. The method of claim 1, wherein the first and second path history unit And updating the path history of the first and second path history parts by using the path history at a previous time of the path history part corresponding to the polarity signal estimated by the polarity inversion estimator. The method of claim 1, If the input symbol is an enhanced symbol, an X2 bit is output as an upper bit among the decoding determination values output from the decision selecting unit, a dummy bit is output as a lower bit, If the input symbol is the main symbol, Viterbi decoder further comprises an output unit for post-decoding the C2 bit of the decoding determination value output from the decision selector to the upper bit, and outputs the X1 bit as the lower bit. The method of claim 1, And a rearranging unit for rearranging and outputting the X2 bit values in the same order as the input symbol string using the buffer among the decoding decision values output from the decision selecting unit. The method of claim 1, wherein the polarity inversion estimation unit The smallest value of the path metric values of each state calculated by the first ACS unit is compared with the smallest value of the path metric values of each state calculated by the second ACS unit, and corresponds to the ACS unit having the smaller value. Viterbi decoder, characterized in that for outputting a polarity signal. The method of claim 1, And the first and second ACS units and the polarity inversion estimator are shared among N Viterbi decoders in a receiving system. The method of claim 1, wherein the first and second ACS unit A feedback processing unit for feeding back the reference output level of the selected survival path for channel equalization in the state having the smallest value among the path metric values of each state, wherein the first ACS unit or the second ACS unit in accordance with the polarity signal Viterbi decoder, characterized in that for selecting and feeding back the reference output level. The method of claim 1, wherein the first and second path history unit And a feedback processing unit for feeding back a decoding decision value for channel equalization for each decoding chapter, wherein the decoding decision value output from the first path history unit or the second path history unit is fed back according to the polarity signal. Viterbi decoder. A first ACS unit that assumes that the polarity of the input symbol is not inverted and performs an ACS operation on the input symbol according to a corresponding branch metric value and an attribute of the input symbol to output survivors and path selection information of each state; A second ACS unit that assumes that the polarity of the input symbol is inverted and performs an ACS operation on the input symbol according to a corresponding branch metric value and an attribute of the input symbol to output survivors and path selection information of each state; A first path history unit which receives the survivor and path selection information of each state from the first ACS unit and traces back a state having a minimum path metric as a decoding decision value by outputting a survivor as long as a decoding station; A second path history unit which receives the survivor and path selection information of each state from the second ACS unit and traces back a state having a minimum path metric, and outputs a survivor as long as a decoding station as a decoding decision value; A polarity inversion estimator for estimating polarity of an input symbol and outputting an estimated polarity signal; A decision selector which selects and outputs one of decoding decision values output from the first and second path history parts according to the polarity signal of the polarity inversion estimator; A post decoder which post-decodes the C2 bits among the decoding determination values selectively output by the decision selecting unit; And An output unit for outputting an X1 bit of a decoding decision value of the decision selector as a lower bit, and outputting one of the output of the X2 bit and the post decoder of the decision selector as an upper bit depending on whether an input symbol is an enhanced symbol or a main symbol; Viterbi decoder, characterized in that the enhanced / main integrated Viterbi decoder. The method of claim 16, The symbol attribute input to the first and second ACS units may be a first indication flag indicating whether the input symbol is a main symbol or an enhanced symbol, or the input symbol is an enhanced symbol encoded at a 1/2 code rate. A second indication flag indicating whether or not an enhanced symbol coded at 1/4 code rate, a third indication flag indicating whether the input symbol is recalculated RS parity, and an enhanced symbol coded at 1/4 code rate And at least one of the fourth indication flags indicating whether the two bits of have the same value or different values after data rendering. The method of claim 16, wherein the first and second ACS unit And updating the path metric values of the first and second ACS units by using the path metric values at the previous time of the ACS unit selected by the polarity signal estimated by the polarity inversion estimator. The method of claim 16, wherein the first and second path history unit And updating the path history of the first and second path history parts by using the path history at the previous time of the path history part selected by the polarity signal estimated by the polarity inversion estimator. The method of claim 16, wherein the polarity inversion estimation unit And outputting a polarity signal corresponding to an ACS unit having a smaller path metric value among the minimum path metric value calculated in the first ACS unit and the minimum path metric value calculated in the second ACS unit. The method of claim 16, And a branch metric calculation unit for calculating each branch metric value between the input symbol and n preset reference output levels and outputting the branch metric value to the first and second ACS units. The method of claim 16, And the X2 bit corresponds to an upper bit before trellis encoding on the transmitting side, the X1 bit corresponds to a lower bit, and the C2 bit is a value corresponding to the most significant bit after trellis encoding. delete The method of claim 16, A feedback processing unit for feeding back the reference output level of the selected survival path in the state having the smallest of the path metric values of each state for channel equalization, wherein the feedback processing unit according to the polarity signal, the first ACS unit or the first 2 Viterbi decoder, characterized in that for selecting and feeding back a reference output level output from the ACS. The method of claim 16, Each decoder further includes a feedback processor for feeding back a decoding decision value for channel equalization, wherein the feedback processor selects a decoding decision value output from the first path history unit or the second path history unit according to the polarity signal. Viterbi decoder characterized in that the feedback. A first ACS unit that assumes that the polarity of the input symbol is not inverted and performs an ACS operation on the input symbol according to a corresponding branch metric value and an attribute of the input symbol to output survivors and path selection information of each state; A second ACS unit that assumes that the polarity of the input symbol is inverted and performs an ACS operation on the input symbol according to a corresponding branch metric value and an attribute of the input symbol to output survivors and path selection information of each state; A first path history unit which receives the survivor and path selection information of each state from the first ACS unit and traces back a state having a minimum path metric as a decoding decision value by outputting a survivor as long as a decoding station; A second path history unit which receives the survivor and path selection information of each state from the second ACS unit and traces back a state having a minimum path metric, and outputs a survivor as long as a decoding station as a decoding decision value; A polarity inversion estimator for estimating polarity of an input symbol and outputting an estimated polarity signal; A decision selector which selects and outputs one of decoding decision values output from the first and second path history parts according to the polarity signal of the polarity inversion estimator; And And an enhanced dedicated Viterbi decoder including a reordering unit for rearranging and outputting the upper bit values among the decoding decision values output from the decision selecting unit in the same order as the input symbol string using a buffer. The method of claim 26, wherein the first and second ACS unit And updating the path metric values of the first and second ACS units by using the path metric values at the previous time of the ACS unit selected by the polarity signal estimated by the polarity inversion estimator. The method of claim 26, wherein the first and second path history unit And updating the path history of the first and second path history parts by using the path history at the previous time of the path history part selected by the polarity signal estimated by the polarity inversion estimator. 27. The apparatus of claim 26, wherein the polarity inversion estimation unit And outputting a polarity signal corresponding to an ACS unit having a smaller path metric value among the minimum path metric value calculated in the first ACS unit and the minimum path metric value calculated in the second ACS unit. The method of claim 26, And a branch metric calculation unit for calculating each branch metric value between the input symbol and n preset reference output levels and outputting the branch metric value to the first and second ACS units.

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