CN105119685A - Data interlacing/de-interlacing method and device - Google Patents
Data interlacing/de-interlacing method and device Download PDFInfo
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Abstract
The invention discloses a data interlacing/de-interlacing device, and the device is characterized in that the device comprises a short interlacing depth processing unit for processing a short interlacing depth, and a long interlacing depth processing unit for processing a long interlacing depth. Correspondingly, the invention also discloses a data interlacing/de-interlacing method. The device and method can achieve the interlacing/de-interlacing of data in a parallel input mode, improve the data transmission rate of a communication system and the supporting capability for big-data communication, and can achieve the high-speed transmission of data according to a CCSDS standard.
Description
Technical field
The present invention relates to communication decoding technique field, particularly a kind of interleaving/deinterleaving method of high speed data transfers and device for meeting CCSDS specification.
Background technology
Intertexture and deinterleaving are a kind of methods of the very practical structure code be also in daily use, and combine with other coded systems (as block encoding), so not only can correct random error, can also be used to correct burst error, so be usually used in aggregate channel error correction system.Some channel coding technologies such as RS encodes, and after adding interleaving technology, can improve interference free performance further.The basic thought of interleaving technology is exactly the shooting sequence changing code element at the transmitting terminal of data, is memoryless channel, thus makes error correction coding be equally applicable to burst of noise channel by a channels with memory successful transformation.Interleaver code element in the scope of several block length (for block code) or several constraint length (for convolution code) is resequenced.This length is determined by the length of burst duration.
The mode that combined with RS encoder/decoder by interleaving/deinterleaving data processing method is adopted to interweave-decoding-deinterleaving process to data in CCDSD specification.
In available data transmission system, the processing mode that-RS encoder/decoder-deinterleaving combines although interweave can meet corresponding demand, but for big data quantity and high speed data transfers system, in order to meet the requirement of system data throughput and speed, the mode of data acquisition parallel transmission, existing intertexture-RS encoder/decoder-deinterleaving process structure is difficult to the parallel transmission mode under adaptation two-forty, data stacking is easily caused to cause error code, self structure also limit the transmission rate of system, some method adopts RAM or SDRAM to carry out data storage simultaneously, the read/write address that its interleaving mode is corresponding relates to the determinant conversion of address matrix, the larger complexity of difficulty is higher.
Summary of the invention
In order to solve at least one problem above-mentioned and/or deficiency, and provide at least one advantage following.
The invention provides a kind of interleaving/deinterleaving method and device, adopt the present invention can realize carrying out interleaving/deinterleaving process to the data of parallel input mode, thus promote the message transmission rate of communication system and the tenability to large data communication, and the transmission of high data rate can be realized according to CCSDS specification.
For solving the problems of the technologies described above, the technical solution adopted in the present invention is as follows:
A kind of interleaving/deinterleaving device, comprising: the short delivery for the treatment of short interleave depth knits advanced treatment unit and the long interleave depth processing unit for the treatment of long interleave depth,
Described short delivery is knitted advanced treatment unit and is comprised short interleave depth interleaving block and short interleave depth de-interleaving block,
Described short interleave depth interleaving block comprises passage gating module, multiple short interleave depth interleaver and data reconstruction module, described passage gating module receives parallel input data, and parallel described input data is outputted to the multiple short interleave depth interleaver of gating according to interleave depth parameter; Multiple described short interleave depth interleaver completes, to after the intertexture of parallel described input data, interleaving data is outputted to described data reconstruction module, and described data reconstruction module exports after described interleaving data reconstruct according to described interleave depth parameter;
Described short interleave depth de-interleaving block comprises passage selected input module, data reorganization module, multiple short interleave depth deinterleaver and passage gating output module, described passage selected input module receives the interleaving data after reconstruct according to described interleave depth parameter selected input port, described data reorganization module receives the interleaving data after the reconstruct of the reception of described passage selected input module, and according to described interleave parameter, restructuring acquisition recombination data is carried out to the interleaving data after reconstruct, multiple described short interleave depth deinterleaver obtains described recombination data respectively and completes deinterleaving process, data strobe after deinterleaving exports by described passage gating output module,
Described long interleave depth processing unit comprises long interleave depth interleaving block and long interleave depth de-interleaving block;
Described long interleave depth interleaving block comprises address mapping data reconstructed module, multiple output buffer memory and exports gating module, described address mapping data reconstructed module receives parallel input data, and according to the address maps rule that described interleave depth parameter is determined, described parallel data is converted into mapping (enum) data output; Multiple described output buffer memory receives described mapping (enum) data, and is exported as interleaving data by described mapping (enum) data according to the gating signal that described output gating module produces; Described gating signal is determined according to described interleave depth parameter by described output gating module;
Described long interleave depth de-interleaving block comprises input port gating module, multiple input-buffer, address mapping module, reads enable signal generation module and address mapping data reconstructed module, described input port gating module according to described interleave depth parameter selected input port for receiving described interleaving data; Multiple described input-buffer receives described interleaving data from described input port gating module; Described enable signal generation module of reading produces and reads enable signal and by the corresponding described input-buffer of described address mapping module gating; The described input-buffer be strobed exports described interleaving data to described address mapping data reconstructed module; Described address mapping data reconstructed module exports after the described interleaving data reconstruct received as deinterleaved data.
Further, also comprise: intertexture gating module, knitting advanced treatment unit or long interleave depth processing unit for exporting described input data to short delivery according to intertexture way, if described intertexture way is less than setting intertexture way, exports described input data to short delivery and knitting advanced treatment unit; If described intertexture way is greater than described setting intertexture way, then export described input data to long interleave depth processing unit.
Further, described short interleave depth interleaver comprises multiple short delivery and knits input-buffer, short delivery knits address mapping module, first reads enable signal generation module and short delivery knits address mapping data reconstructed module, multiple described short delivery knits the described input data that input-buffer walks abreast for buffer memory, when the described input data that multiple described short delivery knits input-buffer are frame data, described first reads the generation of enable signal generation module reads enable signal, described short delivery knit address mapping module utilize according to address mapping ruler described in read enable signal the described input data of knitting in input-buffer export described short delivery to and knit address mapping data reconstructed module by described short delivery, described short delivery is knitted address mapping data reconstructed module and the described input data after restructuring is exported as interleaving data.
Further, described short interleave depth deinterleaver comprises that short delivery knits serioparallel exchange module, short delivery knits address mapping module, multiple short delivery is knitted and exported buffer memory and second and read enable signal generation module, and described short delivery is knitted serioparallel exchange module and described recombination data parallel output to described short delivery is knitted address mapping module; Described short delivery is knitted address mapping module and is exported described recombination data to multiple described short delivery respectively according to address mapping ruler and knit output buffer memory; When multiple described short delivery described recombination data knitted in output buffer memory is frame data, described second reads enable signal generation module reads enable signal according to the generation of described address maps rule is multiple; Multiple described short delivery is knitted and is exported buffer memory and exported as deinterleaved data by described recombination data according to reading enable signal described in receiving.
A kind of interleaving/deinterleaving coding method, comprises the following steps:
Judge intertexture way, if described intertexture way is less than setting intertexture way, then short interleaving treatment and short deinterleaving process are carried out to parallel input data; Otherwise long interleaving treatment and long deinterleaving process are carried out to parallel input data;
Described short delivery is knitted process and is comprised:
According to interleave depth parameter, parallel described input data are carried out short interleaving treatment respectively;
According to interleave depth parameter, the data after short interleaving treatment are reconstructed;
After reconstructing, data are as short delivery organization data parallel output;
Described short deinterleaving process comprises:
Receive according to the described short delivery organization data of described interleave depth parameter to parallel input;
According to interleave parameter, described short delivery organization data is recombinated;
Short deinterleaving process is carried out to the short delivery organization data after restructuring;
Data strobe after short deinterleaving is exported;
Described long interleaving treatment comprises:
Receive parallel input data;
Determine address mapping ruler according to interleave depth parameter, parallel upper described input data are converted to mapping (enum) data according to described address maps rule;
Described mapping (enum) data is carried out respectively interleaving treatment and generate interleaving data;
Described long deinterleaving process comprises:
According to described interleave depth parameter, selected input is carried out to described interleaving data;
Buffer memory is carried out to the described interleaving data of selected input;
The described interleaving data be buffered exports as deinterleaved data after carrying out exporting and reconstruct according to gating rule.
By adopting technical solution of the present invention compared with prior art, tool has the following advantages: be compared to prior art, the parallel data of the present invention to input carries out parallel processing, for the Data classification process under different interleaving depths, not only improve the reliability of system but also meet the two-forty requirement of parallel data processing.Adopt this kind of technical scheme to carry out the interleaving/deinterleaving of high data rate, process complexity is lower, takies resource less.
Accompanying drawing explanation
In order to be illustrated more clearly in the technical scheme in the embodiment of the present invention, below the accompanying drawing used required in describing the embodiment of the present invention is briefly described, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained according to the content of the embodiment of the present invention and these accompanying drawings.
Fig. 1 is embodiment of the present invention interleaving/deinterleaving device schematic diagram;
Fig. 2 is the embodiment of the present invention short interleave depth interleaving block schematic diagram;
Fig. 3 is the embodiment of the present invention short interleave depth de-interleaving block schematic diagram;
Fig. 4 is the embodiment of the present invention long interleave depth interleaving block schematic diagram;
Fig. 5 is the embodiment of the present invention long interleave depth de-interleaving block schematic diagram;
Fig. 6 is the embodiment of the present invention short interleave depth interleaver schematic diagram;
Fig. 7 is the embodiment of the present invention short interleave depth deinterleaver structural representation;
Fig. 8 is that embodiment of the present invention short delivery knits mapping address algorithm schematic diagram in advanced treatment unit;
Fig. 9 is mapping address algorithm schematic diagram in the long interleave depth processing unit of the embodiment of the present invention.
Embodiment
The technical problem solved for making the present invention, the technical scheme of employing and the technique effect that reaches are clearly, be described in further detail below in conjunction with the technical scheme of accompanying drawing to the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those skilled in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
Technical scheme of the present invention is further illustrated by embodiment below in conjunction with accompanying drawing.
Fig. 1 is embodiment of the present invention interleaving/deinterleaving device schematic diagram.
With reference to figure 1, in interleaving/deinterleaving device of the present invention, comprise short delivery and knit advanced treatment unit and long interleave depth processing unit.Short delivery is knitted advanced treatment unit and is knitted advanced treating for carrying out short delivery to input data, and long interleave depth processing unit is used for carrying out long interleave depth process to input data.
Knit in advanced treatment unit at short delivery, comprise short interleave depth interleaving block and short interleave depth de-interleaving block, wherein, short interleave depth interleaving block has been used for input data and has carried out short interleaving treatment, and short interleave depth de-interleaving block is used for carrying out deinterleaving process to the input data after short interleaving treatment.Above-mentioned short interleaving treatment and knit corresponding deinterleaving process with short delivery and form short delivery and knit advanced treating.
In long interleave depth processing unit, comprise long interleave depth interleaving block and long interleave depth de-interleaving block.To knit advanced treating similar with short delivery, and long interleave depth interleaving block is used for carrying out long interleaving treatment to input data, and long interleave depth de-interleaving block is used for carrying out deinterleaving process to the input data after long interleaving treatment.Equally, above-mentioned long interleaving treatment and form long interleave depth process with the long deinterleaving process interweaving corresponding.
Above-mentioned short delivery is knitted advanced treating and is divided according to the way of interleaving treatment is different with long interleave depth process, even setting intertexture way is less than to the way of carrying out interleaving treatment of input data, then carry out short delivery and knit advanced treating, otherwise carry out long interleave depth process.
Fig. 2 is the embodiment of the present invention short interleave depth interleaving block schematic diagram.
Fig. 3 is the embodiment of the present invention short interleave depth de-interleaving block schematic diagram.
With reference to figure 2, short interleave depth interleaving block comprises passage gating module, multiple short interleave depth interleaver and data reconstruction module.Passage gating module receives the input data of multidiameter delay, and the multichannel data received is cushioned, after data are cushioned, according to interleave depth parameter input data are outputted to certain in multiple short interleave depth interleaver several in, multiple short interleave depth interleaver exports the interleaving data generated through process after each triggering.Data reconstruction module receives the interleaving data that multiple short interleave depth interleaver exports respectively, and is reconstructed rear output according to interleave depth parameter to multipath interleaving data.
With reference to figure 3, short interleave depth de-interleaving block carries out deinterleaving process to interleaved data, and this short interleave depth de-interleaving block comprises passage selected input module, data reorganization module, multiple short interleave depth deinterleaver and passage gating output module.
Passage selected input module arranges gating the corresponding interface as input port, to receive through multipath interleaving data according to interleave depth parameter.As shown in Figure 3, in embodiments of the present invention, passage selected input module installation has 8 input ports, and each input port takies 8bit bit wide, and interleaving data is input in data reorganization module by the input port of gating.
Data reorganization module is recombinated to input data according to arranging of interleave depth parameter, and the output interface number of data reorganization module is corresponding with short interleave depth deinterleaver.In embodiments of the present invention, data reorganization module has 4 output ports, each output port bit wide 32bit, according to the setting of interleave depth parameter, takies different bit wides when each output port exports data.Corresponding with 4 output ports, the embodiment of the present invention has 4 short interleave depth deinterleavers, and 4 tunnels of data reorganization module export data and are input to the deinterleaving carrying out data in 4 short interleave depth deinterleavers respectively.Data after deinterleaving output to passage gating output module, data are exported by this passage gating output module.
Fig. 4 is the embodiment of the present invention long interleave depth interleaving block schematic diagram.
Fig. 5 is the embodiment of the present invention long interleave depth de-interleaving block schematic diagram.
With reference to figure 4, long interleave depth interleaving block comprises address mapping data reconstructed module, multiple output buffer memory and exports gating module.
Address mapping data reconstructed module receives the input data of multidiameter delay, and produces mapping address algorithm according to interleave depth parameter, thus input data are converted to mapping (enum) data output by mapping address algorithm.Multiple output buffer memory is used for the mapping (enum) data that receiver address mapping (enum) data reconstructed module exports.Export buffer memory to be used for cushioning the address mapping data of input, and under the gating signal exporting gating module generation controls, mapping (enum) data exported thus complete interleaving treatment.
With reference to figure 5, long interleave depth de-interleaving block comprises input port gating module, multiple input-buffer, address mapping module, reads enable signal generation module and address mapping data reconstructed module.Input port gating module is according to interleave depth parameter selected input port for receiving described interleaving data, and the multiple input-buffers be connected with input port gating module receive the interleaving data inputted.Read enable signal generation module to produce and read enable signal and by the corresponding input-buffer of described address mapping module gating.The input-buffer be strobed exports interleaving data to address mapping data reconstructed module; Address mapping data reconstructed module exports after the interleaving data received reconstruct as deinterleaved data.
Further, in embodiments of the present invention, for completing the selection of short delivery being knitted to advanced treatment unit and long interleave depth processing unit, the embodiment of the present invention also comprises intertexture gating module, and this intertexture gating module is used for exporting input data to short delivery according to intertexture way and knits advanced treatment unit or long interleave depth processing unit.
For realizing selection input data being exported to respective handling unit, intertexture gating module judges according to intertexture way, if intertexture way is less than setting intertexture way, exports input data to short delivery and knits advanced treatment unit; If described intertexture way is greater than setting intertexture way, then export input data to long interleave depth processing unit.
For being described in further details the present invention, in the embodiment of the present invention for completing short/long interleave depth interleaving block of interleaving treatment and short/long interleave depth de-interleaving block for completing deinterleaving process is further described.
Fig. 6 is the embodiment of the present invention short interleave depth interleaver schematic diagram.
Fig. 7 is the embodiment of the present invention short interleave depth deinterleaver structural representation
Fig. 8 is that embodiment of the present invention short delivery knits mapping address algorithm schematic diagram in advanced treatment unit.
Fig. 9 is mapping address algorithm schematic diagram in the long interleave depth processing unit of the embodiment of the present invention.
With reference to figure 6, short interleave depth interleaver comprises multiple short delivery and knits input-buffer FIFO, address mapping module, read enable signal generation module and short delivery knits address mapping data reconstructed module, multiple input-buffer FIFO carries out buffer memory to multichannel road input data respectively, until complete the storage of a whole frame to multidiameter delay data, now start read FIFO read enable signal generation module produce read FIFO enable signal, read enable signal and carry out there is object through address mapping module, read FIFO operation orderly, address mapping module is according to the interleave depth parameter of input, produce according to mapping address algorithm and read fifo address mark accordingly, thus make corresponding short delivery knit input-buffer FIFO the data of buffer memory are exported, short delivery is knitted data cached that FIFO exports by address mapping data reconstructed module and is reconstructed rear output.The mapping address algorithm contrary used in the above-mentioned mapping address algorithm that uses at short interleave depth interleaver and short interleave depth deinterleaver.
With reference to figure 7, short interleave depth deinterleaver comprises that short delivery knits serioparallel exchange module, short delivery knits address mapping module, multiple short delivery is knitted and exported buffer memory FIFO and second and read enable signal generation module.
Short delivery is knitted serioparallel exchange module and recombination data parallel output is knitted address mapping module to short delivery.Short delivery is knitted address mapping module and recombination data is exported respectively to multiple short delivery according to address mapping ruler and knit and export buffer memory FIFO.When multiple short delivery recombination data knitted in output buffer memory is frame data, second reads enable signal generation module reads enable signal according to mapping ruler generation in address is multiple, and multiple short delivery is knitted output buffer memory and exported as deinterleaved data by recombination data according to the enable signal of reading received.
With further reference to Fig. 8, knitting address maps rule in advanced treatment unit at short delivery is: the array num establishing a variable number, and when interleave depth parameter is 1, array only has num [0] variable; When interleave depth is 2, array is made up of num [0] and num [1]; When interleave depth is 3, array is by num [0], and num [1] and num [2] forms.It can thus be appreciated that array number is interleave depth parameter, then can become by unified representation:
If { ni} is the ascending arrangement of integer being more than or equal to 0 and being less than interleave depth parameter, and for the interleave depth parameter determined, the address designation array corresponding to it is num [n1], num [n2],, num [nK], K equals interleave depth parameter altogether.
When interleave depth is 1, the FIFO order identification of periodically reading of generation is
When interleave depth is 2, the FIFO order identification of reading of generation is
When interleave depth is 3, the FIFO order identification of reading of generation is
Read FIFO enable signal and trigger corresponding FIFO according to the instruction of address designation, read corresponding data and be input to address mapping data reconstructed module, data recombination is carried out according to address maps mode, and export data according to the corresponding output branch road of interleave depth parameter gating, namely achieve data interlacing when interleave depth is less than 4.
With reference to figure 9, the address variable number that mapping address algorithm is used in long interleave depth processing unit and the interleave depth parameter interlace_num of input have nothing to do, the number of address variable has and only has 4, is set to N [0] respectively, N [1], N [2] and N [3], generic representation becomes { N [i] }, i=0,1,2,3.
As interlace_num=5,
As interlace_num=8,
Composition graphs 4, is described further, and as interlace_num=5,4 road input signals are input in data reconstruction module, and data reconstruction module is according to address mapping table during interlace_num=5:
In the 1st clock, 4 road input signal input_0, input_1, input_2 and input_3 are pressed address designation, correspondence is written in FIFO_0, FIFO_1, FIFO_2 and FIFO_3;
In 2nd clock, 4 road input signal correspondences are written in FIFO_4, FIFO_0, FIFO_1 and FIFO_2;
In 3rd clock, 4 road input signal correspondences are written in FIFO_3, FIFO_4, FIFO_0 and FIFO_1;
In 4th clock, 4 road input signal correspondences are written in FIFO_2, FIFO_3, FIFO_4 and FIFO_0;
In 5th clock, 4 road input signal correspondences are written in FIFO_1, FIFO_2, FIFO_3 and FIFO_4.
……
Wherein often through 5 clock cycle, 20 byte datas of all periodic input that walked abreast on 4 roads, the interleaving mode being 5 according to interleave depth is written with in 5 FIFO respectively, achieves and stores converting 5 circuit-switched data to after 4 tunnel input data interlacings.
Meanwhile, according to mapping address algorithm, be in the interweaving encoding process of 5 realizing interleave depth, data reconstruction module output pin has only used 5 output interfaces, according to address mapping table FIFO_5, FIFO_6 and FIFO_7 by automatic shield.
By whole frame data after intertexture write 5 FIFO, read data operation is carried out to these 5 FIFO of FIFO_0-FIFO_4 simultaneously, and these 5 pins of gating output_0-outpu_4 are as output interface, the data that these 5 output interfaces of output_0-output_4 export are the data after intertexture.
As interlace_num=8,4 road input signals are input in data reconstruction module, and data reconstruction module is according to address mapping table during interlace_num=8:
In the 1st clock, 4 road input signal input_0, input_1, input_2 and input_3 are pressed address designation, correspondence is written in FIFO_0, FIFO_1, FIFO_2 and FIFO_3;
In the 2nd clock, 4 road input signal correspondences are written in FIFO_4, FIFO_5, FIFO_6 and FIFO_7;
……
Wherein often through 2 clock cycle, 8 byte datas of all periodic input that walked abreast on 4 roads, the interleaving mode being 8 according to interleave depth is written with in 8 FIFO respectively, achieves and stores converting 8 circuit-switched data to after 4 tunnel input data interlacings.
Simultaneously according to mapping address algorithm, be in the interweaving encoding process of 8 realizing interleave depth, data reconstruction module output pin has used 8 interfaces simultaneously, and therefore corresponding 8 FIFO that also used carry out buffer memory to output data.
By whole frame data after intertexture write 8 FIFO, read data operation is carried out to these 8 FIFO of FIFO_0-FIFO_7 simultaneously, and by these 8 pins of output_0-output_7 as output interface, export the data after interweaving.
Particularly point out and work as interlace_num=4, namely when interleave depth is 4, the 4 non-interleaving datas in tunnel of interleaved data and input are structurally completely the same, so can these 4 output interfaces of gating output_0-output_3, directly this 4 channel parallel data of output input_0-input_3.
Corresponding with embodiment of the present invention said apparatus, in an alternative embodiment of the invention, for carrying out interleaving/deinterleaving coding method to parallel data, comprise the following steps:
Judge intertexture way, if intertexture way is less than setting intertexture way, then short interleaving treatment and short deinterleaving process are carried out to parallel input data; Otherwise right input data carry out long interleaving treatment and long deinterleaving process;
Short delivery is knitted process and is comprised:
According to interleave depth parameter, parallel input data are carried out short interleaving treatment respectively;
According to interleave depth parameter, the data after short interleaving treatment are reconstructed;
After reconstructing, data are as short delivery organization data parallel output;
Short deinterleaving process comprises:
Receive according to the short delivery organization data of interleave depth parameter to parallel input;
According to interleave parameter, short delivery organization data is recombinated;
Short deinterleaving process is carried out to the short delivery organization data after restructuring;
Data strobe after short deinterleaving is exported;
Long interleaving treatment comprises:
Receive parallel input data;
Determine address mapping ruler according to interleave depth parameter, parallel upper described input data are converted to mapping (enum) data according to described address maps rule;
Mapping (enum) data is carried out respectively interleaving treatment and generate interleaving data;
Long deinterleaving process comprises:
According to interleave depth parameter, selected input is carried out to interleaving data;
Buffer memory is carried out to the interleaving data of selected input;
The described interleaving data be buffered exports as deinterleaved data after carrying out exporting and reconstruct according to gating rule.
All or part of content in the technical scheme that above embodiment provides can be realized by software programming, and its software program is stored in the storage medium that can read, storage medium such as: the hard disk in computer, CD or floppy disk.
Note, above are only preferred embodiment of the present invention and institute's application technology principle.Skilled person in the art will appreciate that and the invention is not restricted to specific embodiment described here, various obvious change can be carried out for a person skilled in the art, readjust and substitute and can not protection scope of the present invention be departed from.Therefore, although be described in further detail invention has been by above embodiment, the present invention is not limited only to above embodiment, when not departing from the present invention's design, can also comprise other Equivalent embodiments more, and scope of the present invention is determined by appended right.
Claims (5)
1. an interleaving/deinterleaving device, is characterized in that comprising: the short delivery for the treatment of short interleave depth knits advanced treatment unit and the long interleave depth processing unit for the treatment of long interleave depth,
Described short delivery is knitted advanced treatment unit and is comprised short interleave depth interleaving block and short interleave depth de-interleaving block,
Described short interleave depth interleaving block comprises passage gating module, multiple short interleave depth interleaver and data reconstruction module, described passage gating module receives parallel input data, and parallel described input data is outputted to the multiple short interleave depth interleaver of gating according to interleave depth parameter; Multiple described short interleave depth interleaver completes, to after the intertexture of parallel described input data, interleaving data is outputted to described data reconstruction module, and described data reconstruction module exports after described interleaving data reconstruct according to described interleave depth parameter;
Described short interleave depth de-interleaving block comprises passage selected input module, data reorganization module, multiple short interleave depth deinterleaver and passage gating output module, described passage selected input module receives the interleaving data after reconstruct according to described interleave depth parameter selected input port, described data reorganization module receives the interleaving data after the reconstruct of the reception of described passage selected input module, and according to described interleave parameter, restructuring acquisition recombination data is carried out to the interleaving data after reconstruct, multiple described short interleave depth deinterleaver obtains described recombination data respectively and completes deinterleaving process, data strobe after deinterleaving exports by described passage gating output module,
Described long interleave depth processing unit comprises long interleave depth interleaving block and long interleave depth de-interleaving block;
Described long interleave depth interleaving block comprises address mapping data reconstructed module, multiple output buffer memory and exports gating module, described address mapping data reconstructed module receives parallel input data, and according to the address maps rule that described interleave depth parameter is determined, described parallel data is converted into mapping (enum) data output; Multiple described output buffer memory receives described mapping (enum) data, and is exported as interleaving data by described mapping (enum) data according to the gating signal that described output gating module produces; Described gating signal is determined according to described interleave depth parameter by described output gating module;
Described long interleave depth de-interleaving block comprises input port gating module, multiple input-buffer, address mapping module, reads enable signal generation module and address mapping data reconstructed module, described input port gating module according to described interleave depth parameter selected input port for receiving described interleaving data; Multiple described input-buffer receives described interleaving data from described input port gating module; Described enable signal generation module of reading produces and reads enable signal and by the corresponding described input-buffer of described address mapping module gating; The described input-buffer be strobed exports described interleaving data to described address mapping data reconstructed module; Described address mapping data reconstructed module exports after the described interleaving data reconstruct received as deinterleaved data.
2. interleaving/deinterleaving device as claimed in claim 1, it is characterized in that, also comprise: intertexture gating module, knitting advanced treatment unit or long interleave depth processing unit for exporting described input data to short delivery according to intertexture way, if described intertexture way is less than setting intertexture way, exports described input data to short delivery and knitting advanced treatment unit; If described intertexture way is greater than described setting intertexture way, then export described input data to long interleave depth processing unit.
3. interleaving/deinterleaving device as claimed in claim 1, it is characterized in that, described short interleave depth interleaver comprises multiple short delivery and knits input-buffer, short delivery knits address mapping module, first reads enable signal generation module and short delivery knits address mapping data reconstructed module, multiple described short delivery knits the described input data that input-buffer walks abreast for buffer memory, when the described input data that multiple described short delivery knits input-buffer are frame data, described first reads the generation of enable signal generation module reads enable signal, described short delivery knit address mapping module utilize according to address mapping ruler described in read enable signal the described input data of knitting in input-buffer export described short delivery to and knit address mapping data reconstructed module by described short delivery, described short delivery is knitted address mapping data reconstructed module and the described input data after restructuring is exported as interleaving data.
4. interleaving/deinterleaving device as claimed in claim 1, it is characterized in that, described short interleave depth deinterleaver comprises that short delivery knits serioparallel exchange module, short delivery knits address mapping module, multiple short delivery is knitted and exported buffer memory and second and read enable signal generation module, and described short delivery is knitted serioparallel exchange module and described recombination data parallel output to described short delivery is knitted address mapping module; Described short delivery is knitted address mapping module and is exported described recombination data to multiple described short delivery respectively according to address mapping ruler and knit output buffer memory; When multiple described short delivery described recombination data knitted in output buffer memory is frame data, described second reads enable signal generation module reads enable signal according to the generation of described address maps rule is multiple; Multiple described short delivery is knitted and is exported buffer memory and exported as deinterleaved data by described recombination data according to reading enable signal described in receiving.
5. an interleaving/deinterleaving coding method, is characterized in that comprising the following steps:
Judge intertexture way, if described intertexture way is less than setting intertexture way, then short interleaving treatment and short deinterleaving process are carried out to parallel input data; Otherwise long interleaving treatment and long deinterleaving process are carried out to parallel input data;
Described short delivery is knitted process and is comprised:
According to interleave depth parameter, parallel described input data are carried out short interleaving treatment respectively;
According to interleave depth parameter, the data after short interleaving treatment are reconstructed;
After reconstructing, data are as short delivery organization data parallel output;
Described short deinterleaving process comprises:
Receive according to the described short delivery organization data of described interleave depth parameter to parallel input;
According to interleave parameter, described short delivery organization data is recombinated;
Short deinterleaving process is carried out to the short delivery organization data after restructuring;
Data strobe after short deinterleaving is exported;
Described long interleaving treatment comprises:
Receive parallel input data;
Determine address mapping ruler according to interleave depth parameter, parallel upper described input data are converted to mapping (enum) data according to described address maps rule;
Described mapping (enum) data is carried out respectively interleaving treatment and generate interleaving data;
Described long deinterleaving process comprises:
According to described interleave depth parameter, selected input is carried out to described interleaving data;
Buffer memory is carried out to the described interleaving data of selected input;
The described interleaving data be buffered exports as deinterleaved data after carrying out exporting and reconstruct according to gating rule.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109495157A (en) * | 2018-11-15 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of full duplex high-throughput bidirectional ARQ communication system and method based on CCSDS agreement |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050111376A1 (en) * | 2003-11-21 | 2005-05-26 | Nokia Corporation | Flexible rate split method for MIMO transmission |
| CN101557272A (en) * | 2008-04-09 | 2009-10-14 | 展讯通信（上海）有限公司 | Method and device for interleaving high-order modulated HS-DSCH in TD-SCDMA system HSOPA |
| CN102142928A (en) * | 2010-11-19 | 2011-08-03 | 华为技术有限公司 | Methods for interleaving and deinterleaving external code coding output codons and interleaving and deinterleaving devices |
| CN103780341A (en) * | 2013-12-31 | 2014-05-07 | 上海无线通信研究中心 | Wireless communication transmission method based on parallel coding and parallel interleaving |
-
2014
- 2014-09-09 CN CN201410455441.0A patent/CN105119685B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050111376A1 (en) * | 2003-11-21 | 2005-05-26 | Nokia Corporation | Flexible rate split method for MIMO transmission |
| CN101557272A (en) * | 2008-04-09 | 2009-10-14 | 展讯通信（上海）有限公司 | Method and device for interleaving high-order modulated HS-DSCH in TD-SCDMA system HSOPA |
| CN102142928A (en) * | 2010-11-19 | 2011-08-03 | 华为技术有限公司 | Methods for interleaving and deinterleaving external code coding output codons and interleaving and deinterleaving devices |
| CN103780341A (en) * | 2013-12-31 | 2014-05-07 | 上海无线通信研究中心 | Wireless communication transmission method based on parallel coding and parallel interleaving |
Non-Patent Citations (1)
| Title |
|---|
| 黄卉 等: ""高速并行Turbo译码中的交织器技术研究"", 《通信技术》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109495157A (en) * | 2018-11-15 | 2019-03-19 | 西安空间无线电技术研究所 | A kind of full duplex high-throughput bidirectional ARQ communication system and method based on CCSDS agreement |
| CN109495157B (en) * | 2018-11-15 | 2021-09-03 | 西安空间无线电技术研究所 | Full-duplex high-throughput rate bidirectional ARQ communication system and method based on CCSDS protocol |
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