CN101388745B - Parallel channel decoding apparatus applied in radio multimedia sensor network - Google Patents
Parallel channel decoding apparatus applied in radio multimedia sensor network Download PDFInfo
- Publication number
- CN101388745B CN101388745B CN2008100599671A CN200810059967A CN101388745B CN 101388745 B CN101388745 B CN 101388745B CN 2008100599671 A CN2008100599671 A CN 2008100599671A CN 200810059967 A CN200810059967 A CN 200810059967A CN 101388745 B CN101388745 B CN 101388745B
- Authority
- CN
- China
- Prior art keywords
- parallel
- ram
- enable signal
- data
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Error Detection And Correction (AREA)
Abstract
The invention discloses a decoding device of a parallel communication channel which is applied to a radio multimedia sensing network and comprises a parallel de-interleaving machine, a zero inserting device, a parallel viterbi code converter and a serial-to-parallel converter, the idea of splitting serial data into two ways of parallel data for the decoding operation of the communication channel is adopted, compared with a decoding device of a traditional communication channel, under the same working timepiece condition, the throughput of data is improved by one time through a mode of adding the viterbi code converter by the decoding device of the communication channel of the invention, under the same data rate condition, the working timepiece of the decoding device of the communication channel of the invention can be reduced by half, according to the energy consumption calculating formula of an integrated circuit, the working energy consumption of the decoding device of the communication channel of the invention is only one-fourth percent of the traditional communication channel decoding device, and the problem of energy limitation of the radio multimedia sensing network can be effectively released.
Description
Technical field
The present invention relates to a kind of transmission node of the radio multimedia sensor network network based on OFDM (Orthogonal Frequency Division Multiplexing, OFDM) system, relate in particular to channel decoding device wherein.
Background technology
Along with the develop rapidly of the communication technology, embedded computing technique and sensor technology and increasingly mature, the wireless sensor node with perception, computing capability and communication capacity begins to occur, and has caused people's very big concern.This wireless sensor node constitutes various environment or the monitoring target information in wireless sense network perception in phase, collection and the processing network's coverage area, and is distributed to the user who needs these information.Wireless sense network merges information world in logic with real physical world, profoundly changed the interactive mode of man and nature; Can be widely used in numerous areas such as military affairs, industrial or agricultural control, biologic medical, environmental monitoring.
At present, an importance of sensor network research is on the serious limited miniature node of energy, how to realize simple environment data (like temperature, humidity, light intensity etc.) collection, transmission and processing.Yet; Increasingly sophisticated changeable along with monitoring of environmental; The simple data of being obtained by these traditional sensors networks can not satisfy the comprehensive demand of people to environmental monitoring further; Press for that medium such as amount of information abundant image, audio frequency, video are incorporated into the sensor network is the environmental monitoring activity on basis, realize the environmental monitoring of fine granularity, accurate information.Thus, multimedia sensor network arises at the historic moment.
In the laying environment of most wireless sensor node, all exist various noises, interference etc., the signal that transmits in the wireless channel is caused damage, reduce the performance of wireless communication system.Therefore; In wireless communication system; All need add channel coding device, the data that information source is provided encapsulate according to predetermined form, and add some redundant information; The channel code translator of receiving terminal can resist the damage that interference and noise etc. in the wireless channel cause effectively in the cooperation, from the signal of distortion, extracts proper data.
In existing multimedia sensor node, channel decoding device comprises deinterleaver, zero insertion device and Convolutional Decoder Assembly.Because the code stream that convolutional encoding obtains is to have very strong correlation, is exactly to utilize this correlation to correct the error code of some bursts in the code stream during decoding.When code stream suffers from the interference that continues the long period and noise; The error code that can cause longer sequence so that decoder can't recover, therefore need be provided with an interleaver behind convolution coder; The code stream of convolutional encoding is broken up, thereby disperseed long-term bit-error sequence.Accordingly, just need to add a deinterleaver at receiving terminal, the code stream that the interleaver of the end that is encoded is broken up is reorganized into orderly code stream.Deinterleaver essence is the predetermined register matrix of size, reads by row after code stream writes by row again.When realizing, construct this register matrix with a RAM usually, the address of coming compute codeword to write by a write address generator, and read the address that address generator comes compute codeword to read by one.At channel quality relatively preferably under the situation, can remove unnecessary redundant data in the code stream of convolution coder coding, change the code check of convolutional encoding, to improve the spectrum efficiency of system, therefore in encoder, be provided with a card punch.Just need a zero insertion device in decoder inside accordingly.The zero insertion device links to each other with deinterleaver, according to predetermined code check, selects the position of zero insertion, in the output code flow of deinterleaver, inserts zero, to recover the code stream of original code check.Convolutional Decoder Assembly links to each other with the zero insertion device, deciphers according to maximum-likelihood criterion usually, seek one group with the input code sequence apart from the code word of minimum as court verdict.Convolutional Decoder Assembly adopts the viterbi decoder to realize usually.Described viterbi decoder then is the structure according to the encoder for convolution codes of selecting for use; Distance metric value between sequence that calculating rules out and all possible sequence; It is minimum therefrom to select distance metric value again, and promptly the most similar with receiving sequence sequence is as the output of decoding.
In wireless multimedia sensor network, in order to support that to real-time video the transmission of voice etc. needs channel decoder can possess the higher data throughput.All be to realize in traditional sensor node through the work clock that improves decoder; This way needs decoder to be operated on the higher clock on the one hand; As everyone knows, square being directly proportional of energy consumption and work clock in integrated circuit, promptly this mode can cause bigger energy consumption; On the other hand, this mode needs the time-delay of strict constrained path when realizing, increase the difficulty in the design.
Summary of the invention
The object of the present invention is to provide a kind of parallel channel decoding apparatus that is applied to radio multimedia sensor network.What the present invention will solve is the channel encoder work clock problem of higher in the existing multimedia sensor node.In order to reach above-mentioned purpose, the present invention comprises at least: parallel deinterleaver, zero insertion device, parallel viterbi decoder, parallel to serial converter.
Described parallel deinterleaver comprises two onesize RAM, and the write address generator is read address generator.Construct the table that interweaves with RAM, the demodulation code stream of serial is write two RAM successively according to specific sequence of addresses, simultaneously two RAM are carried out read operation by reading address generator during output, obtain the parallel code stream of two-way.
The write address generator produces the enable signal of writing of an address of writing RAM and RAM according to the sequence number of enter code word and the tableau format that interweaves, and the highest order of writing address ram is used to generate the chip selection signal of two RAM.
Read address generator and produce the address of reading RAM according to reading the sequence number of code word and the sequence number of enter code word and the enable signal signal of reading that the zero insertion device provides.
The size of two RAM is confirmed that by the size of the selected table that interweaves the size of each RAM is the half the of table size that interweave.The figure place of each element of RAM has the figure place decision of demodulation result, they with the write address generator with read address generator and cooperate and realize that is imported an operation of reading by going by row.
Described zero insertion device is read the enable signal generator by two selectors and one and is formed.Read the enable signal generator and confirm the position of zero insertion, and provide the corresponding enable signal of reading according to predefined code check.Two selectors link to each other with constant zero with the two-way output code flow of parallel interleaver respectively, select output code flow or output constant zero by reading enable signal control.
Described parallel viterbi decoder is made up of same clock-driven viterbi decoder by two, respectively the two-way code stream is deciphered processing, the parallel judgement data sequence of output two-way.The viterbi decoder here is identical with viterbi decoder architecture in traditional channel decoder, just introduces no longer in detail here.
Described parallel to serial converter then will walk abreast the parallel judgement data sequence of the two-way of viterbi decoder output according to the information bit in the first via data sequence preceding, the information bit in the second circuit-switched data sequence after word order and be one the tunnel.
In the parallel channel decoding apparatus of the present invention at interleaver; Zero insertion device and convolutional code decoder device part all adopt the parallel mode of two-way to handle; Compare with traditional channel coding device; Under identical work clock condition, channel decoding device of the present invention is through increasing the mode of a viterbi decoding unit, and the throughput of data is doubled; Under the condition of identical data rate, the work clock of channel decoding device of the present invention can reduce half the, and according to the energy consumption calculation formula of integrated circuit, the work energy consumption of channel decoding device of the present invention has only 1/4 of traditional channel decoding device.
Description of drawings
Fig. 1 is existing channel decoding device structure chart.
Fig. 2 is the parallel channel decoding apparatus that is applied to multimedia sensing network of the present invention.
Fig. 3 is a parallel deinterleaver structure chart of the present invention.
Fig. 4 is parallel viterbi decoder architecture figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is described further.
Like Fig. 2, Fig. 3 and shown in Figure 4, the present invention includes parallel deinterleaver, zero insertion device, parallel viterbi decoder and parallel to serial converter.
Described parallel interleaver links to each other with demodulator, two onesize RAM, and the write address generator is read address generator.
The write address generator produces the address according to the sequence number of the code stream of input with the tableau format that interweaves, and provides simultaneously and write enable signal.The address highest order that the write address generator produces is used to produce the chip selection signal of two RAM, and all the other are as the write address of two RAM.The table that interweaves with N*M is an example, and the address ram of writing of generation is addr=i*N+j, 0≤i＜M wherein, and 0≤j＜N whenever reads a code word simultaneously, and the value of i adds 1, zero clearing again when i remembers M, the value of j adds 1 simultaneously.
Read address generator and controlled by the enable signal of reading of zero insertion device output, when reading the enable signal signal and be high level, the write address generator adds 1 with the address of output; When the data effective index signal was low level, the write address generator kept the address of output constant.
The size of two RAM is confirmed that by the size of the selected table that interweaves the size of each RAM is the half the of table size that interweave, and the figure place of each element of RAM has the figure place decision of demodulation result.In addition; The write address port of two RAM with write the enable signal port respectively with the writing address signal of write address generator output with write enable signal and link to each other; The write data port described zero insertion device that links to each other with the data of input comprises that two selectors and one read the enable signal generator, reads the enable signal generator and confirms the position of zero insertion according to predefined code check, and provide the corresponding enable signal of reading; High level is represented read data, and low level representes to insert zero; An input port of two selectors links to each other with the two-way code stream of deinterleaver output respectively, another input port input zero, and two selectors are all by reading enable signal control;
The address signal highest order of write address generator output directly links to each other with the chip selection signal input port of first RAM, links to each other with the chip selection signal input port of second RAM behind the door through non-simultaneously.Two RAM read address port with read the enable signal port respectively with read the address signal of reading that address generator provides and link to each other with the enable signal of reading that the zero insertion device provides.The parallel data flow of data-out port output two-way of two RAM.The write address generator with read under the Collaborative Control of address generator, two RAM realize parallel deinterleaving functions, will pass through the serial code stream that interweaves and revert to the parallel code stream of two-way before interweaving.
Described zero insertion device comprises that two selectors and one read the enable signal generator.Read the enable signal generator and confirm the position of zero insertion according to predefined code check; And provide the corresponding enable signal of reading; High level is represented read data, and low level is represented to insert zero, is used for controlling the rhythm of parallel deinterleaver data output and the data of two selector gatings in the zero insertion device.Two selectors correspond respectively to the two-way output of parallel deinterleaver, and two input ports of first selector link to each other with constant zero with the first via output of parallel deinterleaver respectively; Two input ports of corresponding second selector link to each other with constant zero with the second tunnel output of parallel deinterleaver respectively.Two selectors are all controlled by reading the enable signal generator, when to read enable signal be high, and first input port output of gating, otherwise then second input port output of gating.
Described parallel viterbi decoder is made up of same clock-driven viterbi decoder by two; Two viterbi decoders are continuous respectively at the output of two selectors; Handle carrying out viterbi decoding respectively, obtain the parallel judgement data sequence of two-way through the parallel code stream of the two-way behind the zero insertion.
Described parallel to serial converter links to each other with parallel viterbi decoder; The judgement data sequence that the two-way of parallel viterbi decoder output is parallel according to the information bit in the first via data sequence preceding, the information bit in the second circuit-switched data sequence after order and be that one tunnel judgement data sequence is as decoded output.
In the parallel channel decoding apparatus of the present invention in sum at interleaver; Zero insertion device and convolutional code decoder device part all adopt the parallel mode of two-way to handle; Compare with traditional channel coding device; Under identical work clock condition, channel decoding device of the present invention is through increasing the mode of a viterbi decoding unit, and the throughput of data is doubled; Under the condition of identical data rate; The work clock of channel decoding device of the present invention can reduce half the; Energy consumption calculation formula according to integrated circuit; The work energy consumption of channel decoding device of the present invention has only 1/4 of traditional channel decoding device, can effectively alleviate the problem of radio multimedia sensor network energy constraint.
Claims (4)
1. a parallel channel decoding apparatus that is applied to radio multimedia sensor network is characterized in that this device comprises: a parallel deinterleaver, a zero insertion device, a parallel viterbi decoder, a parallel to serial converter;
Described parallel deinterleaver comprises a write address generator, reads address generator and two RAM that size is identical for one; The write address generator produces a RAM writing address signal and a RAM writes enable signal; Read RAM of address generator generation and read address signal; Two RAM are used for making up the table that interweaves; Wherein the data-out port of two RAM is exported the parallel data flow of two-way;
Described zero insertion device comprises that two selectors and one read the enable signal generator, in through the code stream of punching, inserts zero, to recover the code stream sequence of original code check; Read one of enable signal generator generation and read enable signal; Selector is used for selecting output code word or constant zero; Wherein, two selectors correspond respectively to the two-way output of parallel deinterleaver;
Described parallel viterbi decoder comprises two viterbi decoders, to carrying out viterbi decoding through the parallel code stream of the two-way of zero insertion; Described parallel to serial converter is combined into one the tunnel with the judgement data of two viterbi decoder outputs, exports as decoded result.
2. a kind of parallel channel decoding apparatus that is applied to radio multimedia sensor network as claimed in claim 1 is characterized in that parallel deinterleaver comprises a write address generator, reads address generator and two RAM that size is identical for one; The write address generator produces a RAM writing address signal and a RAM writes enable signal; A RAM who reads the address generator generation reads address signal and reads enable signal to control two RAM simultaneously, and the data of two RAM outputs flow as the two-way parallel output data of parallel deinterleaver; Two RAM are used for making up the table that interweaves.
3. a kind of parallel channel decoding apparatus that is applied to radio multimedia sensor network as claimed in claim 1; It is characterized in that: described zero insertion device is read the enable signal generator by two selectors and one and is formed, and reads the enable signal generator and produces the data of reading two selector gatings of enable signal control according to the code check of selecting; Two selectors are handled the parallel code stream of the two-way of parallel deinterleaver output respectively, confirm gating code stream or constant zero according to the level of reading enable signal.
4. a kind of parallel channel decoding apparatus that is applied to radio multimedia sensor network as claimed in claim 1; It is characterized in that: described parallel viterbi decoder is made up of two viterbi decoders, and each decoder is deciphered two channel parallel datas through zero insertion separately.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100599671A CN101388745B (en) | 2008-03-05 | 2008-03-05 | Parallel channel decoding apparatus applied in radio multimedia sensor network |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100599671A CN101388745B (en) | 2008-03-05 | 2008-03-05 | Parallel channel decoding apparatus applied in radio multimedia sensor network |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101388745A CN101388745A (en) | 2009-03-18 |
| CN101388745B true CN101388745B (en) | 2012-11-07 |
Family
ID=40477944
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008100599671A Expired - Fee Related CN101388745B (en) | 2008-03-05 | 2008-03-05 | Parallel channel decoding apparatus applied in radio multimedia sensor network |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101388745B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102136879B (en) * | 2010-08-24 | 2013-04-24 | 华为技术有限公司 | Data de-interleaving method and device |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455565A (en) * | 2003-03-17 | 2003-11-12 | 西南交通大学 | Parallel Turbo coding-decoding method based on block processing for error control of digital communication |
| CN1812309A (en) * | 2006-02-20 | 2006-08-02 | 东南大学 | Parallel realizing method accepted by iterative detection decoding of wireless communication system |
-
2008
- 2008-03-05 CN CN2008100599671A patent/CN101388745B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1455565A (en) * | 2003-03-17 | 2003-11-12 | 西南交通大学 | Parallel Turbo coding-decoding method based on block processing for error control of digital communication |
| CN1812309A (en) * | 2006-02-20 | 2006-08-02 | 东南大学 | Parallel realizing method accepted by iterative detection decoding of wireless communication system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101388745A (en) | 2009-03-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106230489B (en) | Polarization code encoding modulation method suitable for any high order modulation | |
| CN101087181B (en) | A method for removing interweaving and speed match | |
| CN101425871B (en) | Multi-element error correcting code transmitting and receiving apparatus, data communication system and related method | |
| CN104618068B (en) | Bit Interleaved Coded Modulation device and method for wireless broadcast communication system | |
| CN101232289A (en) | Method of decoding turbine coding signal and turbine decoder | |
| CN101986584A (en) | Rate de-matching device and method in 3GPP LTE | |
| CN101286816B (en) | Parallel channel encoding apparatus applicable in multimedia sensor network | |
| CN101969311B (en) | High-speed parallel segmented staggering Viterbi decoding method | |
| CN103023603B (en) | Method for realizing bit-interleaved coded modulation based on low-density parity-check (LDPC) matrix | |
| CN104486033B (en) | A kind of descending multimode channel coded system and method based on C RAN platforms | |
| CN101388745B (en) | Parallel channel decoding apparatus applied in radio multimedia sensor network | |
| CN103986557A (en) | LTE Turbo code parallel block decoding method with low path delay | |
| CN101488833B (en) | Uplink channel encoding method and downlink channel decoding method for TD-SCDMA system | |
| CN101404555A (en) | Convolution interleaving/de-interleaving method in digital transmission | |
| CN1638293B (en) | Communication method and communication terminal equipment, receiving and transmitting-receiving method | |
| CN101399633B (en) | Interference resisting method combining Reed-Solomon code with grid coding modulation technique | |
| CN102361460B (en) | General high speed parallel cycle interleaving Viterbi decoding method | |
| CN101192836A (en) | Interweaver and encoder/decoder and interweaving realization method | |
| CN105450344A (en) | LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method | |
| Peter et al. | Optimizing Building Management Systems with DNC-Aided SCL-Flip Decoding of Polar Codes | |
| CN105356965A (en) | LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method | |
| CN105450338A (en) | LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method | |
| CN105376025A (en) | Interleaving and mapping method and de-interleaving and de-mapping method of LDPC code word | |
| CN101414836A (en) | Processing method and apparatus for convolution topological encode | |
| CN105450340A (en) | LDPC codeword interleaving and mapping method and de-interleaving and de-mapping method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| ASS | Succession or assignment of patent right |
Owner name: CAS JIAXING WIRELESS SENSOR NETWORK ENGINEERING CE Free format text: FORMER OWNER: CAS JIAXING CENTER MICROSYSTEMS INTITUTE BRANCH CENTER Effective date: 20100129 |
|
| C41 | Transfer of patent application or patent right or utility model | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20100129 Address after: 2, building 1, No. 778 Asia Pacific Road, Nanhu District, Zhejiang, Jiaxing Province, China: 314000 Applicant after: Jiaxing Wireless Sensor Network Engineering Center, Chinese Academy of Sciences Address before: A, building four, block JRC, Asia Pacific Road, Nanhu District, Zhejiang City, Jiaxing Province, China: 314000 Applicant before: Microsystem Inst. Branch Center, Jiaxing Center, CAS |
|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20121107 Termination date: 20180305 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |