CN102098126B - Interleaving device, rating matching device and device used for block coding - Google Patents
Interleaving device, rating matching device and device used for block coding Download PDFInfo
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- CN102098126B CN102098126B CN200910201155.0A CN200910201155A CN102098126B CN 102098126 B CN102098126 B CN 102098126B CN 200910201155 A CN200910201155 A CN 200910201155A CN 102098126 B CN102098126 B CN 102098126B
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Abstract
The invention provides a scheme for improving baseband processing capacity through parallel access by using a plurality of memories. The scheme comprises an interleaving device, a rate matching method and a rate matching device used for block coding. The invention provides an interleaving device (9) which is used for interleaving information blocks and comprises buffer memories (10), a write address generating device (20) and a read address generating device (30), wherein the buffer memories (10) comprise 2a random access memories of which the input bit width is 2b bits and the output bit width is 1 bit; the write address generating device (20) is used for generating write addresses of the buffer memories in turn, wherein the write addresses comprise a bits used for addressing the 2a random access memories; the read address generating device is used for generating read addresses of the 2a random access memories according to a predetermined interleaving rule; and 1-bit data is read from the 2a random access memories respectively for one read address, wherein the a and the b are both positive integers. By using the technical scheme, the data throughput for rate matching can be improved greatly.
Description
Technical field
The present invention relates to the communication technology, relate in particular to speed matching method and device thereof for block coding.
Background technology
The object of long-term project evolution (LTE) is to provide than the higher message transmission rate of the 3rd third-generation mobile communication technology and less delay.Have benefited from the development of wireless communication technology (for example self adaptation MIMO technique), LTE version 8 is the downlink data rate of the highest 300Mbps, and the time delay of user level is lower than 5 milliseconds.After, LTE senior (LTE_A) system also can be supported the downlink data rate up to 1Gbps.Without doubt, these specification requirements will make the design of LTE enode b more difficult.The processing stage of LTE downlink physical layer, by carrying out rate-matched, process the output of turbo encoder to be adapted to desired code rate to help mixed automatic retransfer request (HARQ) to process.
As shown in Figure 1, in 3GPP agreement TS 36.212, rate-matched is defined as every encoding block and carries out, and comprising: three message bit stream d to the output of turbo coding
k (0)(systematic bits stream), d
k (1)(first via check bit stream), d
k (2)(second road check bit stream) carries out sub-block interleaving treatment, carries out bit collection after interweaving, generating virtual circular buffering pond then, then carry out after bit selection and punching process, send the output bit of each encoding block.
Consider the requirement of cost and reliability, the system clock of ripe and stable commercial digital processing chip is usually less than 500MHz at present.Obviously, in 2nd generation and the 3rd Generation Mobile Communication System, based on traditional bit-level treatment technology of Digital Signal Processing, be difficult to adapt to the requirement of LTE system.
Summary of the invention
In order to solve the above-mentioned problems in the prior art, the invention provides by a plurality of random access memory parallel accesses to improve the scheme of Base-Band Processing ability.
According to an aspect of the present invention, provide a kind of buffer storage for access information piece, comprised 2
aindividual input bit wide is 2
bbit, output bit wide be the random access memory of 1 bit, in writing address, adopt a bit to this 2
aindividual random access memory carries out addressing, to one, reads address respectively from 2
ain individual random access memory, respectively read 1 Bit data, thereby make this buffer storage realize per clock cycle 2
bthe writing speed of bit and per clock cycle 2
athe reading speed of bit, wherein a, b are positive integer.
Alternatively, in above-mentioned buffer storage, the value of b is one of 1 to 4, and the value of a is less than b or equals b.
According to a further aspect in the invention, provide a kind of interlaced device interweaving for block of information, having comprised: buffer storage, it comprises 2
aindividual input bit wide is 2
bbit, output bit wide are the random access memory of 1 bit; Writing address generating apparatus, generates the writing address of described buffer storage for order, and said write address comprises that a bit is for to described 2
aindividual random access memory carries out addressing; Read address generating device, for generate described 2 according to predetermined interleaving rule
aindividual random access memory read address; For one, read address respectively from described 2
ain individual random access memory, respectively read 1 Bit data, wherein a, b are positive integer.
Alternatively, the predetermined interleaving rule adopting in above-mentioned interlaced device comprises that columns is the interleaver matrix of 2 integral number power.
According to a further aspect in the invention, provide a kind of to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out the rate matching apparatus of rate-matched, comprising: the first buffer storage, its input bit wide is 2
nbit, for access system bit stream, wherein n is positive integer; The second buffer storage, its input bit wide is 2
nbit, for access one road check bit stream; The 3rd buffer storage, its input bit wide is 2
nbit, for another road check bit stream of access; Writing address generating apparatus, for generating the first buffer storage, the second buffer storage, the 3rd buffer storage writing address separately; Read address generating device, for according to predetermined interleaving rule, generate the first buffer storage, the second buffer memory, the 3rd buffer storage separately read address; Bit choice device, reads 2 for reading address according to one of the first buffer storage
nbit data, or according to one of the second buffer storage and the 3rd buffer storage, read address and read respectively 2
n-1bit data.
According to another aspect of the present invention, provide a kind of to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out the method for rate-matched, comprises the following steps: it is 2 that A. stores systematic bits stream into an input bit wide
nthe first buffer storage of bit, storing respectively two-way check bit stream into input bit wide is 2
nthe second buffer storage of bit and the 3rd buffer storage, wherein n is positive integer; B. according to one of the first buffer storage, read address and read 2
nbit data, or according to one of the second buffer storage and the 3rd buffer storage, read address and read respectively 2
n-1bit data.
Use buffer storage, interlaced device, speed matching method and device in the present invention, can realize per clock cycle many bit parallels read/write, thereby improve widely the data throughput of rate-matched.
Accompanying drawing explanation
With reference to figure and explanation below, will understand better this system.Element in figure is not necessarily drawn in proportion, but emphasis is for illustrating the principle of typical model.In the drawings, run through different diagrams, similarly reference number represents characteristic of correspondence.
Fig. 1 show of the prior art to Turbo coding output carry out the system block diagram of rate-matched;
Fig. 2 shows the structured flowchart of interlaced device according to an embodiment of the invention;
Fig. 3 shows the structured flowchart of interlaced device according to another embodiment of the invention;
Fig. 4 show one embodiment of the present of invention to comprising that the Turbo of a road systematic bits stream and the two-way check bit stream output block of encoding carries out the method flow diagram of rate-matched;
Fig. 5 shows according to an embodiment of the invention to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out the structured flowchart of the rate matching apparatus of rate-matched;
The structure in the virtual circular buffering pond of the rate-matched of Fig. 6 in showing according to one embodiment of present invention in processing;
Fig. 7 shows the structured flowchart of rate matching apparatus according to another embodiment of the invention.
Embodiment
In 3GPP agreement TS 36.212, the sub-block that each road output of Turbo coding is carried out interweaves and carries out as follows: from first trip, first, bit stream is write line by line to the interleaver matrix of one 32 row, then each row are rearranged, between row, resetting pattern is < 0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31 >, then to the sense data by column of the matrix after resetting.
In above-mentioned interlacing rule, the order of arbitrary column data does not change, and is suitable for parallel read-out.
According to one embodiment of present invention, provide a kind of interlaced device interweaving for block of information, having comprised: buffer storage, it comprises 2
aindividual input bit wide is 2
bbit, output bit wide are the random access memory of 1 bit; Writing address generating apparatus, for sequentially generating the writing address of described buffer storage, is used for described 2 comprising a bit
aindividual random access memory carries out addressing; Read address generating device, for generate described 2 according to predetermined interleaving rule
aindividual random access memory read address; For one, read address respectively from described 2
ain individual random access memory, respectively read 1 Bit data, wherein a, b are positive integer.
Alternatively, the predetermined interleaving rule adopting in above-mentioned interlaced device comprises that columns is the interleaver matrix of 2 integral number power.
Buffer storage in above-mentioned interlaced device is for block of information described in access, and it can realize per clock cycle 2
bthe writing speed of bit and per clock cycle 2
athe reading speed of bit.In this buffer storage 2
aindividual random access memory has identical structure.Because adopt a bit to 2 in binary system writing address
aindividual random access memory carries out addressing, and all input data are distributed and store 2 into
ain individual random access memory.Select suitably the position of described a bit in affiliated writing address, can be so that be stored in different random access memory corresponding to the data of interleaver matrix adjacent lines.
For example, the equal value of a, b is 2.Fig. 2 shows the structured flowchart of interlaced device according to an embodiment of the invention.As shown in the figure, interlaced device 9 comprises buffer storage 10, writing address generating apparatus 20, reads address generating device 30.The predetermined interleaving rule adopting in interlaced device 9 comprises that columns is 32 interleaver matrix, and for example between above-mentioned row, resetting pattern is < 0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15, the interleaver matrix of 31 >.
Writing address generating apparatus 20 is for sequentially generating the writing address of buffer storage 10.For example, the input port of random access memory 101 to 104 is 4 * 512, output port is 1 * 2048.Buffer storage 10 has 2048 writing address, needs the 0th to the 10th, totally 11 binary address positions, and wherein the 3rd and the 4th are for carrying out addressing to these four random access memory.Input block will be according to writing address by write buffering memory 10 sequentially.
Particularly, buffer storage 10 also comprises that has two gating switches 109 of controlling address, four output branch roads, for realizing the addressing to random access memory 101 to 104, the control address of gating switch 109 is the 3rd and the 4th of writing address.For example, the corresponding address 00,01,10,11 of controlling of random access memory 101 to 104 difference.In all input bits, (128 * i) bit to the (128 * i+31) bit will deposit random access memory 101 in, (128 * i+32) bit to the (128 * i+63) bit will deposit random access memory 102 in, (128 * i+64) bit to the (128 * i+95) bit will deposit random access memory 103 in, (128 * i+96) bit to the (128 * i+127) bit will deposit random access memory 104 in, and wherein i is nonnegative integer.In other words, data corresponding to (4 * i) row in interleaver matrix are stored into random access memory 101, data corresponding to (4 * i+1) row in interleaver matrix are stored into random access memory 102, data corresponding to (4 * i+2) row in interleaver matrix are stored into random access memory 103, and the data of going corresponding to (4 * i+3) in interleaver matrix are stored into random access memory 104.Because four random access memory have identical structure, so write respectively the identical address of four random access memory corresponding to (4 * j) to (4 * j+3) bit of a certain row of interleaver matrix, wherein j is nonnegative integer; , when sense data, this 4 Bit data can be read according to the same address of reading simultaneously.
Read address generating device 30 for generating and read address according to the order of aforementioned predetermined interleaving rule.For each, read address, from random access memory 101 to 104, respectively read out respectively 1 Bit data.The data that read out storage in random access memory 101 to 104 according to the order of reading address, can realize interweaving to input block easily.Because the structure of four random access memory is the same, so the integral multiple that the bit number of reading from this buffer storage is 4.Because input data may not be the integral multiple of 4 bits, so may there are some invalid datas in sense data, these invalid datas should be dropped in subsequent operation.
Like this, buffer storage 10 just can realize writing speed and the reading speed of per clock cycle 4 bit.When system clock is 250MHz, buffer storage 10 and interlaced device 9 can provide the disposal ability up to 1Gbps, and such disposal ability can meet the requirement of LTE system.
Again for example, the equal value of a, b is 3.The predetermined interleaving rule adopting in interlaced device comprises that columns is 32 interleaver matrix.Buffer storage comprises that eight input bit wides are that 8 bits, output bit wide are the random access memory of 1 bit.Writing address generating apparatus is used for generating writing address.For example, the input port of eight random access memory is 4 * 256, output port is 1 * 1024.Buffer storage has 2048 writing address, needs the 0th to the 10th, totally 11 binary address positions, and wherein the 3rd to the 5th for carrying out addressing to these eight random access memory.Input block will be according to writing address by write buffering memory sequentially.Particularly, buffer storage also comprises that has three gating switches of controlling address, eight output branch roads, and for realizing the addressing to eight random access memory, the control address of this gating switch is the 3rd to 5 of writing address.In all input bits, data corresponding to (8 * i) row in interleaver matrix are stored into first random access memory, by that analogy, the data of going corresponding to (8 * i+7) in interleaver matrix are stored into the 8th random access memory, and wherein i is nonnegative integer.Because eight random access memory have identical structure, so write respectively the memory space of an identical address of eight random access memory corresponding to (8 * j) to (8 * j+7) bit of a certain row of interleaver matrix, wherein j is nonnegative integer; , when sense data, this 8 Bit data can be read according to the same address of reading simultaneously.Conventionally, reading address generates according to resetting pattern between the row of above-mentioned interlacing rule by reading address generating device.According to the order of reading address, read out the data of storing in eight random access memory, can realize easily interweaving to input block.Because the structure of eight random access memory is the same, so the integral multiple that the bit number of reading from this buffer storage is 8.Because input data may not be the integral multiple of 8 bits, so may there are some invalid datas in sense data, these invalid datas should be dropped in subsequent operation.Like this, this buffer storage just can realize writing speed and the reading speed of per clock cycle 8 bit.
Again for example, a value is that 1, b value is 2.Fig. 3 shows the structured flowchart of interlaced device according to another embodiment of the invention.As shown in the figure, interlaced device 9 ' comprises buffer storage 10 ', writing address generating apparatus 20 ', reads address generating device 30 '.The predetermined interleaving rule adopting in interlaced device 9 ' comprises that columns is 32 interleaver matrix.
Buffer storage 10 ' comprises that two input bit wides are that 4 bits, output bit wide are the random access memory 101 ' and 102 ' of 1 bit, and these two random access memory have identical structure.
Writing address generating apparatus 20 ' is for sequentially generating the writing address of buffer storage 10 '.For example, the input port of two random access memory is 4 * 1024, output port is 1 * 4096.Buffer storage 10 ' has 2048 writing address, needs the 0th to the 10th, totally 11 binary address positions, and wherein the 3rd for carrying out addressing to these two random access memory.Input block will be according to writing address by write buffering memory 10 ' sequentially.
Particularly, buffer storage 10 ' also comprises that has a gating switch 109 ' of controlling address, two output branch roads, for realizing the addressing to random access memory 101 ' or 102 ', the control address of gating switch 109 ' is the 3rd of writing address.In all input bits, data corresponding to (2 * i) row in interleaver matrix are stored into random access memory 101 ', data corresponding to (2 * i+1) row in interleaver matrix are stored into random access memory 102 ', and wherein i is nonnegative integer.Because two random access memory have identical structure, so write respectively the memory space of an identical address of two random access memory corresponding to (2 * j) to (2 * j+1) bit of a certain row of interleaver matrix, wherein j is nonnegative integer; , when sense data, this 2 Bit data can be read according to the same address of reading simultaneously.
Read address generating device 30 ' for generating and read address according to the order of aforementioned predetermined interleaving rule.For each, read address, from random access memory 101 ' and 102 ', respectively read out respectively 1 Bit data.The data that read out storage in random access memory 101 ' and 102 ' according to the order of reading address, can realize interweaving to input block easily.
Like this, buffer storage 10 ' just can realize the reading speed of writing speed and the bit of per clock cycle 2 of per clock cycle 4 bit.
At the predetermined interleaving rule of above-mentioned employing, comprise that columns is in the interlaced device of 32 interleaver matrix, the value of a, b is generally one of 1 to 4.For input, the output speed of buffer storage are matched, a, b can get identical value.Certainly, a value also can be greater than b or be less than b.
The interlaced device with said structure can be for to block information, Turbo coding output block for example, interweave.Buffer storage wherein can be for access block shape information, for example turbo coding output block.The interlacing rule that wherein adopted is not limited to the interleaver matrix of 32 row, also can comprise that columns is the interleaver matrix of other 2 integral number power, and for example 16,64.When the columns of interleaver matrix be other 2 integral number power, the span of a, b correspondingly changes, and in writing address, for 2a random access memory being carried out to the position of a bit of addressing, also correspondingly changes.Adopt interlaced device and the buffer storage of this spline structure, can be so that the processing speed of block coding output block increases exponentially.
There is interlacing rule that the interlaced device of said structure adopts and also can comprise the not interleaver matrix of 2 integral number power of columns.For example, the interleaver matrix that is 29 for columns can be filled 3 bits between every 29 input data bits, then writes above-mentioned buffer storage, to guarantee being stored in different random access memory corresponding to the data of interleaver matrix adjacent lines.According to interlacing rule, generation after reading sequence of addresses sense data needs these filling bits to delete.
Fig. 4 shows according to an embodiment of the invention to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out the method flow diagram of rate-matched.As shown in the figure, the method comprises two step S1 and S2.
In step S1, storing systematic bits stream into an input bit wide is 2
nthe first buffer storage of bit, storing respectively two-way check bit stream into input bit wide is 2
nthe second buffer storage of bit and the 3rd buffer storage, wherein n is positive integer.
In step S2, according to one of the first buffer storage, read address and read 2
nbit data, or according to one of the second buffer storage and the 3rd buffer storage, read address and read respectively 2
n-1bit data.
Fig. 5 shows according to an embodiment of the invention to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out the structured flowchart of the rate matching apparatus of rate-matched.Below with reference to Fig. 4, Fig. 5, be illustrated.
As shown in Figure 5, rate matching apparatus 8 comprises the first buffer storage 11, the second buffer storage 12, the 3rd buffer storage 13, writing address generating apparatus 21, reads address generating device 31, bit choice device 40.
The first buffer storage 11 is for access system bit stream, and the second buffer storage 12 is for access one road check bit stream, and the 3rd buffer storage 13 is for another road check bit stream of access, and their input bit wide is 2
nbit.
Writing address generating apparatus 21 is for generating the first buffer storage 11, the second buffer storage 12, the 3rd buffer storage 13 writing address separately.
Read address generating device 31 for according to predetermined interleaving rule, generate the first buffer storage, the second buffer memory, the 3rd buffer storage separately read address.
Conventionally, writing address maker 21 sequentially generates respectively the writing address of each buffer storage.In abovementioned steps S1, systematic bits stream will be write according to the writing address being generated in the first buffer storage 11, one road check bit stream will be write according to the writing address being generated in the second buffer storage 12, and another road check bit stream will be write in the 3rd buffer storage 13 according to the writing address being generated.
Particularly, the predetermined interleaving rule here comprises that between aforementioned row, resetting pattern is < 0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7, the interleaver matrix of 23,15,31 >.Read address generating device 31 by according to the address of reading of resetting pattern between these row and generate respectively each buffer storage.
Step S2 is carried out by bit choice device 40.Fig. 6 shows the structure in the virtual circular buffering pond in the rate-matched processing in this embodiment.As shown in the figure, the total data of reading from the first buffer storage 11 is through the system information of interleaving treatment, and the total data of reading from the second buffer storage 12 and the 3rd buffer storage 13 is through interleaving treatment and staggered check information.Bit choice device 40 will determine which informational needs carries out subsequent treatment according to some system parameterss, and these system parameterss comprise code check and/or the HARQ relevant parameters of rate-matched.For example, the code check of rate-matched is 1/3, and all data messages in virtual buffer pond all need to carry out subsequent treatment.
According to one embodiment of present invention, above-mentioned rate matching apparatus 8 adopts programmable gate arrays to realize.
According to a specific embodiment of the present invention, in above-mentioned rate matching apparatus 8, the first buffer storage 11 has and the similar structure of buffer storage shown in Fig. 2 10, and the second buffer storage 12, the 3rd buffer storage 13 has and the similar structure of buffer storage shown in Fig. 3 10 '.Wherein, writing address generating apparatus 20 and 20 ' function merge in writing address generating apparatus 21, and the function of reading address generating device 30 and 30 ' merges to reads in address generating device 31.
The first buffer storage 11 comprises 2
nindividual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit.In this embodiment, the value of n is 2.These four random access memory have identical structure, and for example, input port is 4 * 512, output port is 1 * 2048.The first buffer storage 11 has 2048 writing address, needs the 0th to the 10th, totally 11 binary address positions.This writing address is generated by writing address generating apparatus 21, and wherein the 3rd and the 4th are for carrying out addressing to these four random access memory.In abovementioned steps S1, systematic bits stream is written in the process of the first buffer storage 11, because the effect of these two addressing address bits, corresponding to the data of interleaver matrix adjacent lines, is stored in different random access memory.
The second buffer storage 12, the 3rd buffer storage 13 respectively comprise 2
n-1individual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit.These four random access memory have identical structure, and for example, input port is 4 * 1024, output port is 1 * 4096.The second buffer storage 12, the 3rd buffer storage 13 have respectively 2048 writing address, need the 0th to the 10th, totally 11 binary address positions.The writing address of the second buffer storage 12 is generated by writing address generating apparatus 21, and wherein the 3rd for carrying out addressing to two random access memory.In abovementioned steps S1, first via check bit stream will write in the process of the second buffer storage 12, because the effect of this addressing address bit, corresponding to the data of interleaver matrix adjacent lines, is stored in different random access memory.The writing address of the 3rd buffer storage 13 is generated by writing address generating apparatus 21, and wherein the 3rd for carrying out addressing to two random access memory.In abovementioned steps S1, check bit stream in another road will be written in the process of the 3rd buffer storage 13, because the effect of this addressing address bit, corresponding to the data of interleaver matrix adjacent lines, is stored in different random access memory.
According to one embodiment of present invention, rate matching apparatus 8 also comprises: the 4th buffer storage, the 5th buffer storage, the 6th buffer storage.Wherein, the 4th buffer storage and the first buffer storage 11 form table tennis access mode, and the 5th buffer storage and the second buffer storage 12 form table tennis access mode, and the 6th buffer storage and the 3rd buffer storage 13 form table tennis access mode.Namely, when in the first buffer storage 11, the second buffer storage 12, the 3rd buffer storage 13, the data of storage are read out, another Turbo coding output block can be written into the 4th buffer storage, the 5th buffer storage, the 6th buffer storage; Vice versa.Like this, the processing speed of rate matching apparatus 8 greatly improves, and the stand-by period greatly reduces.
As previously mentioned, each clock cycle, bit choice device 40 will read 2 from each buffer storage
nbit data, wherein may comprise invalid bit (null bit), the filling bit for example adding (filler bit) and/or by the mute bit producing in the process of data write buffering memory (dummy bit) in code block segmentation process.For the system information of reading from the first buffer storage 11 and the first via check information read from the second buffer storage 12, filling bit wherein and mute bit need to abandon in subsequent treatment.For the second road check information of reading from the 3rd buffer storage 13, mute bit wherein need to abandon in subsequent treatment.
According to one embodiment of present invention, speed matching method also comprises two step S31 and S32 (not shown) after step S1 and S2.Fig. 7 shows according to the structured flowchart of the rate matching apparatus of this embodiment.As shown in the figure, rate matching apparatus 8 also comprises a perforating device 50, and it comprises a pretreatment unit 51 and one 2
nthe register 52 of position.In this embodiment, the value of n is 2.
In step S31, by read in step S2 2
nbit data carries out preliminary treatment, and invalid bit permutation is wherein arrived to high significance bit or low order.This step is carried out by pretreatment unit 51.Preferably, invalid bit will be displaced to low order.For example, have 2 bit invalid datas in 4 Bit datas that bit choice device 40 reads simultaneously, pretreatment unit 51 is replaced the 0th and the 1st in 4 bits by this 2 Bit data.
Through after the processing of pretreatment unit 51, the efficiency of rate matching apparatus 8 output valid data will be improved.
Those skilled in the art will be understood that, before step S31, the step that also should comprise an invalid bit of identification, a Bit data of reading from a certain buffer whether valid data can generate the rule of writing address and read address generating device 31 according to writing address generating apparatus 21 and generates the rule of reading address and determined.4 Bit datas that bit choice device 40 is read at every turn can be labelled by a flag respectively.For example, significant bit is identified as 1, and invalid bit is identified as 0.
In step S32, after pretreatment 2
nsignificant bit in Bit data will be stored in register 52, and after register 52 is filled with output data.For example, through first group of 4 Bit data after preliminary treatment, be significant bit, these 4 bit valid data will be stored into register 52 and be exported by register 52; Through second group of 4 Bit data after preliminary treatment, comprise 3 significant bits, these three significant bits in high significance bit will be stored into register 52; Through the 3rd group of 4 Bit datas after preliminary treatment, comprise two significant bits, in these two significant bits will be stored into register 52 and export with together with first three significant bit in register 52, and then another in these two significant bits will be stored into register 52; Other each groups will be carried out similar processing through pretreated 4 Bit datas.
In this embodiment, rate matching apparatus 8 receives from Turbo coding module output San road bit stream, and the input speed on each road is per clock cycle 4 bit; After completing rate-matched processing, output speed is per clock cycle 4 bit.When system clock is 250MHz, this rate matching apparatus 8 can provide the disposal ability up to 1Gbps, and such disposal ability can meet the requirement of LTE system.
In above-mentioned speed matching method and device, the value that the columns of interleaver matrix is 32, n is 2.Those skilled in the art will be understood that n can also be taken as other values in some other embodiment of speed matching method of the present invention and device, for example 1,3,4.When n value is 4, rate matching apparatus can provide the data-handling capacity of per clock cycle 16 bit.Under existence conditions, for other functional modules in system under rate matching apparatus, such data-handling capacity is enough.
Those skilled in the art will be understood that device alleged in the present invention can be realized by software function module, also can be realized by hardware module, or realize by the combination of software and hardware.Preferably, in the present invention, alleged device is realized with programmable gate array.
Those skilled in the art will be understood that above-described embodiment is all exemplary and nonrestrictive.The different technologies feature occurring in different embodiment can combine, to obtain beneficial effect.Those skilled in the art, on the basis of research accompanying drawing, specification and claims, will be understood that and realize the embodiment of other variations of disclosed embodiment.In claims, term " comprises " does not get rid of other devices or step; Indefinite article " one " is not got rid of a plurality of; Term " first ", " second " are for indicating title but not for representing any specific order.Any Reference numeral in claim all should not be understood to the restriction to protection range.The function of a plurality of parts that occur in claim can be realized by an independent hardware or software module.Some technical characterictic appears in different dependent claims and does not mean that and these technical characterictics can not be combined to obtain beneficial effect.
Claims (13)
1. for a buffer storage for access information piece, comprise 2
aindividual input bit wide is 2
bbit, output bit wide be the random access memory of 1 bit, in writing address, adopt a bit to this 2
aindividual random access memory carries out addressing, to one, reads address respectively from 2
ain individual random access memory, respectively read 1 Bit data, thereby make this buffer storage realize per clock cycle 2
bthe writing speed of bit and per clock cycle 2
athe reading speed of bit, wherein a, b are positive integer.
2. buffer storage according to claim 1, is characterized in that, the value of b is one of 1 to 4, and the value of a is less than or equal to b.
3. to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out a rate matching apparatus for rate-matched, comprising:
The first buffer storage, for access system bit stream, input bit wide is 2
nbit, wherein n is positive integer;
The second buffer storage, for access one road check bit stream, input bit wide is 2
nbit;
The 3rd buffer storage, for another road check bit stream of access, input bit wide is 2
nbit;
Writing address generating apparatus, for generating the first buffer storage, the second buffer storage, the 3rd buffer storage writing address separately;
Read address generating device, for according to predetermined interleaving rule, generate the first buffer storage, the second buffer memory, the 3rd buffer storage separately read address;
Bit choice device, reads 2 for reading address according to one of the first buffer storage
nbit data, or according to one of the second buffer storage and the 3rd buffer storage, read address and read respectively 2
n-1bit data;
Wherein:
The first buffer storage comprises 2
nindividual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit;
The second buffer storage, the 3rd buffer storage comprise respectively 2
n-1individual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit;
Said write address generating device in the writing address of the first buffer storage, adopt n bit to its 2
nindividual random access memory carries out addressing, in the writing address of the second buffer storage, the 3rd buffer storage, adopt n-1 bit respectively to its separately 2
n-1individual random access memory carries out addressing;
Described bit choice device for according to described in the first buffer storage, read address respectively from its 2
nindividual random access memory respectively reads 1 Bit data, or according to described in the second buffer storage and the 3rd buffer storage, read address respectively from separately 2
n-1individual random access memory respectively reads 1 Bit data.
4. rate matching apparatus according to claim 3, is characterized in that, the value of n is one of 1 to 4.
5. rate matching apparatus according to claim 3, is characterized in that, described rate matching apparatus also comprises:
The 4th buffer storage, forms table tennis access mode with the first buffer storage;
The 5th buffer storage, forms table tennis access mode with the second buffer storage;
The 6th buffer storage, forms table tennis access mode with the 3rd buffer storage.
6. rate matching apparatus according to claim 3, is characterized in that, described rate matching apparatus also comprises perforating device, and this perforating device comprises:
Pretreatment unit, for bit choice device is read 2
ninvalid bit permutation in Bit data is to highest significant position or least significant bit; And
2
nthe register of position, for storing after pretreatment 2
nsignificant bit in Bit data, and after register is filled with output data.
7. according to the rate matching apparatus described in any one in claim 3 to 6, it is characterized in that, described rate matching apparatus is realized by field programmable gate array.
8. to comprising that the Turbo coding output block of a road systematic bits stream and two-way check bit stream carries out a method for rate-matched, comprises the following steps:
A. systematic bits stream being stored into an input bit wide is 2
nthe first buffer storage of bit, storing respectively two-way check bit stream into input bit wide is 2
nthe second buffer storage of bit and the 3rd buffer storage, wherein n is positive integer;
B. according to one of the first buffer storage, read address and read 2
nbit data, or according to one of the second buffer storage and the 3rd buffer storage, read address and read respectively 2
n-1bit data;
Wherein,
The first buffer storage comprises 2
nindividual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit, and the second buffer storage, the 3rd buffer storage comprise respectively 2
n-1individual input bit wide is 2
nbit, output bit wide are the random access memory of 1 bit;
In described steps A, when data are write to the first buffer storage, in writing address, adopt n bit to its 2
nindividual random access memory carries out addressing, when data are write to the second buffer storage, the 3rd buffer storage, in writing address, adopt n-1 bit respectively to its separately 2
n-1individual random access memory carries out addressing;
In described step B, during from the first buffer storage reading out data, according to described read address respectively from its 2
nindividual random access memory respectively reads 1 Bit data; During from the second buffer storage and the 3rd buffer storage reading out data, according to described read address respectively from its separately 2
n-1individual random access memory respectively reads 1 Bit data.
9. method according to claim 8, is characterized in that, the value of n is one of 1 to 4.
10. method according to claim 8, is characterized in that, also comprises step:
C1. step B is read 2
nbit data carries out preliminary treatment, and invalid bit permutation is wherein arrived to highest significant position or least significant bit;
C2. by after pretreatment 2
nsignificant bit in Bit data deposits one 2 in
nposition register, and after register is filled with output data.
11. 1 kinds of interlaced devices that interweave for block of information, comprising:
Buffer storage, it comprises 2
aindividual input bit wide is 2
bbit, output bit wide are the random access memory of 1 bit;
Writing address generating apparatus, generates the writing address of described buffer storage for order, and its said write address comprises that a bit is for to described 2
aindividual random access memory carries out addressing;
Read address generating device, for generate described 2 according to predetermined interleaving rule
aindividual random access memory read address;
For one, read address respectively from described 2
ain individual random access memory, respectively read 1 Bit data, wherein a, b are positive integer.
12. interlaced devices according to claim 11, is characterized in that, described predetermined interleaving rule comprises that columns is the interleaver matrix of 2 integral number power.
13. interlaced devices according to claim 12, is characterized in that, the value of b is one of 1 to 4, and the value of a is less than or equal to b.
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| CN102420674B (en) * | 2011-11-01 | 2014-03-26 | 上海华为技术有限公司 | Subblock interlacing method and parallel subblock interleaver |
| WO2020133010A1 (en) * | 2018-12-27 | 2020-07-02 | 华为技术有限公司 | Data processing method and matrix memory |
| WO2020215326A1 (en) * | 2019-04-26 | 2020-10-29 | 深圳市大疆创新科技有限公司 | Rate matching method and device for transmission channel, unmanned aerial vehicle and storage medium |
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| CN1926545A (en) * | 2004-03-25 | 2007-03-07 | 英特尔公司 | Content addressable memory constructed from random access memory |
| CN101231883A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method and apparatus for high-efficiency operation of a dynamic random access memory |
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| CN101231883A (en) * | 2007-01-22 | 2008-07-30 | 台湾积体电路制造股份有限公司 | Method and apparatus for high-efficiency operation of a dynamic random access memory |
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