CN102420674B

CN102420674B - Subblock interlacing method and parallel subblock interleaver

Info

Publication number: CN102420674B
Application number: CN201110340439.5A
Authority: CN
Inventors: 周扬
Original assignee: Shanghai Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd; Shanghai Huawei Technologies Co Ltd
Priority date: 2011-11-01
Filing date: 2011-11-01
Publication date: 2014-03-26
Anticipated expiration: 2031-11-01
Also published as: CN102420674A

Abstract

An embodiment of the invention discloses a subblock interlacing method and a parallel subblock interleaver so as to solve a problem that a present serial processing mode has complex address calculation and a low processing speed. The method comprises the following steps: with a data flow as a target matrix, carrying out reading and writing operations on the target matrix. The reading and writing operations comprise that: according to a preset column permutation rule, writing the target matrix into a storage medium, reading write-in matrix according to a column, and outputting read data; or writing the target matrix into the storage medium according to a row, reading write-in matrix according to a column and the preset column permutation rule, and outputting read data. It shows that, in the embodiment, column permutation of the target matrix can be completed when carrying out writing and reading, through directly carrying out column outputting on a matrix which is processed by the column permutation, transposition and output of the matrix are realized, thus the complex address calculation in the prior art is simplified as the column permutation and column output, and then a processing speed of subblock interlacing is raised.

Description

Sub-block deinterleaving method and parallel sub-block interleaver

Technical field

The present invention relates to transmission technique field, more particularly, relate to sub-block deinterleaving method and parallel sub-block interleaver.

Background technology

In fields such as communications, often need that data stream is carried out to sub-block and interweave.It is that a kind of ranks interweave that sub-block interweaves, and its principle is as follows: using data flow as objective matrix A, this objective matrix can be considered by X column vector and forms.An above-mentioned X column vector is carried out to column permutation by default column permutation rule, obtain the objective matrix A1 after column permutation.Subsequently, objective matrix A1 is carried out to transposition, obtain the objective matrix A2 after transposition, finally all data in objective matrix A2 are pressed to line output, complete sub-block and interweave.

Based on the above-mentioned sub-block principle that interweaves, inventor finds, in the prior art, the be treated to serial process mode of sub-block interleaver to data flow, also: data flow order is write in storage medium, and calculate each data in data flow and carry out the address after sub-block interweaves, and then according to calculate interweave after address data flow is read out.Address above mentioned calculates more complicated, has limited the processing speed that sub-block interweaves.

Summary of the invention

In view of this, embodiment of the present invention object is to provide sub-block deinterleaving method and parallel sub-block interleaver, to solve above-mentioned series of problems.

For achieving the above object, the embodiment of the present invention provides following technical scheme:

According to the embodiment of the present invention aspect, a seed block deinterleaving method is provided, for being carried out to sub-block, data stream interweaves, and the method comprises:

Using data flow as objective matrix, described objective matrix is carried out to read-write operation;

Described read-write operation comprises:

According to default column permutation rule, described objective matrix is write to storage medium by row, and by row, read the matrix writing, the data that read out are exported;

Or, described objective matrix is write to storage medium by row, according to default column permutation rule, by row, read the matrix writing, the data that read out are exported.

According to another aspect of the embodiment of the present invention, a kind of parallel sub-block interleaver is provided, for being carried out to sub-block, data stream interweaves, and it comprises: main control unit, storage medium and read-write cell, described main control unit comprises the first control unit, wherein:

Described the first control unit is used to indicate described read-write cell using data flow as objective matrix, and described objective matrix is carried out to read-write operation;

Described read-write operation comprises:

According to default column permutation rule, described objective matrix is write to described storage medium by row, by row, read the matrix writing, and the data that read out are exported;

Or, described objective matrix is write to described storage medium by row, according to default column permutation rule, by row, read the matrix writing, and the data that read out are exported.

From above-mentioned technical scheme, can find out, in embodiments of the present invention, can when writing or read, complete the column permutation of objective matrix (objective matrix A in background technology) (obtaining objective matrix A1 in background technology), because can be considered ranks, transpose of a matrix exchanges again, therefore, the embodiment of the present invention is directly listed as output by the matrix to through column permutation (being also objective matrix A1 in background technology) and comes the transposition of realization matrix and output (be equivalent to obtain in background technology objective matrix A2 and to objective matrix A2 by line output), thereby address computation complicated in prior art is reduced to column permutation and row output, and then improved the processing speed that sub-block interweaves.

Accompanying drawing explanation

In order to be illustrated more clearly in the embodiment of the present invention or technical scheme of the prior art, to the accompanying drawing of required use in embodiment or description of the Prior Art be briefly described below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skills, do not paying under the prerequisite of creative work, can also obtain according to these accompanying drawings other accompanying drawing.

The sub-block deinterleaving method flow chart that Fig. 1 a provides for the embodiment of the present invention;

Another flow chart of sub-block deinterleaving method that Fig. 1 b provides for the embodiment of the present invention;

The another flow chart of sub-block deinterleaving method that Fig. 2 provides for the embodiment of the present invention;

The another flow chart of sub-block deinterleaving method that Fig. 3 provides for the embodiment of the present invention;

The another flow chart of sub-block deinterleaving method that Fig. 4 a provides for the embodiment of the present invention;

The another flow chart of sub-block deinterleaving method that Fig. 4 b provides for the embodiment of the present invention;

The another flow chart of sub-block deinterleaving method that Fig. 5 provides for the embodiment of the present invention;

The storage mode schematic diagram of 32 bit code flow datas in each row vector that Fig. 6 provides for the embodiment of the present invention in RAM;

Another schematic diagram of the storage mode of 32 bit code flow datas in RAM in each row vector that Fig. 7 provides for the embodiment of the present invention;

The overall distribution schematic diagram of the 17 row data that Fig. 8 provides for the embodiment of the present invention in BUF group;

The parallel sub-block interleaver structural representation that Fig. 9 provides for the embodiment of the present invention;

Four kinds of structural representations of parallel sub-block interleaver that Figure 10 a-d provides for the embodiment of the present invention;

The another structural representation of parallel sub-block interleaver that Figure 11 provides for the embodiment of the present invention;

Two kinds of arrangement mode schematic diagrames that the first to the 3rd BUF that Figure 12 a and Figure 12 b provide for the embodiment of the present invention organizes;

Another arrangement mode schematic diagram that the first to the 3rd BUF that Figure 13 provides for the embodiment of the present invention organizes.

Embodiment

For quote and know for the purpose of, the technical term hereinafter using, write a Chinese character in simplified form or abridge and be summarized as follows:

BUF:Buffer, buffer memory;

ENB: base station;

LTE:Long Term Evolution, Long Term Evolution;

PDSCH:Physical Downlink Share Channel, Physical Downlink Shared Channel;

PUSCH:Physical Uplink Share Channel, Physical Uplink Shared Channel;

UE:User Equipment, subscriber equipment;

UMTS:Universal Mobile Telecommunication System, Universal Mobile Telecommunications System;

RAM:random access memory, random asccess memory.In random asccess memory, the content of memory cell can arbitrarily take out as required or deposit in, and the speed of access and memory cell is location-independent;

PSI:Parallel Subblock Interleaver, parallel sub-block interleaver;

FPGA:Field-Programmable Gate Array, field programmable gate array;

ASIC:Application Specific Integrated Circuit, application-specific integrated circuit (ASIC).

Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is clearly and completely described, obviously, described embodiment is only the present invention's part embodiment, rather than whole embodiment.Embodiment based in the present invention, those of ordinary skills, not making the every other embodiment obtaining under creative work prerequisite, belong to the scope of protection of the invention.

The embodiment of the present invention provides a seed block deinterleaving method, to solve the existing sub-block serial process mode that interweaves, address computation more complicated, the problem that processing speed is slow.

The core concept of this sub-block deinterleaving method is: using data flow as objective matrix, this objective matrix is carried out to read-write operation.And above-mentioned read-write operation is selected to realize sub-block and is interweaved by above-mentioned objective matrix being carried out to column permutation and regular row.

Referring to Fig. 1 a and Fig. 1 b, said method at least comprises the steps:

S1, using data flow as objective matrix;

S2, according to default column permutation rule, this objective matrix is write to storage medium by row;

S3, by row, read the matrix writing;

S4, the data that read out are exported.

Or,

S1, using above-mentioned data flow as objective matrix;

S5, by row, write storage medium;

S6, according to default column permutation rule, by row, read the matrix writing;

S4, the data that read out are exported.

Storage medium in all embodiment of the present invention can comprise at least one BUF group, and BUF group comprises at least one BUF.Wherein, BUF can by one independently RAM form, also can be slapped together by a plurality of RAM.When specific implementation, the number that forms a needed RAM of BUF is looked the data capacity decision of BUF storage.

Visible, in the method shown in Fig. 1 a, step S2 is writing fashionable having completed the column permutation of objective matrix (objective matrix A in background technology) (objective matrix A1 in obtaining background technology).Because transpose of a matrix is that ranks exchange, therefore, step S3 and S4 match again, when reading, by read and exported matrix transpose by row, be equivalent to complete by objective matrix A1 being transformed to objective matrix A2 simultaneously, and objective matrix A2 is pressed to line output.

And in the method shown in Fig. 1 b, step 6 and S4 match, when reading, completed column permutation and transposition simultaneously, also realized the conversion to objective matrix A2 by objective matrix A, and objective matrix A2 has been pressed to line output.

As from the foregoing, in the above embodiment of the present invention, can when writing or read, to objective matrix, complete column permutation, and by read (also can be described as regular row selects) by row, the data that read out have been exported to matrix transpose, address computation complicated in prior art is reduced to column permutation and the selection of regular row, thereby has improved the processing speed that sub-block interweaves.And because column permutation both can also can carry out writing fashionable carrying out when reading, the person of being easy to use carries out reasonable disposition according to the complexity of self link neutron block interleaving front and back end.

Certainly, the mode that above-mentioned column permutation adds regular row selection is adapted to sub-block deinterleaving processing too, and therefore, the mode that the column permutation that the above embodiment of the present invention provides adds regular row selection is applicable to the agreement that all ranks interweave, such as UMTS agreement, LTE agreement etc.

By how introducing in detail in LTE agreement, above-mentioned column permutation being added to the mode that regular row selects carry out flexible, concrete application below.

The PDSCH of LTE agreement and PUSCH link are the Turbo coding link of 1/3 code check.PDSCH link is encoded in eNB side, and PUSCH link is encoded in UE (subscriber equipment) side.LTETurbo is encoded to block encoding, supposes that code block length is K (byte), after coding, will produce system bits, first check bit sum the second check digit 3 road code streams.Above-mentioned this 3 road code stream can be referred to as LTE Turbo encoding code stream, and its length is 8K+4 (bit), is also that its corresponding data unit is bit (bit).For balancing resource and efficiency of transmission, in message transmitting procedure, reduce sudden noise jamming, need to carry out rate-matched to above-mentioned 3 road code streams.And rate-matched molecule block interleaving, bit collects selects with bit.

Said system position, first check bit sum the second check digit 3 road code streams are being carried out in sub-block interleaving process, first dummy argument need to interweave in the front end interpolation sub-block of above-mentioned three code streams, make the length of code stream become 32 integral multiple, now, front end can be added to interweave 3 road code streams of dummy argument of sub-block and be called system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 1.

Said system bit code stream the 1, first check digit code stream 1 and the second check digit code stream 1 can be considered as respectively the matrix of r_num*32, and wherein r_num represents line number (span of r_num is 2-193), and 32 represent columns.In addition, according to the relation between matrix and vector, further, also the matrix of r_num*32 can be considered as being formed by 32 column vectors (also can be described as 32 column datas); Or by r_num row vector (also can be described as the capable bit stream data of r_num), formed, and the length of each row vector or every a line bit stream data is 32 data units.Certainly, because the data unit of this 3 road code stream is bit, and in code stream, a data accounts for 1bit, and therefore, each row vector or every a line bit stream data comprise 32 bit data.

In LTE Turbo encoding code stream being carried out to the traditional approach that sub-block interweaves, said system bit code stream 1 is identical with the sub-block interleaving mode of the first check digit code stream 1, specifically comprises:

System bits code stream 1 (the first check digit code stream 1) is considered as to the matrix being comprised of 32 column vectors, and the row sequence number of these 32 column vectors is followed successively by 0-31;

Above-mentioned matrix is carried out to column permutation by column permutation rule.After carrying out column permutation, the row sequence number of above-mentioned 32 column vectors distributes and becomes: 0,16,8,24,4,20,12,28,2,18,10,26,6,22,14,30,1,17,9,25,5,21,13,29,3,19,11,27,7,23,15,31;

Afterwards, the matrix through column permutation is carried out to transposition, finally all data in the matrix after transposition are read out by row, complete the sub-block of system bits code stream 1 or the first check digit code stream 1 is interweaved.

And in traditional sub-block interleaving mode of the second check digit code stream 1, the column permutation of the second check digit code stream 1 rule is identical with system bits code stream 1 and the first check digit code stream 1, but also need it to carry out some other processing.

The second check digit code stream 1 is considered as to line number is

(being also above-mentioned r_num), columns is

C_{subblock}^{TC}

(C_{subblock}^{TC} = 32)

Matrix, its length is K _∏

(K_{Π} = R_{subblk}^{TC} * C_{subblock}^{TC}) .

In addition, suppose each data in the second check digit code stream 1 carry out putting in order before sub-block interweaves into

represent π (k) bit data), and it is carried out sub-block interweave after its put in order into (with v _krepresent to carry out the K bit data after sub-block interweaves), there is following formula:

(wherein, subscript represents code stream numbering: 0 represents first via code stream, i.e. system bits; 1 represents the second road code stream, i.e. the first check digit; 2 represent Third Road code stream, i.e. the second check digit)

The sub-block interleaving mode traditional due to the second check digit code stream 1 is not quite similar with other two code streams on the whole, therefore in the prior art, need to use two cover address calculation to calculate respectively address after interweaving of the second check digit and system bits/the first check digit, cause its more complicated on processing.While is also underused the common ground of three road code streams in sub-block interleaving treatment, has caused certain wasting of resources.

And inventor releases from above-mentioned formula, for the second check digit code stream 1, only need be by its ring shift left one data unit (can referred to as one of ring shift left), also the first bit code flow data that is about to the second check digit code stream 1 moves to code stream end, form the second check digit code stream 2, just can carry out the sub-block interleaving treatment identical with said system bit code stream the 1 and first check digit code stream 1.

Certainly, because the first bit code flow data of the second check digit code stream 1 is the sub-block dummy argument that interweaves, therefore, in other embodiments of the invention, can complete one of above-mentioned ring shift left by the mode of " remove adding sub-block first sub-block of the second check digit code stream after dummy argument dummy argument that interweaves that interweaves, and add a sub-block interleaving dummy argument at its end ".

After the processing through one of above-mentioned ring shift left, system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2 can carry out sub-block according to identical default sub-block interleaving mode and interweave.So just take full advantage of the common ground of three road code streams in sub-block interleaving treatment, further reduced the complexity of processing, reduced the wasting of resources.

Based on above-mentioned analysis, referring to Fig. 2 and Fig. 3, in other embodiments of the invention, above-mentioned steps S1 specific implementation comprises:

S11, system bits code stream, the first check digit code stream and the second check digit code stream are added respectively to the sub-block dummy argument that interweaves, obtain said system bit code stream the 1, first check digit code stream 1 and the second check digit code stream 1;

S12, the second check digit code stream 1 is adjusted, so that the second check digit code stream 1 (being also above-mentioned the second check digit code stream 2) after adjusting can carry out sub-block according to the default sub-block interleaving mode corresponding with other code streams, interweaved;

S13, using add sub-block interweave system bits code stream after dummy argument, add sub-block interweave the first check digit code stream after dummy argument and adjust after the second check digit code stream respectively as the objective matrix of r_num*32.

Certainly, corresponding, the default column permutation rule in step S2 or S6 is now the column permutation rule that above-mentioned default sub-block interleaving mode is corresponding.Meanwhile, in the processing of step S2, the objective matrix of above-mentioned r_num*32 has carried out column permutation when being written into storage medium; And in the processing of step S5, the objective matrix of above-mentioned r_num*32 does not carry out column permutation when being written into storage medium.

In addition, when said system position, first check bit sum the second check bit are carried out to sub-block deinterleaving, also Ke Dui tri-road code streams carry out same deinterleaving (as previously mentioned, deinterleaving also can adopt column permutation to add regular row and select to carry out), and then to one of the second check digit ring shift right of obtaining after deinterleaving, obtain above-mentioned the second check digit code stream 1.

Because the second check digit code stream 2 and other code streams can adopt identical sub-block interleaving mode to carry out sub-block, interweave, the emphasis of the following examples will be put in how specific implementation sub-block interweaves above, and specifically not indicate for which code stream.

Before address, the be treated to serial process of existing sub-block interleaver to data flow, and serial process has greatly limited the throughput of whole coding link.If can be by the serial of interweaving of sub-block for parallel, 2bit, 4bit, 8bit, 16bit, 32bit parallel processing such as realizing sub-block and interweaving, will improve throughput greatly.

The objective matrix of above-mentioned r_num*32 can be write to a plurality of BUF, then from each BUF, simultaneously reading out data is to realize parallel processing, and this parallel processing mode is applicable to interweave in all ranks interleaving modes or the parallel processing scene of deinterleaving.

For above-mentioned parallel processing, the present embodiment is introduced the concept of degree of parallelism: degree of parallelism represents the least significant data units L of average per moment output, and L=^X (X is more than or equal to 1 to be less than or equal to 5 positive integer).Certainly, for system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2, above-mentioned degree of parallelism is specially minimum effective bit number.

Therefore,, in other embodiments of the invention, on the basis of all embodiment of address computation being resolved into column permutation and the selection of regular row, the specific implementation of " writing storage medium by row " in above-mentioned steps S2 or S5 can comprise:

According to degree of parallelism, by row, write, to make in the matrix writing, the data that are arranged in same row in every capable data of 2L are continuously stored on the same address of same BUF group different B UF.

Accordingly, " the reading by row " in above-mentioned steps S3 or S6 specifically also can be: according to degree of parallelism, by row, read.

And when specific implementation, above-mentioned " reading by row according to degree of parallelism " can comprise again:

When L=2, read 4 row data in a column data at every turn simultaneously, during less than 4 row, supplement invalid data.

Work as L=4, and 2≤r_num≤4 o'clock, read 2 complete column datas at every turn simultaneously;

Work as L=4, and during 4 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data.

Work as L=8, and 2≤r_num≤4 o'clock, read 4 complete column datas at every turn simultaneously;

Work as L=8, and 5≤r_num≤8 o'clock, read 2 complete column datas at every turn simultaneously;

Work as L=8, and during 8 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data.

Work as L=16, and 2≤r_num≤4 o'clock, read 8 complete column datas at every turn simultaneously;

Work as L=16, and 5≤r_num≤8 o'clock, read 4 complete column datas at every turn simultaneously;

Work as L=16, and 9≤r_num≤16 o'clock, read 2 complete column datas at every turn simultaneously;

Work as L=16, and during 16 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data.

Work as L=32, and 2≤r_num≤4 o'clock, read 16 complete column datas at every turn simultaneously;

Work as L=32, and 5≤r_num≤8 o'clock, read 8 complete column datas at every turn simultaneously;

Work as L=32, and 9≤r_num≤16 o'clock, read 4 complete column datas at every turn simultaneously;

Work as L=32, and 17≤r_num≤32 o'clock, read 2 complete column datas at every turn simultaneously;

Work as L=32, and during 32 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data.

Due to when reading by row according to degree of parallelism, may need to supplement invalid data, therefore the embodiment of the present invention do not require that reading processing by row all reaches the disposal ability meeting the requirements at every turn, by carving the disposal ability that exceeds requirement be provided when appropriate, to reach the disposal ability that on average degree, realization meets the demands, this mode is applicable to all scenes that disposal ability had to requirement.

From the concrete mode reading by row according to degree of parallelism, can read the data that 2L is capable at most at every turn simultaneously.For guarantee that the capable data of above-mentioned 2L can be read simultaneously, the address of reading of reading by row according to degree of parallelism each time need to be from different BUF.For this reason, the matrix that at least needs K address (because address is from different BUF, the number minimum that therefore needs BUF is also K) storage to write.

Above-mentioned K can calculate by formula K=2LM/W, wherein M is the data sheet figure place that each row of data is stored in 1 address, for the data sheet figure place of storing data (therefore W is 1 address, the data of W/M different rows can be stored at most in 1 address), M can be divided exactly by 32, W is more than or equal to M, W=2^Z (Z is more than or equal to 1 to be less than or equal to 11 positive integer), and LM is the integral multiple of W.

Certainly, for system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2, the data unit of above-mentioned L, M and W is bit.

In addition, when the line number of objective matrix is seldom time, while reading by row according to degree of parallelism, just need to read multi-column data at every turn simultaneously.During by above-mentioned L=2 to 32, press row reading manner, known while reading by row according to degree of parallelism, can read L/2 column data at most at every turn simultaneously, therefore the minimum value of above-mentioned M is L/2.When BUF is when by one, independently RAM forms, generally, one independently the width maximum occurrences of RAM be 32bits (but not getting rid of the possibility that is greater than 32bits).Therefore by ordinary circumstance, the maximum occurrences of above-mentioned W is 32bits.By M=L/2, the above-mentioned K=2LM/W of W=32 substitution, can turn to: K=L^2/32.Also:

For 8bits degree of parallelism, K minimum is L^2/32=2;

For 2bits/4bits degree of parallelism, K minimum is

For 16bits degree of parallelism, K minimum is L^2/32=8;

For 32bits degree of parallelism, K minimum is L^2/32=32.

Certainly, except sub-block interleaving treatment, the BUF in BUF group also may process for other.Also, each address is for storing the not enough 32bits of width possibility of above-mentioned data, and the number of required BUF also can correspondingly increase.

In addition, it should be noted that the above-mentioned invalid data of mentioning and the sub-block dummy argument that interweaves is different, the sub-block dummy argument that interweaves is regarded as valid data when carrying out sub-block interleaving treatment.

Owing to may needing to supplement without logarithmic data, corresponding, above-mentioned steps S4 also will change thereupon, and referring to Fig. 4 a and Fig. 4 b, its specific implementation can comprise:

S41, when reading by row according to degree of parallelism, produce a sign (this sign is for characterizing the valid data units of these data that read out by row according to degree of parallelism) at every turn;

S42, according to above-mentioned sign, remove invalid data in these data that read out by row according to degree of parallelism to obtain valid data;

S43, the valid data that get are linked, obtain valid data chain;

S44, export the valid data chain that length is 2L at every turn.

Certainly, for system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2, the valid data units in above-mentioned steps S41-S44 is specially effective number of bits.

Above-mentioned steps S41-S44 can be described as bit wide and pieces together.Hence one can see that, the embodiment of the present invention does not also require the data of at every turn all processing equal length, but it can carry out bit wide and piece together when output data, to realize, export on the whole the effect of equal length data at every turn, therefore, this mode is applicable to all requirements and processes the identical scene of output data length at every turn.

Below a certain code stream of take in system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2 is described more specifically as example, therefore, in the present embodiment, data unit is bit.

In the present embodiment, suppose in above-mentioned r_num*32 objective matrix, r_num=17, degree of parallelism requires as 8bits.Known according to aforementioned record, L=8 during 8 < r_num, reads 16 row data in a column data at every turn simultaneously, therefore requires the data that are arranged in same row in every continuous 16 row data to be stored on the same address of BUF group different B UF.

In the present embodiment, intend the RAM be 16bits by width and form BUF, and, 1 independently RAM represent a BUF.Set each row of data and in 1 address, can only deposit 8bits (being M=8), 1 row data need 4 continuous addresses just can deposit, and set 1 address all for storing data, are also W=16.According to formula K=2LM/W, can obtain K=2*8*8/16=8.Therefore, in the present embodiment, select 8 RAM.

Referring to Fig. 5, its sub-block interleaving treatment flow process is as follows:

S501, according to default column permutation rule, 2 row data in (17*32) objective matrix are carried out to write operation, not enough data are filled with invalid data simultaneously.In the matrix that final order writes, the data that are positioned at same row in every continuous 16 row bit stream datas are stored on the same address of 8 RAM.

It should be noted that, when RAM is carried out to write operation, write operation all must be write a full address each time.Due in the present embodiment, in RAM, the 16bit of 1 address is all for memory code flow data, and a line bit stream data deposits 8bit in an address, therefore must the 8bit data in two row bit stream datas be write to same address simultaneously.

In addition, because the line number of the objective matrix in the present embodiment is 17, when 32 bit code flow datas of the 17th row (being also last column) are carried out to write operation, (divide and complete writing the 17th row bit stream data 4 times), to an address, write 8bits wherein at every turn, and write invalid data in the remaining 8bits memory space in this address (being also not enough part), to reach the object of writing full this address.Above-mentioned invalid data can be arbitrary data.

In addition, frontly address, can when writing or read, complete column permutation.Suppose before not carrying out sub-block interleaving treatment, in above-mentioned (17*32) objective matrix, row sequence number corresponding to 32 bit code flow datas in each row vector is respectively 0-31.When writing the fashionable column permutation that carries out, the storage mode of 32 bit code flow datas in RAM in each row vector as shown in Figure 6.Related column replacement rule refers to aforementioned record herein, and therefore not to repeat here.

Certainly, in other embodiments of the invention, also can select not fashionablely to carry out column permutation and when reading by row, to carry out column permutation writing, by this kind of mode, the storage mode of 32 bit code flow datas in RAM in each row vector as shown in Figure 7.

Wherein, the ADDR0-ADDR3 in Fig. 6 and Fig. 7 represents front 8bits or the rear 8bits of 4 link addresses in same RAM.

The overall distribution of 17 row data (representing this 17 row data with ROW0-ROW16) in BUF group can be referring to Fig. 8 (representing aforementioned 8 RAM with B0-B7 in Fig. 8).

Refer to Fig. 6 and Fig. 7, known, ROW0 and ROW1 are stored in the ADDR0-ADDR3 of B0, by that analogy simultaneously simultaneously:

ROW2 and ROW3 are stored in the ADDR0-ADDR3 of B1 simultaneously;

ROW4 and ROW5 are stored in the ADDR0-ADDR3 of B2 simultaneously;

ROW6 and ROW7 are stored in the ADDR0-ADDR3 of B3 simultaneously;

ROW14 and ROW15 are stored in the ADDR0-ADDR3 of B7 simultaneously;

ROW16 is stored in the front 8bit memory space of ADDR4-ADDR7 of B0, and other memory spaces of ADDR4-ADDR7 are filled with invalid data.

Therefore, take Fig. 6 as example, in arbitrary row vector in ROW0-ROW15: the data that row sequence number is 16 are stored in the ADDR0 of a certain RAM, row sequence number is that 26 data are stored in the ADDR1 of a certain RAM, row sequence number is that 21 data are stored in the ADDR2 of a certain RAM, and the data that row sequence number is 3 are stored in the ADDR3 of a certain RAM.Also,, in these 16 row vectors of ROW0-ROW15 or 16 row bit stream datas, the data that are positioned at same row are stored on the same address of different RAM (BUF).

S502, read 16 row bit stream datas in a row bit stream data at every turn simultaneously, during less than 16 row, supplement invalid data.

Refer to Fig. 8, concrete reading manner is:

(moment 0) for the first time: read the 1st bit data (1bit) of ROW0-ROW15, also, read in the whole matrix being formed by ROW0-ROW17, the front 16 row data in the 1st column data;

(moment 1) for the second time: read the 1st bit data and 15 invalid datas (15bits) of ROW16, also, read in the whole matrix consisting of ROW0-ROW17, the 17th row data of the 1st column data read 15 without logarithmic data simultaneously);

(moment 3) for the third time: read the 2nd bit data (1bit) of ROW0-ROW15, also, read in the whole matrix being formed by ROW0-ROW17, the front 16 row data in the 2nd column data;

By that analogy, until all read.

S503, produce a sign according to degree of parallelism during by row readout code flow data at every turn, to characterize the effective number of bits of this bit stream data reading out by row according to degree of parallelism;

For example, the sign of 0 correspondence characterizes and reads out 16 significant bits constantly, and the sign of 1 correspondence sign reads out 1 significant bit constantly, the sign of 2 correspondences characterizes and reads out 16 significant bits constantly, and the sign of 3 correspondences characterizes and reads out 1 significant bit constantly, ..., therefore, its degree of parallelism is that 8.5bits/cycle (constantly, is the concept on hardware, process and be called 1 cycle for 1 time), meet the requirement that degree of parallelism is 8bits.

S504, according to above-mentioned sign, remove the invalid data in this bit stream data reading out by row according to degree of parallelism, effective code flow data is linked, obtain effective code flow data chain;

S505, export effective code flow data chain that length is 16bit (also 16 valid data) at every turn.

After the LTE Turbo encoding code stream obtaining after sub-block interweaves, follow-uply will carry out bit to it and collect with bit and select.

In actual applications, collect and need some control informations while selecting with bit above-mentioned LTE Turbo encoding code stream being carried out to bit.Therefore, above-mentioned LTE Turbo encoded data stream also can comprise control information stream, and embodiment of the present invention support LTE Turbo encoding code stream and control information stream carry out sub-block simultaneously and interweaves.

Accordingly, the specific implementation of above-mentioned steps S1 also can comprise:

Using control information stream as the objective matrix that comprises the capable control information data of r_num, the length of every a line control information data is 32 data units.

Processing is afterwards identical with aforementioned record, and therefore not to repeat here.In addition, control information stream can produce when block encoding, also can after block encoding, produce.Therefore, above-mentioned control information stream can be a road and also can be three tunnels.

Such as, control information stream can comprise system bits control information stream, the first check bit control information flow and the second check bit control information flow.Certainly, no matter a road or three tunnels, the bit code flow data in code stream is corresponding with a control information in corresponding control information stream.

When control information stream is 3 tunnel, above-mentioned " using control information stream as the objective matrix that comprises the capable control information data of r_num " can comprise again in refinement:

By the second check bit control information flow ring shift left one data unit of the second check digit code stream 1 correspondence;

Said system bit code is flowed to the system bits control information stream of 1 correspondence, the first check bit control information flow of above-mentioned the first check digit code stream 1 correspondence, and the second check bit control information flow after ring shift left one data unit, respectively as the objective matrix that comprises the capable control information data of r_num.

In other embodiments of the invention, above-mentioned control information can comprise dummy argument indication, dummy argument has indicated the position of dummy argument in the code stream of exporting after sub-block interleaving treatment, and the punching (removing invalid dummy argument) collecting in selecting with bit for bit operates required.

The acquisition methods of dummy argument indication has two kinds: a kind of is by address computation, to obtain after sub-block interweaves; Another kind is to show at the interweave rower that advances of sub-block, and with coded data, carries out together sub-block and interweave, and then passes to rear class processing unit.The method that obtains dummy argument indication before sub-block interweaves is: before system bits, the first check digit, N+F (bits) is dummy argument; Front N bits before the second one of check digit ring shift left is dummy argument.Wherein, N is the sub-block dummy argument number that interweaves, and F is current code block segmentation dummy argument number.

When corresponding dummy argument indication is adjusted to the second check digit, can take equally the mode of a dummy argument indication of ring shift left.Concrete, can remove by dummy argument indication corresponding to dummy argument that first sub-block is interweaved, and in the end face adds a dummy argument indication that sub-block interleaving dummy argument is corresponding.

It should be noted that control information can comprise any user-defined information.Therefore, in code stream, the length of a bit code flow data or data unit are 1 bit, but the length of a corresponding control information or data unit may more than 1 bits with it, and it may be 2 bits, 3 bits or more.

In view of this, in all embodiment of the present invention, when to operations such as code stream procession displacements, its exercisable minimum particle size is a bit stream data, and when control information being flow to the operations such as ranks displacement, its exercisable minimum particle size is a control information.And, because the length of control information may be greater than 1bit, therefore, when control information stream is carried out to sub-block interleaving treatment, may need more BUF or memory space.

Answer in contrast, the embodiment of the present invention also provides simultaneously carries out to above-mentioned data flow the parallel sub-block interleaver (PSI) that sub-block interweaves.

Fig. 9 shows a kind of structure of PSI, and it comprises: the first control unit 1, storage medium 2 and read-write cell 3, the first control units 1 are under the jurisdiction of main control unit 100, wherein:

The first control unit 1 indication read-write cell 3, using data flow as objective matrix, carries out read-write operation to objective matrix;

Above-mentioned read-write operation comprises:

According to default column permutation rule, objective matrix is write to storage medium 2 by row, by row, read the matrix writing, and the data that read out are exported;

Or, objective matrix is write to storage medium 2 by row, according to default column permutation rule, by row, read the matrix writing, and the data that read out are exported.

Above-mentioned PSI specifically can be used for that LTE Turbo encoded data stream is carried out to sub-block and interweaves.And frontly addressed, LTE Turbo encoded data stream comprises system bits code stream, the first check digit code stream and the second check digit code stream.

While being specifically applied to the sub-block interleaving treatment of system bits code stream, the first check digit code stream and the second check digit code stream, referring to Figure 10 a-d, above-mentioned PSI or main control unit 100 also can comprise sub-block interweave dummy argument adding device 4 and the first adjustment unit 5, wherein:

The sub-block dummy argument adding device 4 that interweaves can add respectively the sub-block dummy argument that interweaves to said system bit code stream, the first check digit code stream and the second check digit code stream, or the 3 pairs of said system bit codes of indication read-write cell stream, the first check digit code stream and the second check digit code streams add respectively the sub-block dummy argument that interweaves, to form aforementioned system bit code stream the 1, first check digit code stream 1 and the second check digit code stream 1;

The second check digit code stream (the second check digit code stream 1) that the first 5 of adjustment units can interweave after dummy argument to interpolation sub-block is adjusted, or 3 pairs of the second check digit code streams 1 of indication read-write cell are adjusted, to obtain aforementioned the second check digit code stream 2, how to adjust and refer to aforementioned relevant introduction herein, therefore not to repeat here.

In addition, in the present embodiment, aforementioned objective matrix comprises the first object matrix corresponding with system bits code stream 1, second objective matrix corresponding with the first check digit code stream 1, and three objective matrix corresponding with the second check digit code stream 2.And the first line number to the 3rd objective matrix is r_num, columns is 32.

Accordingly, in the present embodiment, aforementioned default column permutation rule is specially: the column permutation rule in the default sub-block interleaving mode of system bits code stream 1 (the first check digit code stream 1) correspondence.

In other embodiments of the invention, the specific implementation of " writing by row " in " read-write operation " mentioned in aforementioned all embodiment can comprise:

According to degree of parallelism L, by row, write, to make in the matrix writing, the data that are arranged in same row in every capable data of 2L are continuously stored on the same address of same BUF group different B UF.

Certainly, frontly address, for system bits code stream 1, the first check digit code stream 1 and the second check digit code stream 2, degree of parallelism is specially minimum effective bit number.

Accordingly, specifically also can be of " the reading by row " in above-mentioned " read-write operation ": read by row according to degree of parallelism.

And the specific implementation of " reading by row according to degree of parallelism " can be referring to aforementioned introduction, therefore not to repeat here.

Accordingly, " data that read out are exported " in above-mentioned read-write operation can be refined as again aforesaid " bit wide is pieced together ", at this, also do not repeat.

For calling conveniently, existing other unit or parts except storage medium and read-write cell are referred to as control section.

For the PSI of LTE Turbo encoded data stream, at the beginning of design, set degree of parallelism L, and the columns 32 of objective matrix is also changeless.And after block encoding, the line number r_num of system bits code stream, the first check digit code stream and the second check digit code stream also can be known.Therefore, the control section of PSI can be known by simple computation, reads read out effective number of bits each time according to degree of parallelism L by row.For example:

Work as L=8, during r_num=7, read 2 complete column datas at every turn simultaneously, now there is no invalid data;

And work as L=8, and during r_num=17, read 16 row data in a column data at every turn simultaneously,, when reading the 17th row data, must have the invalid data of 15bit.Therefore, the bit number of 0 invalid data reading must be 0 constantly, and the bit number of the invalid data constantly reading out for 1 o'clock must be 15.

Therefore, control section oneself maybe can indicate read-write cell to produce the sign of bit wide in piecing together, and according to the identical effective code flow data of this sign output length.

In other embodiments of the invention, corresponding with above-mentioned the first to three objective matrix, referring to Figure 11, BUF group in all embodiment can comprise a BUF group 201 of the bit stream data of storage first object matrix above, the 3rd BUF group 203 of the 2nd BUF group 202 of the bit stream data of storage the second objective matrix and the bit stream data of storage the 3rd objective matrix.

The arrangement mode of the one BUF group the 201, the 2nd BUF group the 202, the 3rd BUF group 203 has multiple, and Figure 12 a and 12b show wherein two kinds.

For realizing parallel processing, 203 BUF numbers that can comprise of above-mentioned BUF group 201, the two BUF group the 202 and the 3rd BUF groups, have the restriction of minimum number.And also may process for other due to a certain or some BUF group, therefore, these three BUF organize corresponding minimum number and may be not quite similar.

The embodiment of the present invention represents above-mentioned minimum number with K, and K can calculate by aforementioned formula K=2LM/W, and therefore not to repeat here.

It should be noted that BUF group the 201, the 2nd BUF group the 202, a 3rd BUF group 203 can be the BUF group in physical significance, can be also only the BUF group from marking off in logic.

Referring to Figure 13, can select 24 RAM to form eight physics BUF (every 3 RAM form a BUF): B0-B7.But RAM0-7 logically belongs to a BUF group, RAM8-15 logically belongs to the 2nd BUF group, and RAM16-23 logically belongs to the 3rd BUF group.

In addition, these eight physical devices in Figure 13 of still take are example, suppose that system bits code stream 1 needs 8 BUF to store, and needs to take 64 addresses on each BUF; The first check digit code stream 1 also needs 8 BUF to store, and on each BUF, needs to take 64 addresses; The second check digit code stream 2 equally also needs 8 BUF to store, and on each BUF, also needs to take 64 addresses.And each BUF can provide 256 addresses in B0-B7.Thereby can to system bits code stream 1, a 64-127 address assignment, give first check digit code stream 1, a 128-191 address assignment to the second check digit code stream 2 0-63 the address assignment of each BUF in B0-B7.

Certainly, according to this mode of address assignment, system bits code stream 1, the first check digit code stream 1 and the second check bit code stream 2 are that (being also serial) carries out parallel processing that sub-block interweaves in turn in time.Other methods of salary distribution in time simultaneously (also parallel) 3 road code streams are carried out respectively to parallel processing that sub-block interweaves.

In addition, frontly address, LTE Turbo encoded data stream also can comprise control information stream.

In contrast should, objective matrix also can comprise with above-mentioned control information and flow corresponding control information objective matrix, relevant introduction refers to aforementioned description herein, therefore not to repeat here.

In addition, when control information stream comprises system bits control information stream, the first check digit data flow and the second check bit control information flow, aforementioned PSI or main control unit also can comprise the second adjustment unit.This second adjustment unit can be used for the second check bit control information flow ring shift left one data unit of the second check digit code stream 1 correspondence, or indication read-write cell is by the second check bit control information flow ring shift left one data unit of the second check digit code stream 1 correspondence.

Meanwhile, above-mentioned control information objective matrix comprises again the first to the 3rd control information objective matrix, and the relevant introduction of the first to the 3rd control information objective matrix refers to aforementioned record herein, and therefore not to repeat here.

It should be noted that except storage medium 2, the function of the arbitrary unit in all embodiment of the present invention or the arbitrarily combination function of a unit all can be realized by FPGA or ASIC.As for storage medium 2, both can be the internal storage medium of FPGA or ASIC, also can be independently exterior storage medium.

Certainly, for the consideration on cost, the function of above-mentioned all unit can be realized with a slice FPGA or ASIC, also adopt the internal storage medium of FPGA or ASIC as above-mentioned storage medium 2, FPGA or ASIC realize as PSI the parallel processing that sub-block interweaves.

In addition, frontly address, eNB side and UE side all need that LTE Turbo coded number code stream is carried out to sub-block and interweave.Generally speaking, eNB side adopts FPGA or ASIC, and ASIC is due to when the product volume production, have the advantages such as unit cost is low, performance is high, low in energy consumption, so UE side is generally selected ASIC.Certainly, along with FPGA in unit cost, power consumption, fail safe, reliability, power up the optimization of the aspects such as validity, monolithic integrated level, size, ease for use and performance, UE side is not got rid of the use to FPGA.

Now with monolithic FPGA or ASIC, the embodiment of the present invention is done to other supplementary notes:

When realizing the function of method that the embodiment of the present invention provided or device with FPGA or ASIC class hardware, to the read and write of storage medium, be to be completed by FPGA or the upper different parts of ASIC, be also read operation and write operation are relatively independent.

Also therefore, the indication of the aforementioned unit of mentioning to read-write cell, when realizing by hardware, actual is by indicating implementing the independent of parts of " reading " operation, and the independence indication of the parts of enforcement " writing " operation is realized.In addition, aforementioned " data that read out are exported " and refinement thereof, belong to " reading " operation.

Also have, " add sub-block interweave dummy argument " completes when write operation.Especially it is pointed out that the second check digit code stream is added to interweave one of dummy argument and ring shift left of sub-block to be completed when the write operation in the lump.

Say for example, suppose that need to add 8 sub-block interleaving dummy arguments to the second check digit code stream producing after block encoding forms aforementioned the second check digit code stream 1, when practical operation, 7 the sub-block interleaving dummy arguments of the second check digit code stream interpolation to producing after block encoding, at end, add 1 sub-block interleaving dummy argument (also aforesaid " by adding sub-block first sub-block of the second check digit code stream after dummy argument dummy argument that interweaves that interweaves, remove; and at its end, add a sub-block interleaving dummy argument "), realize that sub-block dummy argument adds and one of ring shift left simultaneously.

Those of ordinary skills can recognize, unit and the algorithm steps of each example of describing in conjunction with embodiment disclosed herein, can realize with electronic hardware, computer software or the combination of the two, for the interchangeability of hardware and software is clearly described, composition and the step of each example described according to function in the above description in general manner.These functions are carried out with hardware or software mode actually, depend on application-specific and the design constraint of technical scheme.Professional and technical personnel can specifically should be used for realizing described function with distinct methods to each, but this realization should not thought and exceeds scope of the present invention.

Those skilled in the art can be well understood to, and for convenience and simplicity of description, the specific works process of the device of foregoing description and unit, can, with reference to the corresponding process in preceding method embodiment, not repeat them here.

In the several embodiment that provide in the application, should be understood that disclosed apparatus and method can realize by another way.For example, device embodiment described above is only schematic, for example, the division of said units, be only that a kind of logic function is divided, during actual realization, can have other dividing mode, for example a plurality of unit or assembly can in conjunction with or can be integrated into another system, or some features can ignore, or do not carry out.Another point, shown or to cross the coupling each other of opinion or direct-coupling or communication connection can be by some interfaces, indirect coupling or the communication connection of device or unit, can be electrically, machinery or other form.

The above-mentioned unit as separating component explanation can or can not be also physically to separate, and the parts that show as unit can be or can not be also physical locations, can be positioned at a place, or also can be distributed on a plurality of unit.Can select according to the actual needs some or all of unit wherein to realize the object of the present embodiment scheme.

In addition, each functional unit in each embodiment of the present invention can be integrated in a processing unit, can be also that the independent physics of unit exists, and also can be integrated in a unit two or more unit.Above-mentioned integrated unit both can adopt the form of hardware to realize, and also can adopt the form of SFU software functional unit to realize.

If the form of SFU software functional unit of usining above-mentioned integrated unit realizes and during as production marketing independently or use, can be stored in a computer read/write memory medium.Understanding based on such, the all or part of of the part that technical scheme of the present invention contributes to prior art in essence in other words or this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprise that some instructions are with so that a computer equipment (can be personal computer, server, or the network equipment etc.) carry out all or part of step of each embodiment said method of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, read-only memory (ROM, Read-Only Memory), the various media that can be program code stored such as random access memory (RAM, Random Access Memory), magnetic disc or CD.

Above-mentioned explanation to the disclosed embodiments, makes professional and technical personnel in the field can realize or use the present invention.To the multiple modification of these embodiment, will be apparent for those skilled in the art, General Principle as defined herein can, in the situation that not departing from the spirit or scope of the present invention, realize in other embodiments.Therefore, the present invention will can not be restricted to these embodiment shown in this article, but will meet the widest scope consistent with principle disclosed herein and features of novelty.

Claims

1. a seed block deinterleaving method, interweaves for data stream is carried out to sub-block, it is characterized in that, comprising:

Using described data flow as objective matrix, described objective matrix is carried out to read-write operation;

Described read-write operation comprises:

According to default column permutation rule, described objective matrix is write to storage medium by row, writing the fashionable column permutation having completed objective matrix, and by row, reading the matrix writing, the data that read out are exported;

Or, described objective matrix is write to storage medium by row, according to default column permutation rule, by row, read the matrix writing, when reading, completed column permutation and transposition simultaneously, the data that read out are exported.

2. the method for claim 1, is characterized in that:

Described method interweaves for LTE Turbo encoded data stream is carried out to sub-block, and described LTE Turbo encoded data stream comprises LTE Turbo encoding code stream, and data unit corresponding to described LTE Turbo encoding code stream is bit;

Described LTE Turbo encoding code stream comprises system bits code stream, the first check digit code stream and the second check digit code stream;

The described specific implementation using described data flow as objective matrix comprises:

Described system bits code stream, the first check digit code stream and the second check digit code stream are added respectively to the sub-block dummy argument that interweaves;

The second check digit code stream ring shift left one data unit that interpolation sub-block is interweaved after dummy argument, obtain the second check digit code stream after adjusting, the second check digit code stream after described adjustment can carry out sub-block according to default sub-block interleaving mode corresponding to the system bits code stream interweaving after dummy argument with interpolation sub-block and interweave;

Using add sub-block interweave system bits code stream after dummy argument, add sub-block and interweave the first check digit code stream after dummy argument and the second check digit code stream after described adjustment respectively as the objective matrix that comprises the capable bit stream data of r_num, the length of every a line bit stream data is 32 data units, and the span of described r_num is 2 to 193;

Described default column permutation rule is specially the column permutation rule that described default sub-block interleaving mode is corresponding.

3. method as claimed in claim 2, is characterized in that,

Described storage medium comprises at least one buffer memory BUF group, and described BUF group comprises at least one BUF;

The described specific implementation that writes storage medium by row comprises:

According to degree of parallelism, by row, write, to make in the matrix writing, the data that are arranged in same row in every capable data of 2L are continuously stored on the same address of same BUF group different B UF;

Described degree of parallelism represents the least significant data units L of average per moment output, described L=2^X, and described X is more than or equal to 1 to be less than or equal to 5 positive integer.

4. method as claimed in claim 3, is characterized in that, the described specific implementation reading by row comprises: according to described degree of parallelism, by row, read.

5. method as claimed in claim 4, is characterized in that, the described specific implementation reading by row according to described degree of parallelism comprises:

When L=2, read 4 row data in a column data at every turn simultaneously, during less than 4 row, supplement invalid data;

Work as L=4, and during 4 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data;

Work as L=8, and during 8 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data;

Work as L=16, and during 16 < r_num, read the capable data of 2L in a column data at every turn simultaneously, when not enough 2L is capable, supplement invalid data;

6. method as claimed in claim 5, is characterized in that, the described specific implementation that the data that read out are exported comprises:

When reading by row according to described degree of parallelism, produce a sign, described sign is for characterizing the valid data units of these data that read out by row according to degree of parallelism at every turn;

According to described sign, remove invalid data in these data that read out by row according to degree of parallelism to obtain valid data;

The valid data that get are linked, obtain valid data chain;

The valid data chain that each output length is 2L.

7. method as claimed in claim 2, it is characterized in that, describedly by adding the interweave specific implementation of the second check digit code stream ring shift left one data unit after dummy argument of sub-block, comprise: described interpolation sub-block first sub-block of the second check digit code stream after dummy argument dummy argument that interweaves that interweaves is removed, at its end, add a sub-block interleaving dummy argument.

8. the method as described in claim 3-7 any one, it is characterized in that, described BUF group comprises at least K BUF, described K=2LM/W, wherein M is the data sheet figure place that each row of data is stored in 1 address, described W is that 1 address is for storing the data sheet figure place of data, M can be divided exactly by 32, W=2^Z, described Z is more than or equal to 1 to be less than or equal to 11 positive integer, and LM is the integral multiple of W.

9. method as claimed in claim 2, is characterized in that:

Described LTE Turbo encoded data stream also comprises control information stream;

The described specific implementation using described data flow as objective matrix also comprises:

Using described control information stream as the objective matrix that comprises the capable control information data of r_num, the length of every a line control information data is 32 data units.

10. method as claimed in claim 9, is characterized in that,

Described control information stream comprises system bits control information stream, the first check bit control information flow and the second check bit control information flow;

Described described control information stream is comprised as the specific implementation that comprises the objective matrix of the capable control information data of r_num:

The second check bit control information flow ring shift left one data unit corresponding to the second check digit code stream that described interpolation sub-block is interweaved after dummy argument;

System bits control information stream corresponding to system bits code stream that described interpolation sub-block is interweaved after dummy argument, the first check bit control information flow corresponding to the first check digit code stream that described interpolation sub-block interweaves after dummy argument, and the second check bit control information flow after ring shift left one data unit, respectively as the objective matrix that comprises the capable control information data of r_num.

11. 1 kinds of parallel sub-block interleavers, interweave for data stream is carried out to sub-block, it is characterized in that, comprising: main control unit, and storage medium and read-write cell, described main control unit comprises the first control unit, wherein:

Described the first control unit is used to indicate described read-write cell using described data flow as objective matrix, and described objective matrix is carried out to read-write operation;

Described read-write operation comprises:

According to default column permutation rule, described objective matrix is write to described storage medium by row, writing the fashionable column permutation having completed objective matrix, by row, read the matrix writing, and the data that read out are exported;

Or, described objective matrix is write to described storage medium by row, according to default column permutation rule, by row, read the matrix writing, when reading, completed column permutation and transposition simultaneously, and the data that read out have been exported.

12. parallel sub-block interleavers as claimed in claim 11, is characterized in that:

Described parallel sub-block interleaver interweaves specifically for LTE Turbo encoded data stream is carried out to sub-block, and described LTE Turbo encoded data stream comprises LTE Turbo encoding code stream, and data unit corresponding to described LTE Turbo encoding code stream is bit;

Described parallel sub-block interleaver or described main control unit also comprise sub-block interweave dummy argument adding device and the first adjustment unit, wherein:

Described sub-block interweave dummy argument adding device for, described system bits code stream, the first check digit code stream and the second check digit code stream are added respectively to the sub-block dummy argument that interweaves,

Or indicate described read-write cell to add respectively the sub-block dummy argument that interweaves to described system bits code stream, the first check digit code stream and the second check digit code stream;

Described the first adjustment unit is used for, the second check digit code stream ring shift left one data unit that interpolation sub-block is interweaved after dummy argument, obtain the second check digit code stream after adjusting, the second check digit code stream after described adjustment can carry out sub-block according to default sub-block interleaving mode corresponding to the system bits code stream interweaving after dummy argument with interpolation sub-block and interweave

Or second check digit code stream ring shift left one data unit of indicating described read-write cell that interpolation sub-block is interweaved after dummy argument, obtains the second check digit code stream after described adjustment;

Described objective matrix comprises first object matrix corresponding to system bits code stream interweaving after dummy argument with interpolation sub-block, the second objective matrix corresponding to the first check digit code stream interweaving after dummy argument with interpolation sub-block, and three objective matrix corresponding with the second check digit code stream after described adjustment, the described first to the 3rd objective matrix includes the capable bit stream data of r_num, every a line bit stream data length is 32 data units, and the span of described r_num is 2 to 193;

13. parallel sub-block interleavers as claimed in claim 12, is characterized in that, described storage medium comprises at least one BUF group, and described BUF group comprises at least one BUF;

The specific implementation writing by row in described read-write operation comprises:

14. parallel sub-block interleavers as claimed in claim 13, is characterized in that, the specific implementation reading by row in described read-write operation comprises: according to described degree of parallelism, by row, read.

15. parallel sub-block interleavers as claimed in claim 14, is characterized in that, the described specific implementation reading by row according to described degree of parallelism comprises:

16. parallel sub-block interleavers as claimed in claim 15, is characterized in that, the specific implementation that the data to reading out in described read-write operation are exported comprises:

The valid data that get are linked, obtain valid data chain;

The valid data chain that each output length is 2L.

17. parallel sub-block interleavers as described in claim 13-16 any one, is characterized in that,

Described BUF group comprises the first to the 3rd BUF group;

A described BUF group is for storing the bit stream data of described first object matrix;

Described the 2nd BUF group is for storing the bit stream data of described the second objective matrix;

Described the 3rd BUF group is for storing the bit stream data of described the 3rd objective matrix.

18. parallel sub-block interleavers as claimed in claim 17, it is characterized in that, arbitrary described BUF group comprises at least K BUF, described K=2LM/W, wherein M is the data sheet figure place that each row of data is stored in 1 address, described W is that 1 address is for storing the data sheet figure place of data, M can be divided exactly by 32, W=2^Z, described Z is more than or equal to 1 to be less than or equal to 11 positive integer, and LM is the integral multiple of W.

19. parallel sub-block interleavers as claimed in claim 12, is characterized in that,

Described objective matrix also comprises with described control information and flows corresponding control information objective matrix, and described control information objective matrix comprises the capable control information data of r_num, and every a line control information data comprise 32 data units.

20. parallel sub-block interleavers as claimed in claim 19, is characterized in that,

Described control information stream comprises system bits control information stream, the first check digit data flow and the second check bit control information flow;

Described parallel sub-block interleaver or described main control unit also comprise the second adjustment unit, second check bit control information flow ring shift left one data unit corresponding to second check digit code stream of described the second adjustment unit for described interpolation sub-block is interweaved after dummy argument, or

Second check bit control information flow ring shift left one data unit corresponding to the second check digit code stream of indicating described read-write cell that described interpolation sub-block is interweaved after dummy argument;

Described control information objective matrix comprises the first to the 3rd control information objective matrix;

System bits control information corresponding to system bits code stream that described the first control information objective matrix interweaves after dummy argument with described interpolation sub-block flowed corresponding;

The first check bit control information stream that described the second control information objective matrix is corresponding with the first check bit code stream that interpolation sub-block interweaves after dummy argument is corresponding;

Described the 3rd control information objective matrix is corresponding with the second check bit control information flow of ring shift left one data unit.