CN101938325A - Rate de-matching method and device for finite length circular buffering rate matching - Google Patents
Rate de-matching method and device for finite length circular buffering rate matching Download PDFInfo
- Publication number
- CN101938325A CN101938325A CN2009101515095A CN200910151509A CN101938325A CN 101938325 A CN101938325 A CN 101938325A CN 2009101515095 A CN2009101515095 A CN 2009101515095A CN 200910151509 A CN200910151509 A CN 200910151509A CN 101938325 A CN101938325 A CN 101938325A
- Authority
- CN
- China
- Prior art keywords
- data
- rate
- circuit
- sub
- parallel
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Error Detection And Correction (AREA)
- Detection And Prevention Of Errors In Transmission (AREA)
Abstract
The invention discloses a rate de-matching method and a rate de-matching device for finite length circular buffering rate matching. The method comprises: buffering input data in parallel according to the column rearrangement mode of sub-block interweavers; performing parallel processing of the data buffered in parallel; and outputting processed data as de-matched-rate data. The method and the device have the advantages of improving rate de-matching throughput and reducing rate de-matching time.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of dissociation rate matching method and device of limited length circulating buffer memory rate coupling.
Background technology
The rate conversion of limited length circulating buffer memory rate coupling flexibly, to separate rate-matched simple, adopted by many systems.The process of limited length circulating buffer memory rate coupling as shown in Figure 1.This rate-matched is at first carried out sub-block interleaving respectively to three circuit-switched data of Turbo coding output, and this sub-block interleaving is that a ranks matrix interweaves, and writes by row earlier and carries out rank transformation again, reads by leu at last; Then collect module with the synthetic circuit-switched data of three circuit-switched data through bit, preceding 1/3 of this circuit-switched data is a first via data, and then the back two paths of data alternately constitutes back 2/3 data successively, has so just constituted a virtual circular buffer; Collect with cutting through bit at last and obtain dateout, a certain position k from circular buffer
0The transmission that begins to circulate meets the demands up to number, and the centre runs into will skipping of NULL.Separating rate-matched is exactly the inverse process of rate-matched.
In correlation technique, dissociation rate matching method commonly used is earlier the data serial that receives to be cached in the memory, then it is carried out subsequent treatment, and the serial buffer memory makes the throughput of separating rate-matched reduce, and the time that causes separating the rate-matched process increases.
Summary of the invention
This bright purpose is to provide a kind of dissociation rate matching method and device of limited length circulating buffer memory rate coupling, and it is low to solve the throughput of separating rate-matched in the correlation technique, separates the long technical problem of time of rate-matched process.
According to an aspect of the present invention, provide a kind of dissociation rate matching method of limited length circulating buffer memory rate coupling, having comprised: according to the rearrangement pattern parallel buffer input data of sub-block interleaver; Data to parallel buffer are carried out parallel processing; The data after the rate-matched are separated in data conduct after output is handled.
Preferably, the rearrangement pattern parallel buffer input data according to sub-block interleaver specifically comprise: according to the parallel ping-pong buffer input of the rearrangement pattern of sub-block interleaver data.
Preferably, the data of parallel buffer are carried out parallel processing specifically comprise:, and data are recovered according to the punching pattern according to rearrangement mode producing punching pattern; Recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively; Three circuit-switched data are walked abreast respectively separate sub-block interleaving.
Preferably, according to the punching pattern data are recovered specifically to comprise:, obtain being in the data address of NULL according to the punching pattern; According to the address that obtains, insert 0 in the corresponding address in data so that data are recovered.
Preferably, recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively specifically comprises: data are divided into three circuit-switched data, wherein, three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output; According to the punching pattern, respectively each data in three circuit-switched data and its are sued for peace the legacy data on the address stored; To walk abreast with value and store the appropriate address of a plurality of memories into.
Preferably, dissociation rate matching method also comprises: when separating sub-block interleaving, to the zero clearing respectively of three circuit-switched data.
According to another aspect of the present invention, what a kind of limited length circulating buffer memory rate coupling also was provided separates the rate-matched device, and comprising: cache module is used for the rearrangement pattern parallel buffer input data according to sub-block interleaver; Processing module is used for the data of parallel buffer are carried out parallel processing; Output module is used to export data after the processing as the data of separating after the rate-matched.
Preferably, cache module is the ping-pong buffer module.
Preferably, processing module comprises: data recovery unit is used for the rearrangement mode producing punching pattern according to sub-block interleaver, and according to the punching pattern data is recovered; The data division unit is used for the data recovery unit recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively; Separate sub-block interleaving unit, be used for three circuit-switched data are walked abreast respectively and separate sub-block interleaving.
Preferably, the data division unit comprises: data are divided subelement, be used for data are divided into three circuit-switched data, wherein, three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output; The summation subelement is used for respectively each data in three circuit-switched data and its being sued for peace the legacy data on the address stored according to the punching pattern; Storing sub-units is used for storing the appropriate address of a plurality of memories into walking abreast with value.
Preferably, separate the rate-matched device and also comprise: the zero clearing unit is used for when separating sub-block interleaving, to the zero clearing respectively of three circuit-switched data.The rate-matched device of separating according to the embodiment of the invention only writes non-NULL value, and other parts are defaulted as 0, so require zero clearing as early as possible to guarantee to carry out fast the rate-matched of separating of next code block.
By means of above-mentioned at least one technical scheme of the present invention, by rearrangement pattern the input data are carried out parallel buffer according to sub-block interleaver, and data in buffer carried out parallel processing, thereby realized improving the throughput of separating rate-matched, shortened the technique effect of the time of separating the rate-matched process.
Description of drawings
Accompanying drawing is used to provide further understanding of the present invention, and constitutes the part of specification, is used from explanation the present invention with embodiments of the invention one, is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is a rate-matched block diagram of the prior art;
Fig. 2 is the flow chart according to the dissociation rate matching method of the limited length circulating buffer memory rate coupling of first embodiment of the invention;
Utilization shown in Figure 3 is according to the curve chart of the error rate of the dissociation rate matching method of first embodiment of the invention and the dissociation rate matching method in the correlation technique;
Fig. 4 is the schematic diagram according to the clear circuit of first embodiment of the invention;
The block diagram of separating the rate-matched device that Fig. 5 mates for the limited length circulating buffer memory rate according to second embodiment of the invention;
Fig. 6 is the entire block diagram of separating the rate-matched device according to the limited length circulating buffer memory rate coupling of third embodiment of the invention;
Fig. 7 is the schematic diagram according to the interleaving address generator of third embodiment of the invention;
Fig. 8 is crucial counting sequence figure in the punching pattern system bits, the first check digit interleaving address generator according to third embodiment of the invention;
Fig. 9 is according to crucial counting sequence figure in the punching pattern second check digit interleaving address generator of third embodiment of the invention;
Figure 10 is according to crucial counting sequence figure in the sub-block interleaving system bits of separating of third embodiment of the invention, the first check digit interleaving address generator;
Figure 11 is according to crucial counting sequence figure in the sub-block interleaving second check digit interleaving address generator of separating of third embodiment of the invention.
Embodiment
Below in conjunction with accompanying drawing the preferred embodiments of the present invention are described, should be appreciated that preferred embodiment described herein only is used for description and interpretation the present invention, and be not used in qualification the present invention.
In the following description, for the purpose of explaining, a plurality of specific details have been described, to provide to thorough of the present invention.Yet, obviously, do not having under the situation of these specific detail, also can realize the present invention, in addition, under the situation of not conflicting, promptly under the situation that does not deviate from the spirit and scope that claims illustrate, each details among following embodiment and the embodiment can be carried out various combinations.
First embodiment
Fig. 2 is the flow chart according to the dissociation rate matching method of the limited length circulating buffer memory rate coupling of first embodiment of the invention.As shown in Figure 2, the dissociation rate matching method according to the limited length circulating buffer memory rate of first embodiment of the invention coupling may further comprise the steps:
Step S202 is according to the rearrangement pattern parallel buffer input data of sub-block interleaver;
Step S204 carries out parallel processing to the data of parallel buffer;
Step S206, the data after the rate-matched are separated in the data conduct after output is handled.
In step S202, the reason that why will carry out metadata cache has following two: do not know the pattern that punches when one, beginning to separate rate-matched, therefore need earlier data to be carried out buffer memory that wait punching pattern calculates and finishes; Two, when being handled, data need in data, replenish NULL follow-up, if do not carry out the continuous processing that buffer memory can't guarantee data.Can carry out for example 4 tunnel parallel or 8 road parallel buffers for the input data.
Dissociation rate matching method according to the limited length circulating buffer memory rate of first embodiment of the invention coupling carries out parallel buffer by the rearrangement pattern according to sub-block interleaver to the input data, and data in buffer carried out parallel processing, thereby realized improving the throughput of separating rate-matched, shortened the technique effect of the time of separating the rate-matched process.
Preferably, the rearrangement pattern parallel buffer input data according to sub-block interleaver specifically comprise: according to the parallel ping-pong buffer input of the rearrangement pattern of sub-block interleaver data.Further improve throughput in the mode of utilizing ping-pong buffer.
Preferably, the data of parallel buffer are carried out parallel processing specifically comprise:, and data are recovered according to the punching pattern according to rearrangement mode producing punching pattern; Recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively; Three circuit-switched data are walked abreast respectively separate sub-block interleaving.Because the input of rate-matched is three circuit-switched data of Turbo coding output, therefore separates rate-matched and require output three circuit-switched data.
Preferably, according to the punching pattern data are recovered specifically to comprise:, obtain being in the data address of NULL according to the punching pattern; According to the address that obtains, insert 0 in the corresponding address in data so that data are recovered.
Preferably, recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively specifically comprises: data are divided into three circuit-switched data, wherein, three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output; According to the punching pattern, respectively each data in three circuit-switched data and its are sued for peace the legacy data on the address stored; To walk abreast with value and store the appropriate address of a plurality of memories into.
Because the input of rate-matched is three circuit-switched data of Turbo coding output, therefore separates rate-matched and require output three circuit-switched data.The way of storing is exactly that contrast punching pattern is stored in the content addition of valid data with the correspondence position of depositing on the correspondence position again, and NULL is owing to be by 0 replacement, and therefore 0+0=0 need not consider the storage of NULL, but corresponding address will be skipped.Processing method for repetition bits in the correlation technique has two kinds: (1) replaces former data SUB with new data; (2) directly abandon unnecessary data REJ.From information-theoretical angle analysis: (1) makes full use of the information of all receptions as far as possible; (2) emission diversity gain.Above-mentioned two kinds of ways all have losing of information, and all do not utilize and repeat to send the emission diversity gain of bit, and just can make full use of repetition bits according to the method for the embodiment of the invention, reach optimal performance.
Shown in Figure 3 is utilizes curve chart according to the error rate of the dissociation rate matching method ACC of the embodiment of the invention and dissociation rate matching method SUB in the correlation technique and REJ.The simulated conditions of Fig. 3 is that QPSK modulates, has the bit of half to carry out repeating sending, though very little according to the dissociation rate matching method gain of the embodiment of the invention for the precipitous code word in the such waterfall of Turbo district, still there is bigger performance to improve.
Preferably, dissociation rate matching method also comprises: when separating sub-block interleaving, to the zero clearing respectively of three circuit-switched data.Dissociation rate matching method according to the embodiment of the invention only writes non-NULL value, and other parts are defaulted as 0, so require zero clearing as early as possible to guarantee to carry out fast the rate-matched of separating of next code block.Dissociation rate matching method in the correlation technique concentrates on a period of time zero clearing usually, promptly loses time and wastes resource, also is that the dissociation rate matching method in the correlation technique is separated long reason of rate-matched time.And the method for taking real-time zero clearing in the present embodiment can shorten the time of separating rate-matched, reduces the power consumption of entire circuit.Clear circuit as shown in Figure 4.Though but this circuit is simple very effective.
Dissociation rate matching method according to the limited length circulating buffer memory rate of first embodiment of the invention coupling carries out parallel buffer by the rearrangement pattern according to sub-block interleaver to the input data, and data in buffer carried out parallel processing, thereby realized improving the throughput of separating rate-matched, shortened the time of separating the rate-matched process, the technique effect that reduces the error rate, reduction hardware circuit power consumption.
Second embodiment
The block diagram of separating the rate-matched device that Fig. 5 mates for the limited length circulating buffer memory rate according to second embodiment of the invention.As shown in Figure 5, the rate-matched device of separating according to the limited length circulating buffer memory rate of second embodiment of the invention coupling comprises: cache module 502 is used for the rearrangement pattern parallel buffer input data according to sub-block interleaver; Processing module 504 is used for the data of parallel buffer are carried out parallel processing; Output module 506 is used to export data after the processing as the data of separating after the rate-matched.
The rate-matched device of separating according to the limited length circulating buffer memory rate of second embodiment of the invention coupling carries out parallel buffer by the rearrangement pattern according to sub-block interleaver to the input data, and data in buffer carried out parallel processing, thereby realized improving the throughput of separating rate-matched, shortened the technique effect of the time of separating the rate-matched process.
Preferably, cache module is the ping-pong buffer module.Further improve throughput in the mode of utilizing ping-pong buffer.
Preferably, processing module comprises: data recovery unit is used for the rearrangement mode producing punching pattern according to sub-block interleaver, and according to the punching pattern data is recovered; The data division unit is used for the data recovery unit recovered data is divided into three circuit-switched data, and the storage that walks abreast respectively; Separate sub-block interleaving unit, be used for three circuit-switched data are walked abreast respectively and separate sub-block interleaving.Because the input of rate-matched is three circuit-switched data of Turbo coding output, therefore separates rate-matched and require output three circuit-switched data.
Preferably, the data division unit comprises: data are divided subelement, be used for data are divided into three circuit-switched data, wherein, three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output; The summation subelement is used for respectively each data in three circuit-switched data and its being sued for peace the legacy data on the address stored according to the punching pattern; Storing sub-units is used for storing the appropriate address of a plurality of memories into walking abreast with value.
Because the input of rate-matched is three circuit-switched data of Turbo coding output, therefore separates rate-matched and require output three circuit-switched data.The way of storing is exactly that contrast punching pattern is stored in the content addition of valid data with the correspondence position of depositing on the correspondence position again, and NULL is owing to be by 0 replacement, and therefore 0+0=0 need not consider the storage of NULL, but corresponding address will be skipped.Processing method for repetition bits in the correlation technique has two kinds: (1) replaces former data SUB with new data; (2) directly abandon unnecessary data REJ.From information-theoretical angle analysis: (1) makes full use of the information of all receptions as far as possible; (2) emission diversity gain.Above-mentioned two kinds of ways all have losing of information, and all do not utilize and repeat to send the emission diversity gain of bit, and just can make full use of repetition bits according to the method for the embodiment of the invention, reach optimal performance.
Preferably, separate the rate-matched device and also comprise: the zero clearing unit is used for when separating sub-block interleaving, to the zero clearing respectively of three circuit-switched data.The rate-matched device of separating according to the embodiment of the invention only writes non-NULL value, and other parts are defaulted as 0, so require zero clearing as early as possible to guarantee to carry out fast the rate-matched of separating of next code block.The rate-matched device of separating in the correlation technique concentrates on a period of time zero clearing usually, promptly loses time and wastes resource.Zero clearing in real time can be shortened the time of separating rate-matched, reduces the power consumption of entire circuit.
The rate-matched device of separating according to the limited length circulating buffer memory rate of second embodiment of the invention coupling carries out parallel buffer according to the rearrangement pattern of sub-block interleaver to the input data by utilizing cache module, and utilize processing module that data in buffer is carried out parallel processing, data after output is handled then, thereby realized improving the throughput of separating rate-matched, shortened the time of separating the rate-matched process, the technique effect that reduces the error rate, reduction hardware circuit power consumption.
The 3rd embodiment
Fig. 6 is the entire block diagram of separating the rate-matched device according to the limited length circulating buffer memory rate coupling of third embodiment of the invention.
As shown in Figure 6, separating in the rate-matched device that the limited length circulating buffer memory rate according to third embodiment of the invention mates, MEM 602 realizes the parallel buffer of input data, and in the present embodiment, data are 4 road parallel buffers.In addition, suppose that the rearrangement pattern of sub-block interleaver is as follows:
The analysis rearrangement pattern that interweaves can find that the above-mentioned row that interweave can be divided into four groups: 0,16,8,24,4,20,12,28; 2,18,10,26,6,22,14,30; 1,17,9,25,5,21,13,29; 3,19,11,27,7,23,15,31.So can store every road with four RAM, first RAM deposits 0,16,8,24,4, the information of 20,12,28 row, second RAM deposits 2,18,10, the information of 26,6,22,14,30 row, the 3rd RAM deposits 1,17,9,25,5,21, the information of 13,29 row, the 4th RAM deposits 3,19,11, the information of 27,7,23,15,31 row.Therefore, can easily realize 4 tunnel parallel processings, if RAM is a twoport, can realize easily that also 8 the tunnel is parallel, for example: the 4 tunnel when parallel, the rule that interweaves according to ranks, once Shu Ru four values are distributed in different four and list, according to column weight pattern of rows and columns, these four values are distributed among four different RAM, can realize that therefore four the tunnel is parallel.In like manner, can realize that also 8 the tunnel is parallel.
According to above analysis, this punching pattern is 12 RAM.System bits, check digit 1 and check digit 2 respectively corresponding four RAM, each RAM is that single-bit writes, four bits are read.These four RAM are storing 0,16,8,24,4,20,12,28 respectively; 2,18,10,26,6,22,14,30; 1,17,9,25,5,21,13,29; The positional information of the corresponding NULL of 3,19,11,27,7,23,15,31 row.If this position is NULL, then the value of this position is 1.The degree of depth of each RAM is K
w/ 12=R * C/4.Because no matter be the NULL that the Turbo coding produces, the NULL that adds when still interweaving all is positioned at each sub-interleaver foremost, according to the NULL number N of the interpolation of importing
FThe punching pattern interleaving address generator of (number of the NULL of first code block Turbo coding output) and N (filling the number of NULL when interweaving) and correspondence, can produce among 12 RAM the address of promising NULL.Punching pattern interleaving address generator as shown in Figure 7.In the present embodiment, the NULL of writing system position at first writes the NULL of check digit 1 again, is the NULL of check digit 2 at last.
The content that ROM deposits among Fig. 7 is＜0,4,2,6,1,5,3,7〉and, can replace with array for saving this ROM of resource.The multiple of the number of NULL if not 4, the one group of number that writes at last be with the spot patch foot, supplies rule to be: if having more 1 supply into: 1000, if having more two, then supply into: 1010, if having more three, then supply into: 1110.
Cunt1, Cunt2 counter are the core of this module at this moment, if system bits and check digit 1, then sequential relationship as shown in Figure 8; If during check digit 2, because address relationship needs cyclic shift 1, so first 1 is placed at last and handles, carry out according to the treating method of system bits fully the front, and last data that write is 0001, Cunt1=7, Cunt2=Row-1, corresponding sequential relationship as shown in Figure 9.In addition, above-mentioned cunt2 finally can count down to much going back and N+N
F, N is relevant.
Among Fig. 6, storage is the reception information of the system bits of Turbo coding output among the Sys 604; Storage is the reception information of the check digit 1 of Turbo coding output among the Parity0 606; Storage is the reception information of the check digit 2 of Turbo coding output among the Parity1 608.The method of storage is that contrast punching pattern is stored in the content addition of valid data with the correspondence position of depositing on the correspondence position again.Because NULL replaces by 0, thus need not consider the storage of NULL, but corresponding address will be skipped.At this moment, Sys, Parity0, Parity1 three tunnel all deposit with 4 RAM, store 0,16,8,24,4,20,12,28 respectively; 2,18,10,26,6,22,14,30; 1,17,9,25,5,21,13,29; The corresponding information of 3,19,11,27,7,23,15,31 row.Respectively these data are deposited among 12 corresponding RAM according to following rule: if k
0=0, then use 4-(k
0Mod4) the preceding 4-(k of individual 0 alternative four parallel-by-bit data of from MEM, reading
0Mod4) individual data, the pattern that punches are that replace with 0 the position of NULL, and corresponding data are passed backward, utilize the temporary data that do not have processing this moment of register.Should be noted that the punching pattern of not considering front benefit 0 this moment.Read four parallel datas then in order from MEM, and read the drawing information that interweaves from the pattern that interweaves, if NULL is arranged, then this position replaces by 0, and corresponding data are passed backward, utilizes the temporary data that do not have processing of register.In the time of write data original value read out and write after adding up with currency.If the address enters check digit, then at first take out 8 bit data in two moment and 8 punching patterns, mend into corresponding 0 according to the punching pattern, write operation with before be consistent.
The detailed structure of interleaving address generator 610 is that counter at this moment is different also as shown in Figure 7, and the interleaving address generator of punching pattern is to write NULL, and is that valid data are read now.Because the input of Turbo decoder needs three the tunnel, therefore need two interleaving address generators herein, one is used for reading of preceding two paths of data, and another is used for reading of Third Road data.Two counters still are the cores of this module, the crucial counting sequence of system bits and check digit 1 as shown in figure 10, the crucial counting sequence of check digit 2 is as shown in figure 11.Can consider and previous shared one road address generator of punching pattern interleaving address generator herein, reduce the hardware resource expense.
Among Fig. 6, clear circuit 612 is used for real-time zero clearing, to guarantee to carry out fast the rate-matched of separating of next code block.Can shorten the time of separating rate-matched by the real-time zero clearing of clear circuit 612 realizations, reduce the power consumption of entire circuit.The concrete structure of clear circuit can be as shown in Figure 4.In this circuit, the realization of zero clearing in real time is to write 0 on this address by reading of data the time to realize at once.Very effective though this circuit is simple, much other scheme is concentrated a period of time zero clearing, promptly loses time and wastes resource.
As mentioned above, by means of above-mentioned at least one technical scheme of the present invention, by rearrangement pattern the input data are carried out parallel buffer according to sub-block interleaver, and data in buffer carried out parallel processing, thereby realized improving the throughput of separating rate-matched, shortened the technique effect of the time of separating the rate-matched process.
The above is the preferred embodiments of the present invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (11)
1. the dissociation rate matching method of a limited length circulating buffer memory rate coupling is characterized in that, comprising:
Rearrangement pattern parallel buffer input data according to sub-block interleaver;
Described data to parallel buffer are carried out parallel processing;
The data after the rate-matched are separated in described data conduct after output is handled.
2. dissociation rate matching method according to claim 1 is characterized in that, imports data according to the rearrangement pattern parallel buffer input data parallel buffer memory of sub-block interleaver and specifically comprises:
The described input data of rearrangement pattern parallel buffer input data parallel ping-pong buffer according to sub-block interleaver.
3. dissociation rate matching method according to claim 1 is characterized in that, the described data of parallel buffer is carried out parallel processing specifically comprise:
According to described rearrangement mode producing punching pattern, and described data are recovered according to described punching pattern;
Described data after recovering are divided into three circuit-switched data, and the storage that walks abreast respectively;
Described three circuit-switched data are walked abreast respectively separate sub-block interleaving.
4. dissociation rate matching method according to claim 3 is characterized in that, according to described punching pattern described data is recovered specifically to comprise:
According to described punching pattern, obtain being in the described data address of NULL;
According to the described address that obtains, insert 0 in the corresponding address in described data so that described data are recovered.
5. dissociation rate matching method according to claim 3 is characterized in that, the described data after recovering are divided into three circuit-switched data, and the storage that walks abreast respectively comprises specifically:
Described data are divided into three circuit-switched data, and wherein, described three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output;
According to described punching pattern, respectively each data in described three circuit-switched data and its are sued for peace the legacy data on the address stored;
With the described and parallel appropriate address that stores a plurality of memories into of value.
6. dissociation rate matching method according to claim 3 is characterized in that, also comprises:
When separating sub-block interleaving, to the zero clearing respectively of described three circuit-switched data.
Limited length circulating buffer memory rate coupling separate the rate-matched device, it is characterized in that, comprising:
Cache module is used for the rearrangement pattern parallel buffer input data according to sub-block interleaver;
Processing module is used for the described data of parallel buffer are carried out parallel processing;
Output module is used to export described data after the processing as the data of separating after the rate-matched.
8. the rate-matched device of separating according to claim 7 is characterized in that described cache module is the ping-pong buffer module.
9. the rate-matched device of separating according to claim 7 is characterized in that described processing module comprises:
Data recovery unit is used for according to described rearrangement mode producing punching pattern, and according to described punching pattern described data is recovered;
The data division unit is used for the described data after the described data recovery unit recovery are divided into three circuit-switched data, and the storage that walks abreast respectively;
Separate sub-block interleaving unit, be used for described three circuit-switched data are walked abreast respectively and separate sub-block interleaving.
10. the rate-matched device of separating according to claim 9 is characterized in that, described data division unit comprises:
Data are divided subelement, are used for described data are divided into three circuit-switched data, and wherein, described three circuit-switched data correspond respectively to the system bits of Turbo coding output, first check digit of Turbo coding output, second check digit of Turbo coding output;
The summation subelement is used for according to described punching pattern, respectively each data in described three circuit-switched data and its is sued for peace the legacy data on the address stored;
Storing sub-units is used for the described and parallel appropriate address that stores a plurality of memories into of value.
11. the rate-matched device of separating according to claim 9 is characterized in that, also comprises:
The zero clearing unit is used for when separating sub-block interleaving, to the zero clearing respectively of described three circuit-switched data.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910151509 CN101938325B (en) | 2009-06-29 | 2009-06-29 | Rate de-matching method and device for finite length circular buffering rate matching |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200910151509 CN101938325B (en) | 2009-06-29 | 2009-06-29 | Rate de-matching method and device for finite length circular buffering rate matching |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101938325A true CN101938325A (en) | 2011-01-05 |
| CN101938325B CN101938325B (en) | 2012-12-19 |
Family
ID=43391478
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200910151509 Active CN101938325B (en) | 2009-06-29 | 2009-06-29 | Rate de-matching method and device for finite length circular buffering rate matching |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101938325B (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594490A (en) * | 2011-01-17 | 2012-07-18 | 中兴通讯股份有限公司 | Method and device for degradation rate matching |
| CN103368685A (en) * | 2012-04-01 | 2013-10-23 | 电信科学技术研究院 | Method and device for rate de-matching |
| CN103840912A (en) * | 2013-12-27 | 2014-06-04 | 北京星河亮点技术股份有限公司 | Method for rate dematching of LTE/LTE-A system traffic channel |
| CN103873188A (en) * | 2012-12-13 | 2014-06-18 | 中兴通讯股份有限公司 | Parallel rate de-matching method and parallel rate de-matching device |
| CN106452454A (en) * | 2015-08-04 | 2017-02-22 | 上海数字电视国家工程研究中心有限公司 | Data sequence exchange transmitting and receiving decoding method and device |
| CN104184541B (en) * | 2013-05-24 | 2018-12-18 | 中兴通讯股份有限公司 | A kind of LTE downlink dissociation rate matching method and device |
| CN109768843A (en) * | 2018-12-18 | 2019-05-17 | 京信通信系统（中国）有限公司 | Speed matching method, dissociation rate matching method, device and base station |
| CN110190934A (en) * | 2019-06-18 | 2019-08-30 | 普联技术有限公司 | A kind of method and apparatus of data punching |
| CN111600681A (en) * | 2020-05-15 | 2020-08-28 | 北京邮电大学 | Downlink bit level processing method based on FPGA hardware acceleration |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087181A (en) * | 2007-07-11 | 2007-12-12 | 中兴通讯股份有限公司 | A method for removing interweaving and speed match |
| CN101257663A (en) * | 2008-04-29 | 2008-09-03 | 北京天碁科技有限公司 | Method and device for implementing data velocity match and release velocity match |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE102005018982B4 (en) * | 2005-04-22 | 2009-02-19 | Schreck Kunststofftechnik Gmbh | Device for opening and closing injection nozzles in an injection molding tool |
-
2009
- 2009-06-29 CN CN 200910151509 patent/CN101938325B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101087181A (en) * | 2007-07-11 | 2007-12-12 | 中兴通讯股份有限公司 | A method for removing interweaving and speed match |
| CN101257663A (en) * | 2008-04-29 | 2008-09-03 | 北京天碁科技有限公司 | Method and device for implementing data velocity match and release velocity match |
Cited By (17)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102594490B (en) * | 2011-01-17 | 2014-11-05 | 中兴通讯股份有限公司 | Method and device for degradation rate matching |
| CN102594490A (en) * | 2011-01-17 | 2012-07-18 | 中兴通讯股份有限公司 | Method and device for degradation rate matching |
| CN103368685A (en) * | 2012-04-01 | 2013-10-23 | 电信科学技术研究院 | Method and device for rate de-matching |
| CN103368685B (en) * | 2012-04-01 | 2016-12-14 | 电信科学技术研究院 | Dissociation rate matching method and device |
| CN103873188B (en) * | 2012-12-13 | 2017-06-27 | 中兴通讯股份有限公司 | A kind of parallel dissociation rate matching method and device |
| CN103873188A (en) * | 2012-12-13 | 2014-06-18 | 中兴通讯股份有限公司 | Parallel rate de-matching method and parallel rate de-matching device |
| CN104184541B (en) * | 2013-05-24 | 2018-12-18 | 中兴通讯股份有限公司 | A kind of LTE downlink dissociation rate matching method and device |
| CN103840912B (en) * | 2013-12-27 | 2017-05-17 | 北京星河亮点技术股份有限公司 | Method for rate dematching of LTE/LTE-A system traffic channel |
| CN103840912A (en) * | 2013-12-27 | 2014-06-04 | 北京星河亮点技术股份有限公司 | Method for rate dematching of LTE/LTE-A system traffic channel |
| CN106452454A (en) * | 2015-08-04 | 2017-02-22 | 上海数字电视国家工程研究中心有限公司 | Data sequence exchange transmitting and receiving decoding method and device |
| CN106452454B (en) * | 2015-08-04 | 2019-09-27 | 上海数字电视国家工程研究中心有限公司 | Data change sequence and transmit and receive interpretation method and device |
| CN109768843A (en) * | 2018-12-18 | 2019-05-17 | 京信通信系统（中国）有限公司 | Speed matching method, dissociation rate matching method, device and base station |
| CN109768843B (en) * | 2018-12-18 | 2021-09-03 | 京信网络系统股份有限公司 | Rate matching method, rate de-matching method, device and base station |
| CN110190934A (en) * | 2019-06-18 | 2019-08-30 | 普联技术有限公司 | A kind of method and apparatus of data punching |
| CN110190934B (en) * | 2019-06-18 | 2022-02-18 | 普联技术有限公司 | Data punching method and equipment |
| CN111600681A (en) * | 2020-05-15 | 2020-08-28 | 北京邮电大学 | Downlink bit level processing method based on FPGA hardware acceleration |
| CN111600681B (en) * | 2020-05-15 | 2022-07-01 | 北京邮电大学 | Downlink bit level processing method based on FPGA hardware acceleration |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101938325B (en) | 2012-12-19 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101938325B (en) | Rate de-matching method and device for finite length circular buffering rate matching | |
| CN101540654B (en) | Method for interlacing rate matching and de-interlacing off-rate matching | |
| CN102447521B (en) | A kind of dissociation rate matching method and device | |
| CN101192833B (en) | A device and method for low-density checksum LDPC parallel coding | |
| CN101986584A (en) | Rate de-matching device and method in 3GPP LTE | |
| CN1130028C (en) | Viterbi decoding apparatus and viterbi decoding method | |
| CN100568745C (en) | Interleaver in the communication system and deinterleaving method | |
| CN102033854A (en) | Data storage method for sparse matrix and method for realizing SpMV based on same | |
| CN1365539A (en) | Matched filter using time-multiplexed procombinations | |
| CN101719810A (en) | Simulation generation method for parallel interleaver | |
| JP2005535190A5 (en) | ||
| CN101060374B (en) | Turbo coding stream processing device and method | |
| CN1105454C (en) | Data transposition system | |
| CN109889205A (en) | Encoding method and system, decoding method and system, and encoding and decoding method and system | |
| CN108288966A (en) | The rate-matched processing method and processing device of polarity Polar codes | |
| CN110278000A (en) | LDPC code parallel decoding FPGA based on DVB-S2 standard realizes framework and interpretation method | |
| CN102546082A (en) | Rate de-matching method and device | |
| CN102255687A (en) | Rate matching method and device thereof | |
| CN102111163B (en) | Turbo encoder and encoding method | |
| CN101944972B (en) | Coding and decoding method, device and communication system | |
| CN106603082A (en) | Universal high-speed LDPC code encoding method and encoder | |
| CN113222129A (en) | Convolution operation processing unit and system based on multi-level cache cyclic utilization | |
| CN102098126B (en) | Interleaving device, rating matching device and device used for block coding | |
| CN102468902B (en) | Method for Turbo coding of rate match/de-rate match in LTE (long term evolution) system | |
| CN101515805B (en) | Turbo encoder and encoding method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| EE01 | Entry into force of recordation of patent licensing contract |
Application publication date: 20110105 Assignee: SANECHIPS TECHNOLOGY Co.,Ltd. Assignor: ZTE Corp. Contract record no.: 2015440020319 Denomination of invention: Rate de-matching method and device for finite length circular buffering rate matching Granted publication date: 20121219 License type: Common License Record date: 20151123 |
|
| LICC | Enforcement, change and cancellation of record of contracts on the licence for exploitation of a patent or utility model | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20221027 Address after: 518055 Zhongxing Industrial Park, Liuxian Avenue, Xili street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: SANECHIPS TECHNOLOGY Co.,Ltd. Address before: 518057 No. 55 South Science and technology road, Shenzhen, Guangdong, Nanshan District Patentee before: ZTE Corp. |
|
| TR01 | Transfer of patent right |