CN101719810A - Simulation generation method for parallel interleaver - Google Patents

Abstract

The invention discloses a simulation generation method for a parallel interleaver, and belongs to the technical field of mobile wireless data transmission. The method is characterized by comprising the following steps: dividing an RAM into M independent access blocks, and setting the number of storage units of each block as W so as to acquire a block address (block number and in-block address) of each storage unit; equally dividing sequences to be interleaved into M sections in order, and setting the number of symbols of each section as W so as to acquire a section address (section number and in-section address) of each symbol; using the generated different random sequences as rows of interleaving patterns, and mapping the section number of each section address to the block number of the block address; on the basics, generating a basic interleaving vector according to the length of the memory, acquiring rows of interleaving patterns of different interleavers through cyclic shift for the basic interleaving vector, and mapping the in-section address of each section address to the in-block address of the corresponding block; and writing the symbols of the section address into the storage units of the corresponding block address, and synchronously reading the symbols out in address order. The method saves the storage resource and effectively reduces the time delay.

Description

A kind of simulation generation method of parallel interleaver

Technical field

The invention belongs to the mobile wireless data transmission technique field, particularly a kind of generation method of parallel interleaver.

Background technology

Interweaving is to carry out data processing in the communication system and a kind of technology of adopting, and interleaver is exactly a kind of device of realizing changing message structure to greatest extent and not changing the information content from essence.From tradition is exactly to make the error code discretization, makes the burst error channel become discrete mistake channel, and receiving terminal is corrected discrete at random mistake, thereby improves systematic function.

The function that interweaves, in essence, be exactly position, obtain the corresponding output signal sequence, and each symbol correspondence position in output signal sequence be exactly an interlacing pattern in this input signal sequence according to each symbol in certain mapping relations exchange input signal sequence.

The generation method of existing interlacing pattern mainly contains determinant block interleaved, spiral block interleaved, convolutional interleave, random interleaving etc., and the content and the characteristics of each method are respectively described below:

1. determinant block interleaved

The basic design philosophy of determinant block interleaved device i.e. " row goes into to list " or " listing row in goes out ".At first open up a rectangle memory space more than or equal to the length L of input signal sequence; Then, all symbols in the input signal sequence are write the procession exchange with line direction; At last, all symbols are read with column direction.Obtain interlacing pattern according to the position of input signal symbol in output signal sequence.

2. spiral block interleaved

Grouping spiral Design of Interleaver process is: at first open up a rectangle memory space more than or equal to the length L of input signal sequence; Then, all symbols in the input signal sequence are write the procession exchange with line direction; At last, burst is read with diagonal.Obtain interlacing pattern according to the position of each symbol of input signal sequence in output signal sequence.

3. convolutional interleave

The design process of convolutional deinterleaver is: at first, determine the time-delay symbol period that props up way B and each branch road that input signal sequence is divided into, wherein not time-delay of article one branch road, M symbol period of second branch road time-delay, article three, 2M symbol period of branch road time-delay,, B bar branch road time-delay (B-1) M symbol period; Then, each symbol of input signal sequence is entered B bar branch road in order respectively, press the beat of input simultaneously and export the delayed symbol of corresponding branch road respectively synchronously; At last, obtain interlacing pattern according to the position of each symbol of input signal sequence in output signal sequence.

4. random interleaving

The design process of convolutional deinterleaver is: at first, open up a memory space more than or equal to the length L of input signal sequence; Secondly, each symbol of burst to be interweaved writes this memory space in proper order; Then, determine the exponent number m and the primitive polynomial thereof of maximum length shift register code according to weaving length L, wherein the pass of L and m is L=2 ^m-1, the corresponding shift register in every rank; Then, by register shift, mould two and, operation such as read, all symbols in the burst are all read; At last, obtain interlacing pattern according to the position of each symbol of input signal sequence in output signal sequence.

From above-mentioned several Design of Interleaver methods as can be seen, for identical weaving length, in order to obtain different interlacing patterns: the line number that determinant block interleaved and spiral block interleaved need change the rectangle memory space is with columns or exchange different ranks; And convolutional interleave need change the delay cycle of a way B and each bar branch road, and they all must change hardware configuration could realize, so flexibility is not high enough; And random interleaving is to utilize maximum length shift register code itself as the address after interweaving, thereby the composition interlacing pattern, therefore, in case weaving length L fixes, the exponent number m of the maximum length shift register code that it is corresponding and primitive polynomial thereof are also just fixing, interlacing pattern is also just fixing like this, lacks flexibility.

In the wireless communication system, the reconciliation interleaving treatment that interweaves for all spread-spectrum code chips of finishing different user needs the interleaver information stores with each user in system.If adopt the method for designing of above-mentioned several interlacing patterns, long when interleaver sizes, when number of users was many, the information of storing all users' interleaver can take a large amount of internal memories, increase the complexity of system, generated also underaction of multiple different interlacing pattern; On the other hand, traditional multi-user's Iterative detection algorithm, because it is by chip iterative detection characteristic, time delay is bigger, the throughput of system is not high.

The reconciliation interlace operation that interweaves of parallelization can carry out parallel decoding easily, thereby can effectively reduce system's time delay.A kind of implementation method of the parallelization of interleaver is the RAM piece that the RAM memory is divided into a plurality of storages that can walk abreast.If different RAM pieces then can carry out access independently, therefore can carry out counting the access of similar number simultaneously at most with the RAM piece.

Yet different according to the dividing method of interlacing pattern and RAM piece sometimes can produce storage interference.So-called memory contention just is meant the operation of simultaneously data in the memory being read or writing at two or more parallel processors of same clock cycle.In order to solve the memory contention problem, to guarantee that the handled data of parallel decoding/despreading are from different memory blocks in the time of the design parallel interleaver.Therefore, satisfying under the certain condition, can design the interlacing pattern that conflict is avoided.

If but memory is divided into the M piece of parallel access, when M symbol from parallel decoder output and when being written to the different RAM pieces simultaneously, can under the situation that storage interference is avoided, make parallelization reach maximum.

Summary of the invention

The objective of the invention is to for overcoming the big deficiency of Multiuser Detection iterative decoding time delay, a kind of parallel interleaver method for designing of not having memory contention is proposed, can not only generate different interlacing patterns in real time according to a little information of storage, and, the interlace operation of parallelization, for parallel decoding has reduced time delay, effectively brought up to throughput of system.

Described method realizes in computer successively according to the following steps:

Step (1) is divided into memory a plurality of of energy independent access, the piece number is M, number of memory cells in every is W, thereby obtain the block address of described each memory cell, be expressed as { m, w} with array (address in the piece number, piece), again treating that interleaved sequence lines up the two-dimensional matrix of the capable W of M row by row major order, the row at each symbol place number and row number are the sector address of this symbol in the described interleaved sequence.Be expressed as { m ', w ' } with array (segment number, section in address), wherein, m ∈ 1,2 ..., M}, m ' ∈ 1,2 ..., M}, w ∈ 1,2 ..., W}, w ' ∈ 1,2 ..., W};

Step (2) is treated interleaved sequence to what above-mentioned two-dimensional matrix was arranged, adopts the sequence that generates at random as interlacing pattern in the row, and every row symbol is listed as interior rearrangement, and the segment number in each described sector address is reflected piece number in the described block address, and its step is as follows:

W the random seed that step (2.1) generates, and distribute to each row of parallel interleaver arbitrarily, described W sees the number of memory cells of each memory block in the step (1),

Each interleaver of step (2.2) generates W length according to the random seed that is assigned to and respectively is the random sequence of M, and guarantee each sequence be 0,1,2 ..., the random rearrangement of M-1};

The rearrangement of each symbol in step (2.3) is listed as follows: with the value of each element in the random sequence as row number, with the row at this element place as row number, be mapped in the symbol for the treatment of interleaved sequence of the interior two-dimensional arrangements of two-dimensional matrix in the step (1), the segment number of each sector address is written to piece number in the block address, to form the two-dimensional matrix for the treatment of interleaved sequence after resetting in the row, line number is M, and columns is W;

On the basis that step (3) is reset in step (2) realizes row, by to resetting in the every trade of whenever advancing, in the piece of relevant block in the address, its step is as follows section interior map addresses in described each sector address:

Step (3.1) adopts following relational expression π (i)=(f between input position index i and the outgoing position index π (i) according to the QPP interleaver in the 3Gpp Realse8 standard ₁I+f ₂i ²) modW, wherein constant f ₁, f ₂Obtaining by the value of searching the described number of memory cells W of Turbo code interleaver parameter list in the 3Gpp Realse8 standard, is the base of the W vector that interweaves thereby generated length;

Step (3.2) is carried out the cyclic shift of the regular length of different number of times k to the vector that interweaves of resulting base in the step (3.1) successively according to the sequence number of each interleaver in the described parallel interleaver, k=1,2, ..., W, displacement for the first time just obtains the interlacing pattern of first row of each described interleaver, again the interlacing pattern of each interleaver first row is carried out successively the cyclic shift of M-1 unit length, obtain M-1 the vector that interweaves, be combined into the capable interlacing pattern of described each interleaver

Step (3.3) makes up be expert at storage list after interweaving of each interleaver as follows: interweave the value of each component in the vector as row number with base described in step (3.3) the row interlacing pattern, capable number of the capable conduct at place, be mapped to the two-dimensional matrix for the treatment of interleaved sequence after resetting in the row in the step (2.3), the row at sector address place number is written in the memory cell at place, relevant block address, obtains be expert at storage list after interweaving of each interleaver;

Step (4) is read the data in each interleaver memory of step (3.3) successively by the row order, obtains the sequence of each interleaver.

Characteristics of the present invention and effect:

According to the present invention, for the number K of interleaver, interleaver degree of parallelism M, memory length W utilizes identical method, can obtain a plurality of interlacing patterns that carry out parallel work-flow in real time.Only store a little information, the base that just can generate the random sequence of resetting in being used to be listed as and be used for resetting in the row vector that interweaves.Only need carry out simple circulative shift operation, just can flexible, convenient, fastly obtain new interlacing pattern the base vector that interweaves.Not only saved memory space, and do not needed to change hardware configuration, algorithm complex is low, does not have complicated multiplication and division computing.

In addition, the present invention is a kind of parallel interleaver method for designing of no memory access conflict.In finishing row, go interior rearrangement again on the basis of rearrangement, be the equal of after allocation of symbols is arrived different memory blocks, be each allocation of symbols memory cell again in each memory block, read in turn by memory unit address from a plurality of symbols of different memory blocks at last, thereby satisfied the condition that no memory conflicts:

$\∀k,k^{\′}=\mathrm{1,2},...,L,k\≠k^{\′}$

k＝k′(modW)→M(k)≠M(k′)

k＝k′(modW)→M(π(k))≠M(π(k′))

It will interweave (deinterleaving) operate in concurrent carrying out between a plurality of memories, overcome traditional multi-user's iterative detection, particularly under the situation that number of users is big, by the big shortcoming of chip decoding delay, accelerated to interweave and the speed of parallel decoding, reduce time delay, effectively raised throughput of system.

The present invention can be used as the interior deinterleaving method of encoder in the communication system, also can be used as channel interleaving method, can also be as being the generation method of the address code (being the interlacing pattern of different user) of distinguishing the different user in the interlacing multi-address technology that different user adopts in the communication system.

Description of drawings

Fig. 1 is the flow chart of the parallel interlacing pattern generation method of the present invention.

Embodiment

The invention provides a kind of generation method of parallel interleaver pattern, the method comprises:

Step (1) but RAM is divided into a plurality of of independent access, the piece number is M, every number of memory cells is W, can obtain the block address (piece number, address in the piece) of each memory cell; To treat that interleaved sequence is divided into the M section in order, every section symbolic number is W, can arrive each sign field address (segment number, address in the section);

Step (2) rearranges in every row are listed as the interleaved sequence for the treatment of of above-mentioned two-dimensional arrangements, and the segment number in each sector address is mapped to piece number in the block address;

On the basis that step (3) is reset in realizing row, by to rearranging in the every trade of whenever advancing, with the interior map addresses of the section in each sector address in the piece of relevant block in the address;

Step (4) is written to the symbol at sector address place in the ram memory cell at place, relevant block address, and with the data in each RAM piece, reads simultaneously according to sequence of addresses;

In the described step (1), the row major two-dimensional arrangements of sequence to be interweaved, the sector address of each symbol are expressed as that (m, w), m, w represent the row number (segment number) and the row number (section in address) of this symbol place two-dimensional arrangements respectively.The block address of ram memory cell is (m ', w '), and m ', w ' represent address in the piece number of this memory cell place RAM piece and the piece respectively, m wherein, m ' ∈ 1,2 ..., M}w, w ' ∈ 1,2 ..., W}; Treat promptly that also (the individual symbol of i=(m-1) * W+w) is exactly j (j=(m '-1) * W+w ') the individual symbol of back in the sequence that interweave for i in the interleaved sequence.

In the described step (2) (3), the mapping from the sector address to the block address realizes by resetting for two steps in the heavy row and line in being listed as:

Reset in the row: (same row) symbol { a identical address in the section _{:, w}, according to segment number m, according to regular C _w(m) obtain waiting to deposit the piece m ' of RAM piece, i.e. m '=C _w(m).

Mapping from the segment number to the piece number is the equal of to treat that interleaved symbol has been assigned in the RAM piece of each independent access.For example the interleaved symbol that number is assigned to for the RAM piece of m ' of piece is $\{a_{C_1^{-1}\left(m^{\′}\right),1},a_{C_2^{-1}\left(m^{\′}\right),2},...,a_{C_W^{-1}\left(m^{\′}\right),W}\}.$

Reset in the row: in above-mentioned row, reset on the basis of finishing, to being assigned to the symbol of same RAM piece, according to address w in the section of this symbol, according to regular R _{M '}(w) obtain this symbol piece number for the piece in the RAM piece of m ' in address w ', i.e. w '=R _{M '}(w).

The mapping of address in from address in the section to piece is the equal of that the symbol that is assigned in the RAM piece is put into the corresponding memory cell of this RAM piece.

So far, finished treat the interleaved sequence sector address (m, but w) to the mapping of the RAM block address of independent access (m ', w '): (m, w) → (C _w(m), R _{M '}(w))

In the described step (4), the data in each RAM piece are read simultaneously, be meant the same clock cycle with piece in the data of the identical memory cell in address read simultaneously, finish parallel interlace operation.

To the mapping of segment number to piece number, i.e. rearrangement method C in the row _w(m), wherein a kind of implementation is to adopt the sequence that generates at random as interlacing pattern in the row;

Be that each interleaver distributes different random number seeds, interleaver k for example, according to the random seed that the is assigned to random sequence that to generate W length be M (element in each sequence from 1,2 ..., value among the M}, and different), as the interlacing pattern of each row;

To the mapping of address in the piece, address in the section, interlacing pattern generation method R at once _{M '}(w), can obtain the different vectors that interweaves (interlacing pattern) by the cyclic shift of sequence;

Generate the base vector that interweaves according to the length W of storage block RAM, the base vector that interweaves is carried out the cyclic shift of K regular length successively, obtain the first capable interlacing pattern of each interleaver; The first row interlacing pattern with each interleaver carries out (M-1) individual vector that interweaves that the cyclic shift of M-1 unit length obtains successively again.Constitute the capable interlacing pattern of M of this interleaver thus;

Describe technical scheme of the present invention in detail below in conjunction with the drawings and specific embodiments.

Parallel interleaver method for designing of the present invention, mapping from the sector address for the treatment of the interleaved sequence symbol to the memory block block address, be the equal of the length W that counts M and every according to memory block, after sequence before interweaving carried out the two-dimensional arrangements of the capable and W row of M by row major order, rearrange in being listed as pattern with random sequence earlier, rearrange in going by the interweave cyclic shift of vector of base again, obtain the interlacing pattern of a plurality of interleavers thus.

Comprise following several steps successively:

At first, initiation parameter: but the interleaver number that parallelization interweaves is K (also promptly needs generate interlacing pattern number); The sequence length N that at every turn interweaves; Degree of parallelism M, the length W of each memory block (then has N=M * W);

Then, but all can generate as follows the interlacing pattern that each parallelization interweaves:

Step (1) will be treated interleaved sequence by row major order, make the two-dimensional arrangements of the capable W row of M;

Step (2) is the interlacing pattern of the random sequence of M as every row with W the length that generates, and rearranges in being listed as;

Step (3) generates the base vector that interweaves according to the length W of memory again, to the base vectorial cyclic shift that interweaves, obtains the capable interlacing pattern of each interleaver, rearranges in going;

Step (4) is read the data in each memory block simultaneously by sequence of addresses, can obtain the sequence after the process parallelization interweaves.

Embodiment: present embodiment is interleaver number K=2, degree of parallelism M=4, treat the generation of interleaved sequence length N=24, the parallel interlacing pattern when obtaining memory length W=N/M=6 thus.Wherein, in the described step (3), the QPP interleaver among the 3GPP Realse8 is adopted in the interweave generation of vector of base, and input position index i and outgoing position index π (i) adopt following relational expression:

π(i)＝(f ₁i+f ₂i ²)modW，

Parameter f ₁And f ₂Depend on block size W, can obtain by searching Turbo code interleaver parameter list in the 3GPP Realse8 standard (such as when the W=40, f ₁=3, f ₂=10).

Signal Message Address sequence before setting interweaves is the sequence arrangement by 1-24, and the generation of its interlacing pattern comprises the steps:

Step (1) will be treated interleaved sequence by row major order, make the two-dimensional arrangements of 4 row, 6 row:

The interweave two-dimensional arrangements of presequence of table 1

Each interleaver of step (2) generates W=6 the random sequence that length is M=4 by random seed number separately, as the interlacing pattern of every row, shown in following table 2, table 3:

Interlacing pattern in the row of table 2 interleaver 1

The column interleaving pattern of table 3 interleaver 2

To each columns certificate of each two-dimensional arrangements, be listed as interior rearrangement then, obtain shown in following table 4, table 5 according to the column interleaving pattern:

Data after resetting in table 4 interleaver 1 row

Data after resetting in table 5 interleaver 2 row

Step (3) is according to the QPP interleaver among the 3GPP Realse8, and the input position index i of employing and outgoing position index π (i) relational expression are: π (i)=(f ₁I+f ₂i ²) modW.

Generating length and be 6 the base vector that interweaves is: π _Base=[4 0213 5], then first of the interleaver 1 row interlacing pattern is with respect to π _BaseCyclic shift length is: 3, and the first row interlacing pattern of interleaver 2 is with respect to π _IniCyclic shift length is: 6, then:

π _1，0＝{1，3，5，4，0，2}

π _2，0＝{4，0，2，1，3，5}

With π _1,0And π _2,0Each obtains the interlacing pattern of remaining triplex row through after unit length of 3 cyclic shifts.Thus, the parallel interlacing pattern that can obtain above-mentioned two interleavers is respectively:

π _1，0＝{1，3，5，4，0，2}

π _1，1＝{3，5，4，0，2，1}

π _1，2＝{5，4，0，2，1，3}

π _1，3＝{4，0，2，1，3，5}

π _2，0＝{4，0，2，1，3，5}

π _2，1＝{0，2，1，3，5，4}

π _2，2＝{2，1，3，5，4，0}

π _2，3＝{1，3，5，4，0，2}

The capable interlacing pattern of each interleaver is shown in table 6, table 7:

The capable interlacing pattern of table 6 interleaver 1

The capable interlacing pattern of table 7 interleaver 2

Press the capable interlacing pattern shown in table 6, the table 7, interweave in each every trade of advancing to storage list behind the column interleaving of each interleaver, just obtained being written to data in each memory cell of memory block, shown in table 8, table 9:

Storage list after table 8 interleaver 1 row interweaves

Storage list after table 9 user 2 row interweave

Step (4) is read the data in each interleaver memory successively by row, the sequence after can obtaining interweaving, and interleaver 1 transmitting terminal sequence is: { 20,20,12,17,19,3,4,18,11,1,9,2,24,23,7,15,8,10,5,13,21,14,16,6}, interleaver 2 transmitting terminal sequences are: { 12,8,16,21,5,19,14,10,3,23,7,24,22,9,17,13,18,20,15,11,25,6,2,4}.

In the method for designing of this parallel interleaver: the interlacing pattern generation method of rearrangement in the row also can be other random sequence production methods, as m serial method, linear congruential method, and is not limited to generation of random series method based on random seed; The interlacing pattern generation method of resetting in the row, wherein the length of the cyclic shift of basic interleaver also can adopt other definition; Generate more interlacing pattern as needs, also can adopt the mode that will be listed as interior interlacing pattern cyclic shift to distinguish different interleavers.

The foregoing description just is used to specify the generation method that interweaves of the present invention; concrete data wherein just arbitrarily are provided with for explanation; can not be in order to limit protection scope of the present invention; promptly as long as implement by the described step of this claim, wherein any variation of data all should belong to protection category of the present invention.

Claims (1)

1. the simulation generation method of a parallel interleaver is characterized in that, described method realizes in computer successively according to the following steps:

Step (1) is divided into memory a plurality of of energy independent access, the piece number is M, number of memory cells in every is W, thereby obtain the block address of described each memory cell, be expressed as { m, w} with array (address in the piece number, piece), again treating that interleaved sequence lines up the two-dimensional matrix of the capable W of M row by row major order, the row at each symbol place number and row number are the sector address of this symbol in the described interleaved sequence.Be expressed as { m ', w ' } with array (segment number, section in address), wherein, m ∈ 1,2 ..., M}, m ' ∈ 1,2 ..., M}, w ∈ 1,2 ..., W}, w ' ∈ 1,2 ..., W};

Step (2) is treated interleaved sequence to what above-mentioned two-dimensional matrix was arranged, adopts the sequence that generates at random as interlacing pattern in the row, and every row symbol is listed as interior rearrangement, and the segment number in each described sector address is reflected piece number in the described block address, and its step is as follows:

W the random seed that step (2.1) generates, and distribute to each row of parallel interleaver arbitrarily, described W sees the number of memory cells of each memory block in the step (1),

Each interleaver of step (2.2) generates W length according to the random seed that is assigned to and respectively is the random sequence of M, and guarantee each sequence be 0,1,2 ..., the random rearrangement of M-1};

The rearrangement of each symbol in step (2.3) is listed as follows: with the value of each element in the random sequence as row number, with the row at this element place as row number, be mapped in the symbol for the treatment of interleaved sequence of the interior two-dimensional arrangements of two-dimensional matrix in the step (1), the segment number of each sector address is written to piece number in the block address, to form the two-dimensional matrix for the treatment of interleaved sequence after resetting in the row, line number is M, and columns is W;

On the basis that step (3) is reset in step (2) realizes row, by to resetting in the every trade of whenever advancing, in the piece of relevant block in the address, its step is as follows section interior map addresses in described each sector address:

Step (3.1) adopts following relational expression π (i)=(f between input position index i and the outgoing position index π (i) according to the QPP interleaver in the 3Gpp Realse8 standard ₁I+f ₂i ²) modW, wherein constant f ₁, f ₂Obtaining by the value of searching the described number of memory cells W of Turbo code interleaver parameter list in the 3Gpp Realse8 standard, is the base of the W vector that interweaves thereby generated length;

Step (3.2) is carried out the cyclic shift of the regular length of different number of times k to the vector that interweaves of resulting base in the step (3.1) successively according to the sequence number of each interleaver in the described parallel interleaver, k=1,2, ..., W, displacement for the first time just obtains the interlacing pattern of first row of each described interleaver, again the interlacing pattern of each interleaver first row is carried out successively the cyclic shift of M-1 unit length, obtain M-1 the vector that interweaves, be combined into the capable interlacing pattern of described each interleaver

Step (3.3) makes up be expert at storage list after interweaving of each interleaver as follows: interweave the value of each component in the vector as row number with base described in step (3.3) the row interlacing pattern, capable number of the capable conduct at place, be mapped to the two-dimensional matrix for the treatment of interleaved sequence after resetting in the row in the step (2.3), the row at sector address place number is written in the memory cell at place, relevant block address, obtains be expert at storage list after interweaving of each interleaver;

Step (4) is read the data in each interleaver memory of step (3.3) successively by the row order, obtains the sequence of each interleaver.

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