CN110098891B - Interleaving method and interleaving apparatus - Google Patents
Interleaving method and interleaving apparatus Download PDFInfo
- Publication number
- CN110098891B CN110098891B CN201810087141.XA CN201810087141A CN110098891B CN 110098891 B CN110098891 B CN 110098891B CN 201810087141 A CN201810087141 A CN 201810087141A CN 110098891 B CN110098891 B CN 110098891B
- Authority
- CN
- China
- Prior art keywords
- cyclic shift
- sequence
- sequences
- bit
- interleaving
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Abstract
The application provides an interleaving method which can improve the random interleaving performance of interleaving equipment under the condition that the interleaving complexity is not increased. The method comprises the following steps: generating a first interleaving matrix according to the N first bit sequences, wherein the first matrix is l multiplied by l,
represents rounding up; performing first cyclic shift on the first matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer; performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2; obtaining N second bit sequences according to the third matrix; outputting the second bit sequence.
Description
Technical Field
The present application relates to the field of channel coding, and in particular, to an interleaving method and an interleaving apparatus.
Background
Digital communication systems generally employ channel coding to improve reliability of data transmission, wherein some channel coding employs an interleaving technique to further improve interference resistance during data transmission. On a plurality of composite channels with random errors and burst errors occurring at the same time, if an error occurs, a string of data is often involved, so that the burst errors exceed the error correction capability of the channel, and the error correction capability is reduced. If the burst error is firstly dispersed into random error and then the random error is corrected, the anti-interference performance of the system is further improved.
At present, the interleaving method is mainly divided into random interleaving and row-column interleaving according to the difference of the interleaving method. Random interleaving requires storing permutation sequences for interleaving and deinterleaving when calculating cyclic shift sequences offline, and under the condition of long code length, the storage resources required by random interleaving are very large and even unacceptable. And the error correction capability of the row-column interleaving for the reached errors is weak, and the error correction performance is poor.
Disclosure of Invention
The application provides an interleaving method and an interleaving device, which can improve the error correction performance under the condition of not increasing the interleaving complexity.
In a first aspect, the present application provides an interleaving method, including: obtaining N first bit sequences, wherein N is an integer;
generating a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l multiplied by l,
represents rounding up; performing first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer; performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2; obtaining N second bit sequences according to the third matrix; outputting the second bit sequence.
Compared with random interleaving, the interleaving method of the embodiment of the application has low interleaving complexity, but the interleaving performance is equivalent to or even better than the random interleaving performance. Therefore, error correction performance can be improved without increasing interleaving complexity.
With reference to the first aspect, in certain implementations of the first aspect, the method further includes:
and generating the second cyclic shift sequence according to the cyclic shift sequence.
With reference to the first aspect, in certain implementations of the first aspect, in implementations of the second aspect, the method specifically includes:
the bit value included in the second cyclic shift sequence is a multiple or fraction of the bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence.
With reference to the first aspect, in certain implementations of the first aspect, in implementations of the third aspect, the method specifically includes:
truncating S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception mode comprises any one of the following combinations: the method comprises the following steps of intercepting S bits from back to front according to the bit sequence, intercepting S bits from front to back according to the bit sequence, or intercepting S1 bits from back to front according to the bit sequence and intercepting S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer.
With reference to the first aspect, in certain implementations of the first aspect, in implementations of the fourth aspect, the method specifically includes:
truncating S cyclic shift sequences from the J first cyclic shift sequences in a manner including any combination of: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
and sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as a second cyclic shift sequence.
With reference to the first aspect, in certain implementations of the first aspect, in an implementation of the fifth aspect, the method specifically includes:
the first cyclic shift sequence and the second cyclic shift sequence may be obtained from L longest cyclic shift sequences configured in advance, J is smaller than L, S is smaller than L, and L is an integer.
Compared with random interleaving, the interleaving method of the embodiment of the application has low interleaving complexity, but the interleaving performance is equivalent to or even better than the random interleaving performance. Therefore, error correction performance can be improved without increasing interleaving complexity.
In a second aspect, an interleaving apparatus is provided for performing the first aspect and the method in any possible implementation manner of the first aspect. In particular, the apparatus comprises means for performing the method of the first aspect or any possible implementation manner of the first aspect.
In a third aspect, the present application provides an interleaving apparatus, comprising: one or more processors, one or more memories, one or more transceivers (each transceiver comprising a transmitter and a receiver). The transceiver is used for transmitting and receiving signals through the antenna. The memory is used to store computer program instructions (or code). The processor is configured to execute instructions stored in the memory, and when executed, the processor performs the method of the first aspect or any possible implementation manner of the first aspect.
In a fourth aspect, the present application provides a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to perform the method of the first aspect or any possible implementation manner of the first aspect.
In a fifth aspect, the present application provides a chip (or a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device in which the chip is installed performs the method in the first aspect and any one of the possible implementations of the first aspect.
In a sixth aspect, the present application provides a computer program product comprising: computer program code for causing a computer to perform the method of the first aspect and any one of its possible implementations described above, when said computer program code is run on a computer.
In a seventh aspect, the present application provides a coding apparatus having the function of implementing the method in the first aspect and any one of the possible implementation manners of the first aspect. These functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions. Furthermore, the encoding apparatus should have performance related to encoding, such as encoding, rate matching, and the like.
In one possible design, when part or all of the functions are implemented by hardware, the encoding apparatus includes: the input interface circuit is used for obtaining N first bit sequences, wherein N is an integer; a logic circuit configured to perform the interleaving method in any one of the possible designs of the first aspect and the first aspect thereof; and the output interface circuit is used for outputting the second bit sequence.
Alternatively, the encoding means may be a chip or an integrated circuit.
In one possible design, when part or all of the functions are implemented by software, the encoding means includes: a memory for storing a computer program; a processor configured to execute the computer program stored in the memory, wherein when the computer program is executed, the encoding apparatus may implement the interleaving method described in any one of the above first aspect and its possible designs.
In a possible design, when part or all of these functions are implemented by software, the coding means comprise a processor, a memory for storing the computer program being located outside the coding means, the processor being connected to the memory by means of circuits/wires for reading and executing the computer program stored in said memory.
Alternatively, the memory may be a physically separate unit or may be integrated with the processor.
It should be noted that the interleaving method described in the present application is performed by an interleaving apparatus for data and/or information. At the receiving end of the data and/or information, the received bit sequence needs to be deinterleaved. As is well known to those skilled in the art, deinterleaving is the inverse of interleaving. A de-interleaving method is easily available to a person skilled in the art on the basis of the interleaving method described in the above first aspect and any one of its possible implementations, and is not described in detail herein.
Furthermore, the present application provides an apparatus for deinterleaving, in particular, an apparatus for deinterleaving comprising means for performing the method for deinterleaving.
In addition, the present application also provides a de-interleaving apparatus comprising one or more processors, one or more memories, one or more transceivers (a transceiver comprises a transmitter and a receiver). The transmitter or the receiver transmits and receives signals through the antenna. The memory is used to store computer program instructions (or code). The processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs the method of deinterleaving.
Further, the present application provides a computer-readable storage medium having stored therein computer instructions, which when run on a computer, cause the computer to perform a method of deinterleaving.
The present application further provides a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform a method of deinterleaving.
The present application also provides a chip (or a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device in which the chip is installed executes an interleaving method in the method embodiments of the present application.
The present application also provides a decoding apparatus having a function of implementing the method of deinterleaving described in the embodiment of the present application. These functions may be implemented by hardware, or by hardware executing corresponding software. Besides, the decoding device also has the relevant functions of decoding, such as rate de-matching, decoding, and the like.
In the embodiment of the application, a simple and easy-to-operate interleaving method is provided, and the error correction performance can be improved under the condition that the interleaving complexity is not increased.
Drawings
Fig. 1 is a wireless communication system 100 suitable for use in embodiments of the present application.
Fig. 2 is a basic flow diagram for communication using wireless technology.
Fig. 3 is a flowchart of an interleaving method according to an embodiment of the present application.
Fig. 4 is a schematic diagram of another interleaving method according to an embodiment of the present application.
Fig. 5 is a schematic diagram of an interleaving apparatus 500 according to an embodiment of the present application.
Fig. 6 is a schematic configuration diagram of an interleaving apparatus 600 according to an embodiment of the present application.
Fig. 7 is a schematic structural diagram of a terminal device 700 according to an embodiment of the present application.
Detailed Description
The technical solution in the present application will be described below with reference to the accompanying drawings.
Fig. 1 is a wireless communication system 100 suitable for use in embodiments of the present application. At least one network device 101 may be included in the wireless communication system that communicates with one or more terminal devices (e.g., terminal device 102 and terminal device 102 shown in fig. 1). The network device 101 may be a base station, a device formed by integrating the base station with a base station controller, or other devices having similar communication functions.
The wireless communication system mentioned in the embodiments of the present application includes but is not limited to: narrowband Band-Internet of Things (NB-IoT), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (Code Division Multiple Access, CDMA2000), Time Division synchronous Code Division Multiple Access (Time Division-Synchronization Code Division Multiple Access, TD-SCDMA), Long Term Evolution (Long Term Evolution, LTE), triple-application scenarios eMBB, URLLC, eMTC of next generation 5G Mobile communication systems, or new communication systems emerging in the future.
The terminal devices referred to in the embodiments of the present application may include various handheld devices, vehicle mounted devices, wearable devices, computing devices, or other processing devices connected to a wireless modem with wireless communication capability. The terminal device may be a Mobile Station (MS), a subscriber unit (subscriber unit), a cellular phone (cellular phone), a smart phone (smart phone), a wireless data card, a Personal Digital Assistant (PDA) computer, a tablet computer, a wireless modem (modem), a handset (handset), a laptop (laptop computer), a Machine Type Communication (MTC) terminal, or the like.
The network device 101 in fig. 1 communicates with the terminal device using wireless technology. When the network device sends a signal, the network device is an interleaving device, and the terminal device is a receiving end. When the network device receives the signal, it is the receiving end, and the terminal device is the interleaving device.
Fig. 2 is a basic flow diagram for communication using wireless technology. The information source of the interleaving device is sent out on the channel after the information source coding, the channel coding, the rate matching and the modulation are carried out in sequence. After receiving the signal, the receiving end obtains the information sink through demodulation, rate de-matching, channel decoding and information source decoding in sequence.
Channel coding is one of the core technologies of wireless communication systems, and the improvement of performance will directly improve the network coverage and the user transmission rate. To improve the signal immunity to interference, interleaving techniques may further be introduced. The idea of interleaving is to separate the symbols in time and to convert a channel with memory into a channel without memory, so that the random error correction coding can also be applied to noisy burst channels.
Common interleaving methods include random interleaving and row-column interleaving. Random interleaving is superior in average performance, but due to the randomness of interleaving, it cannot be guaranteed that each interleaving has superior performance. And in the case of offline interleaving, a large number of permutation sequences need to be stored for interleaving and deinterleaving. When the code length is long, the storage resource required by random interleaving is large, which causes a large hardware load to the encoder, even is unacceptable. In addition, the complexity of random interleaving is high. While the scheme of row-column interleaving is simpler, the data randomization process is weaker, and the interleaving performance is not ideal.
Therefore, the application provides an interleaving method which can improve the error correction performance under the condition of not increasing the interleaving complexity. The following describes the interleaving method in the embodiment of the present application in detail.
Referring to fig. 3, fig. 3 is a flowchart of an interleaving method according to an embodiment of the present application.
310. The interleaving device obtains N first bit sequences.
The first bit sequence comprises N bits, wherein N is an integer.
320. The interleaving device generates a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l multiplied by l,
indicating rounding up.
330. And the interleaving equipment performs first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer.
Specifically, the method for generating the second cyclic shift sequence by the interleaving device is as follows: and generating the second cyclic shift sequence according to the cyclic shift sequence.
Further optionally, the method for generating the second cyclic shift sequence by the interleaving device is:
the bit value included in the second cyclic shift sequence is a multiple or fraction of the bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence; alternatively, the first and second electrodes may be,
truncating S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception mode comprises any one of the following combinations: intercepting S bits from back to front according to the bit sequence, intercepting S bits from front to back according to the bit sequence, or intercepting S1 bits from back to front according to the bit sequence and intercepting S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer; alternatively, the first and second electrodes may be,
truncating S cyclic shift sequences from the J first cyclic shift sequences in a manner including any combination of: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as second cyclic shift sequences; alternatively, the first and second electrodes may be,
the first cyclic shift sequence and the second cyclic shift sequence may be obtained from L longest cyclic shift sequences configured in advance, J is smaller than L, S is smaller than L, and L is an integer.
340. And performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is not less than 2.
350. And obtaining N second bit sequences according to the third matrix, and sending the second bit sequences.
360. Outputting the second bit sequence.
The interleaving device comprises an interleaving device, and specifically, the method is executed by the interleaving device; the interleaving device may be a network device or a terminal device.
In the embodiment of the application, a simple and easy-to-operate interleaving method is provided, and by performing row or column cyclic shift on a bit sequence to be interleaved and performing two consecutive cyclic shifts of the column or row cyclic shift on the bit sequence to be interleaved without increasing interleaving complexity, the performance after interleaving is close to the random interleaving performance, especially the performance close to a random interleaving device can be achieved under high-order modulation, and the error correction performance of a system is further improved; meanwhile, the scheme also belongs to a determined interweaving device and meets the design requirement of the interweaving device.
The following describes in detail the interleaving process of the interleaving apparatus to the cyclically shifted sequences in this embodiment with reference to fig. 4.
In the embodiment of the present invention, a row-column matrix is given as a square matrix, and a specific generation manner of cyclic shift sequences, such as a first bit sequence and a second bit sequence, is given, but the generation and initialization of an actual cyclic shift sequence may have various forms, and is not limited to the method described below in the embodiment.
Step 1: the interleaving device obtains N bit sequences to be interleaved, where N is an integer.
Step 2: the interleaving device sets the number of rows and columns of the interleaving device according to the N bit sequences to be interleaved, the number of rows and columns is equal,
marking as l; then
Indicating rounding up.
As shown in fig. 4, taking an example of an N-16 bit sequence to be interleaved, the interleaving device size is set to 4x4 according to the N, i.e., l-4.
And step 3: the interleaving device generates a first interleaving matrix according to a bit sequence to be interleaved, wherein the size of the first interleaving matrix is l multiplied by l.
As shown in (1) in fig. 4, here, the interleaving apparatus acquires the bit sequence to be interleaved as: x ═ 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 };
reading a bit sequence to be interleaved into interleaving equipment row by row or column by column according to a mode of one row of one bit or a mode of one column of one bit, and filling NULL bits in the rest positions; when reading out from the interleaving device, the NULL bits are skipped without reading, and then a first interleaving matrix of l × l is generated. As shown in fig. 4, the bits are read into the interleaving device row by row in such a way that 4 bits are read per row, and a first interleaving matrix, such as matrix (1) in fig. 4, is generated.
And 4, step 4: the interleaving device cyclically shifts the first interleaving matrix.
Specifically, a cyclic shift operation is performed on a bit sequence in the interleaving device according to a cyclic shift sequence:
first, generation of the cyclic shift sequence described above is described:
the cyclically shifted sequences include a first cyclically shifted sequence and a second cyclically shifted sequence, denoted as S and S', respectively.
Taking the number of bits to be interleaved N bits as an example,
(1) initializing specific elements in S, e.g. S1＝a,S2＝b；
(2) For Si: the calculation formula can be selected as: si＝(Si-1+Si-2)&l；3≤i≤l；
(3) The sequence S 'is the reverse order of S, i.e. S'i＝Sl-i+1；1≤i≤l。
The sequence S 'can be obtained by a new calculation formula, but when the interleaving matrix is a square matrix, the sequence S' is the reverse sequence of S or other variants, and the implementation is more convenient and simpler.
Taking N as 16 and X as {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}, cyclic shift sequences S, S' are generated according to the equations of steps (2) and (3):
(1) 1 for S1, 2 for S2; s3 ═ (S2+ S1) &4 ═ 3; s4 ═ S3+ S2) &4 ═ 1; i.e., S ═ {1,2,3,1 };
(2) s 'is the reverse of S, then S' ═ {1,3,2,1 };
secondly, the bits to be interleaved are cyclically shifted in rows and columns:
(1) according to the sequence S, circularly shifting the matrix (1) by rows to obtain a second matrix, such as the matrix (2) in FIG. 4;
(2) according to the sequence S', circularly shifting the matrix (2) by columns to obtain a third matrix, such as the matrix (3) in FIG. 4;
and 5: and the interleaving equipment reads the third matrix sequence in a row or column mode, skips over the NULL bit position and outputs the read bit sequence.
Taking the above N as an example of 16, when the third matrix is read out row by row, the output bit sequence X is {16,8,12,15,4,11,14,3,7,13,2,6,10,1,5,9 }.
The interleaving device includes an interleaving device, and the interleaving device may be a network device or a terminal device.
Specifically, the interleaving process of the interleaving device to be used for the cyclic shift sequence in the embodiment of the present application may also be as follows:
the present embodiment differs from the previous embodiments in that: the row-column matrix is not in the form of a square matrix, but the number of rows is multiple to the number of columns, so when one cyclic shift sequence is obtained, another cyclic shift sequence can be obtained through repetition or truncation according to the multiple relation or fractional relation.
Step 1: the interleaving equipment obtains N bit numbers to be interleaved;
step 2: and the interleaving equipment sets the size of the interleaving equipment as follows according to the N: the number of rows is r, the number of columns c is l times the number of rows,
c is l r, then
Represents rounding up;
and step 3: and the interleaving device reads bits to be interleaved row by row or column by column according to the size of the interleaving device r x c, fills NULL bits in the rest positions and generates a first interleaving matrix.
And 4, step 4: the interleaving device performs cyclic shift on the first interleaving matrix:
for example: performing cyclic shift with unequal length on the rows and the columns, and respectively recording shift sequences as S and S';
the cyclic shift sequence S, S' is calculated as follows, wherein:
(1) initializing a specific element in SA peptide; e.g. S1＝a,S2＝b；
(2) Calculating Si(ii) a For example, the calculation formula may be selected as: si＝(Si-1+Si-2)&l；3≤i≤l；
(3) The sequence S' is a repeated accumulation after the sequential transformation of S.
Optionally:
the cyclic shift sequence S, S' is calculated as follows, wherein:
(1) initializing a specific element in S';
(2) calculating S'i；
(3) The sequence S is the interception of S ', the interception mode can be that the sequence with the length of S is intercepted from back to front, or the cyclic shift sequence with the corresponding length is intercepted from front to back, or from a specific position, and then S' is obtained; alternatively, the first and second electrodes may be,
and intercepting from S, and then carrying out reverse order or other sequence transformation operation on the intercepted sequence to obtain S'.
And 5: the interleaving device cyclically shifts the first interleaving matrix.
Cyclically shifting the bits to be interleaved in rows and columns:
(1) according to the sequence S, circularly shifting the matrix (1) by rows to obtain a second matrix, such as the matrix (2) in FIG. 4;
(2) according to the sequence S', circularly shifting the matrix (2) by columns to obtain a third matrix, such as the matrix (3) in FIG. 4;
step 6: and the interleaving equipment reads the third matrix sequence in a row or column mode, skips over the NULL bit position and outputs the read bit sequence.
Specifically, the interleaving process of the interleaving device to be used for the cyclic shift sequence in the embodiment of the present application may also be as follows:
the present embodiment is different from the previous embodiments in that the maximum mother code length of the current control channel is considered to be defined as 1024 bits, and when the coded bits are greater than 1024, repetition coding is adopted to obtain the coded bits. Therefore, considering this case, it may be considered to design the longest available interleaving matrix or the longest cyclic shift sequence, and when the required cyclic shift sequence is smaller than the maximum interleaving matrix or the longest cyclic shift sequence for cyclic shift, the first cyclic shift sequence and the second cyclic shift sequence are truncated from the maximum interleaving matrix or the longest cyclic shift sequence. In addition, other related steps are the same as those in the above embodiment, and thus are not described again.
Further, specific examples are as follows:
first, the method of obtaining the maximum interleaving matrix is as follows:
1, setting the number of bits to be interleaved as Nmax, setting the size of interleaving equipment as r, c, r × c ═ Nmax;
2, setting the size of interleaving equipment as r × c, defining an interleaving matrix as A, reading bits to be interleaved into the interleaving equipment according to rows, and filling NULL bits in the rest positions;
secondly, the method for obtaining the required interleaving matrix is as follows:
1, setting the number of bits to be interleaved as N, setting the size of the interleaving device to be r1, c1 the number of columns, and r1 × c1> -N;
2, the size of interleaving equipment is r1 × c1, an interleaving matrix is defined as B, bits to be interleaved are read into the interleaving equipment according to rows, and NULL bits are filled in the rest positions;
the obtaining of the interleaving matrix B is obtained based on the matrix a, optionally, the matrix B may be an intercept from top to bottom and from left to right of the matrix a, optionally, the matrix B may be an intercept from bottom to top and from right to left of the matrix a, the matrix B may be an intercept from top to bottom and from right to left of the matrix a, the matrix B may be an intercept from bottom to top and from left to right of the matrix a, and the matrix B may be an intercept of a corresponding number of rows and columns starting from a specific position of the matrix a.
It should be noted that the above describes the obtaining of the cyclic shift sequence in the form of an interleaving matrix, and the matrix and the sequence are different in the representation manner, but are composed of bits and can be interchanged with each other.
For a process of performing the cyclic shift operation on the matrix, please refer to the further description of the above embodiment, which is not described herein again.
The embodiment of the application provides a simple and easy-to-operate interleaving method, which can perform row or column cyclic shift on a bit sequence to be interleaved and perform two successive cyclic shifts of the row or row cyclic shift on the bit sequence to be interleaved under the condition of not increasing interleaving complexity, so that the performance after interleaving is close to the random interleaving performance, especially the performance close to a random interleaving device can be achieved under high-order modulation, and the error correction performance of a system is further improved; meanwhile, the scheme also belongs to a determined interweaving device and meets the design requirement of the interweaving device.
The process of the interleaving method according to the embodiment of the present application is described in detail above with reference to fig. 1 to 4, and the interleaving apparatus according to the embodiment of the present application is described below.
Fig. 5 is a schematic diagram of an interleaving apparatus 500 according to an embodiment of the present application. As shown in fig. 5, the apparatus 500 includes a receiving unit 500, a processing unit 520, and a transmitting unit 530. Wherein the content of the first and second substances,
a receiving unit 510, configured to obtain N first bit sequences, where N is an integer;
a processing unit 520, configured to generate a first interleaving matrix according to the N first bit sequences, where the first interleaving matrix is l × l,
represents rounding up; performing first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer; performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2; obtaining N second bit sequences according to the third matrix;
a transmitting unit 530, configured to transmit the second bit sequence.
The units in the apparatus 500 of the embodiments of the present application and the other operations or functions described above are respectively for implementing the interleaving methods in the embodiments of the present application. For brevity, no further description is provided herein.
The interleaving device of the embodiment of the application can improve the error correction performance under the condition of not increasing the interleaving complexity.
Fig. 6 is a schematic configuration diagram of an interleaving apparatus 600 according to an embodiment of the present application. As shown in fig. 6, the apparatus 600 includes: one or more processors 601, one or more memories 602, one or more transceivers 603. The processor 601 is configured to control the transceiver 603 to transmit and receive signals, the memory 602 is configured to store a computer program, and the processor 601 is configured to call and run the computer program from the memory 602, so that the interleaving apparatus 600 performs the corresponding processes and/or operations of the embodiments of the interleaving method. For brevity, no further description is provided herein.
It should be noted that the interleaving apparatus 500 shown in fig. 5 can be implemented by the interleaving device 600 shown in fig. 6. For example, the receiving unit 510 and the transmitting unit 530 may be implemented by the transceiver 603 in fig. 6. The processing unit 520 may be implemented by the processor 601, etc.
The interleaving device may be a network device or a terminal device shown in fig. 1. In uplink transmission, the interleaving device is specifically a terminal device, and the terminal device has a function of implementing the interleaving method described in each embodiment. These functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions. In downlink transmission, the interleaving device is specifically a network device (e.g., a base station), and the network device has a function of implementing the interleaving method described in each of the above embodiments. Likewise, these functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more units corresponding to the above functions.
When the interleaving device 600 is embodied as a terminal device, the structure of the terminal device may be as shown in fig. 7. Fig. 7 is a schematic structural diagram of a terminal device 700 according to an embodiment of the present application.
As shown in fig. 7, the terminal device 700 includes: a transceiver 708 and a processing device 704. The terminal device 700 may also include a memory 719, and a memory 819 for storing computer instructions.
A transceiver 708 configured to obtain N first bit sequences, where N is an integer.
A processor 704 configured to generate a first interleaving matrix according to the N first bit sequences, where the first interleaving matrix is l × l,
represents rounding up; performing first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer; performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2; obtaining N second bit sequences according to the third matrix;
a transceiver 708, configured to transmit the second bit sequence according to the indication of the processing apparatus 704.
Further, the processing means 704 may be configured to perform the actions implemented inside the interleaving device described in the previous method embodiment, and the transceiver 708 may be configured to perform the receiving or transmitting actions of the interleaving device described in the previous method embodiment. Please refer to the description of the previous embodiment of the method, which is not repeated herein.
The processing device 704 and the memory 719 can be integrated into a processor, and the processor is configured to execute the program codes stored in the memory 719 to implement the functions described above. In particular, the memory 719 may be integrated into the processor.
The terminal device 700 may also include a power supply 812 for providing power to various components or circuits within the terminal device 700. The terminal device 700 may include an antenna 710 for transmitting data or information output by the transceiver 808 via wireless signals.
In addition, in order to further improve the functions of the terminal apparatus 800, the terminal apparatus 800 may further include one or more of an input unit 714, a display unit 716, an audio circuit 718, a camera 720, a sensor 722, and the like. The audio circuitry may also include a speaker 7182, a microphone 7184, and the like.
It should be noted that the interleaving method provided in the embodiment of the present application may be applied to various channel codes, for example, LDPC codes, Turbo codes, polarization (Polar) codes, and the like. The embodiments of the present application do not limit this.
In addition, the interleaving method provided by the application can be used as a single interleaving module for realizing interleaving processing. The method can also be used as a mode for reading bits during rate matching, so that the interleaving and the rate matching can be integrated together for realization, an interleaving module does not need to be designed separately, and the same error correction performance as random interleaving can be achieved.
The interleaving method according to the embodiment of the present application is also applicable to interleaving of symbol (symbol) sequences, and those skilled in the art can also apply the interleaving method to interleaving of symbol sequences according to the method for interleaving bit sequences described above, and will not be described in detail herein.
Further, the present application provides a computer-readable storage medium having stored therein instructions, which when run on a computer, cause the computer to perform the interleaving method in the above-described embodiments.
The present application further provides a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform the interleaving method described in the above embodiments.
The present application also provides a chip including a memory for storing a computer program and a processor for calling and running the computer program from the memory so that a communication device in which the chip is installed performs the interleaving method described in the above embodiments.
The communication device may be a network device or a terminal device.
The present application also provides an encoding apparatus having a function of implementing the interleaving method described in the above embodiment. These functions may be implemented by hardware, or by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions. Besides, the coding device also has the relevant function of realizing coding. After the coding device codes the sequence to be coded, the coded sequence is interleaved by adopting the interleaving method of the embodiment of the application. Or, the encoding apparatus may also apply the interleaving method of the embodiment of the present application to rate matching, so that an interleaving module may be omitted, but the same effect of improving error correction performance may be achieved.
In one possible design, when part or all of the functions are implemented by hardware, the encoding apparatus includes:
an input interface circuit for obtaining a first bit sequence;
a logic circuit for performing the interleaving method described in the above embodiments. The method is specifically used for: generating a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l multiplied by l,
represents rounding up; performing first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer; performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2; obtaining N second bit sequences according to the third matrix;
an output interface circuit for outputting the second bit sequence;
alternatively, the encoding means may be a chip or an integrated circuit.
In one possible design, when part or all of the functions are implemented by software, the encoding means includes: a memory for storing a computer program; a processor for executing a memory-stored computer program that when executed, the encoding apparatus may implement the interleaving method as set forth in any one of the possible designs of the above embodiments.
In one possible design, the encoding means includes a processor when part or all of these functions are implemented in software. The memory for storing the computer program is located outside the encoding device, and the processor is connected with the memory through a circuit/wire for reading and executing the computer program stored in the memory.
It should be noted that the interleaving method described in the present application is performed by an interleaving apparatus for data and/or information. At the receiving end of the data and/or information, the received bit sequence needs to be deinterleaved. As is well known to those skilled in the art, deinterleaving is the inverse of interleaving. A de-interleaving method is easily available to a person skilled in the art on the basis of the interleaving method described in the above first aspect and any one of its possible implementations, and is not described in detail herein.
Correspondingly, the application provides a deinterleaving device, which is used for realizing corresponding functions in the deinterleaving method. These functions may be implemented by hardware, or by hardware executing corresponding software.
Further, the present application provides a computer-readable storage medium having stored therein computer instructions, which when run on a computer, cause the computer to perform a method of deinterleaving.
The present application further provides a computer program product comprising: computer program code which, when run on a computer, causes the computer to perform a method of deinterleaving.
The present application also provides a chip (or a chip system) including a memory and a processor, where the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that a communication device in which the chip is installed executes an interleaving method in the method embodiments of the present application.
A de-interleaving apparatus is provided that includes one or more processors, one or more memories, one or more transceivers (each transceiver including a transmitter and a receiver). The transmitter or the receiver transmits and receives signals through the antenna. The memory is used to store computer program instructions (or code). The processor is configured to execute instructions stored in the memory, and when the instructions are executed, the processor performs the method of deinterleaving.
The present application also provides a decoding apparatus having a function of implementing the method of deinterleaving described in the embodiment of the present application. These functions may be implemented by hardware, or by hardware executing corresponding software. Besides, the decoding device also has the relevant functions of decoding, such as rate de-matching, decoding, and the like.
Alternatively, the memory and the storage described in the above embodiments may be physically separate units, or the memory and the processor may be integrated together.
In the above embodiments, the processor may be a Central Processing Unit (CPU), a microprocessor, an Application-Specific Integrated Circuit (ASIC), or one or more Integrated circuits for controlling the execution of the program in the present Application. For example, a processor may be comprised of a digital signal processor device, a microprocessor device, an analog to digital converter, a digital to analog converter, and so forth. The processor may distribute the control and signal processing functions of the mobile device between these devices according to their respective functions. Further, the processor may include functionality to operate one or more software programs, which may be stored in the memory.
The functions of the processor can be realized by hardware, and can also be realized by hardware executing corresponding software. The hardware or software includes one or more modules corresponding to the above-described functions.
The Memory may be a Read-Only Memory (ROM) or other type of static storage device that may store static information and instructions, a Random Access Memory (RAM) or other type of dynamic storage device that may store information and instructions. But is not limited to, Electrically Erasable Programmable Read-Only Memory (EEPROM), Compact Disc Read-Only Memory (CD-ROM) or other optical disk storage, optical disk storage (including Compact Disc, laser disk, optical disk, digital versatile disk, blu-ray disk, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a computer.
In conjunction with the foregoing description, those skilled in the art will recognize that the methods of the embodiments herein may be implemented in hardware (e.g., logic circuitry), or software, or a combination of hardware and software. Whether such methods are performed in hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
When the above functions are implemented in the form of software and sold or used as a separate product, they may be stored in a computer-readable storage medium. In this case, the technical solution of the present application or a part of the technical solution that contributes to the prior art in essence may be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method described in the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.
Claims (13)
1. An interleaving method, comprising:
obtaining N first bit sequences, wherein N is an integer;
generating a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l multiplied by l,
represents rounding up;
performing first cyclic shift on the first interleaving matrix according to a first cyclic shift sequence to obtain a second matrix, wherein the first cyclic shift sequence comprises J bits, and J is more than or equal to 2 and is an integer;
performing second cyclic shift on the second matrix according to a second cyclic shift sequence to obtain a third matrix, wherein the second cyclic shift sequence comprises S bits, and S is an integer and is greater than or equal to 2;
obtaining N second bit sequences according to the third matrix;
outputting the second bit sequence;
wherein the method further comprises:
generating the second cyclic shift sequence according to the cyclic shift sequence;
the method specifically comprises the following steps:
truncating S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception includes any one of the following: according to the bit sequence, truncating S bits from back to front, truncating S bits from front to back according to the bit sequence, or truncating S1 bits from back to front according to the bit sequence and truncating S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, S2 is an integer, or truncating S1 bits from back to front according to the bit sequence and truncating S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer;
or
Truncating S cyclic shift sequences from the J first cyclic shift sequences in a manner including any one of: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
and sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as a second cyclic shift sequence.
2. The method according to claim 1, characterized in that it comprises in particular: the bit value included in the second cyclic shift sequence is a multiple or fraction of the bit value corresponding to the first cyclic shift sequence, or the second cyclic shift sequence is obtained by sequentially transforming the first cyclic shift sequence.
3. The method of claim 1, wherein the first cyclically shifted sequence and the second cyclically shifted sequence are obtained from L longest cyclically shifted sequences configured in advance, J is smaller than L, S is smaller than L, and L is an integer.
4. An interleaving apparatus, comprising:
the input interface circuit is used for obtaining N first bit sequences, wherein N is an integer;
a logic circuit for generating a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l x l,
an output interface circuit for outputting the second bit sequence;
wherein the logic circuit is further configured to generate the second cyclically shifted sequence according to the cyclically shifted sequence;
wherein the content of the first and second substances,
the logic circuit is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception includes any one of the following: intercepting S bits from back to front according to the bit sequence, and intercepting S bits from front to back according to the bit sequence, or intercepting S1 bits from back to front according to the bit sequence and intercepting S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer;
alternatively, the first and second electrodes may be,
the logic circuit is specifically configured to intercept S cyclic shift sequences from the J first cyclic shift sequences, where the interception includes any one of the following manners: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
and sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as a second cyclic shift sequence.
5. The apparatus of claim 4, wherein the logic circuit is specifically configured to cause the second cyclically shifted sequence to include bit values that are multiples or fractions of bit values corresponding to the first cyclically shifted sequence, or to cause the second cyclically shifted sequence to be obtained by sequentially transforming the first cyclically shifted sequence.
6. The apparatus of claim 4, wherein the logic circuit is specifically configured to obtain the first cyclic shift sequence from L longest cyclic shift sequences configured in advance; and acquiring the second cyclic shift sequence from L longest cyclic shift sequences configured in advance, wherein J is less than L, S is less than L, and L is an integer.
7. An interleaving apparatus, characterized in that the apparatus comprises:
a processor for generating a first interleaving matrix according to the N first bit sequences, wherein the first interleaving matrix is l x l,
wherein the processor is further configured to generate the second cyclically shifted sequence according to the cyclically shifted sequence;
wherein the processor is specifically configured to truncate S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception includes any one of the following: intercepting S bits from back to front according to the bit sequence, intercepting S bits from front to back according to the bit sequence, or intercepting S1 bits from back to front according to the bit sequence and intercepting S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer;
alternatively, the first and second electrodes may be,
wherein the processor is specifically configured to truncate S cyclic shift sequences from the J first cyclic shift sequences, where the truncation includes any one of: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
and sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as a second cyclic shift sequence.
8. The apparatus of claim 7, wherein the processor is specifically configured to include a bit value of a multiple or fraction of a bit value corresponding to the first cyclically shifted sequence in the second cyclically shifted sequence, or to sequentially transform the first cyclically shifted sequence.
9. The apparatus of claim 7, wherein the processor is specifically configured to obtain the first cyclically shifted sequence from L longest cyclically shifted sequences configured in advance; and acquiring the second cyclic shift sequence from L longest cyclic shift sequences configured in advance, wherein J is less than L, S is less than L, and L is an integer.
10. An interleaving apparatus, characterized in that the apparatus comprises:
a receiving unit, configured to receive N first bit sequences, where N is an integer;
a processing unit, configured to generate a first interleaving matrix according to the N first bit sequences, where the first interleaving matrix is l × l,
a transmitting unit configured to output the second bit sequence;
wherein the processing unit is further configured to generate the second cyclic shift sequence according to the cyclic shift sequence;
the processor is specifically configured to truncate S cyclic shift sequences from the J first cyclic shift sequences as the second cyclic shift sequence; the interception includes any one of the following: intercepting S bits from back to front according to the bit sequence, intercepting S bits from front to back according to the bit sequence, or intercepting S1 bits from back to front according to the bit sequence and intercepting S2 bits from front to back according to the bit sequence, wherein S1+ S2 is S, S1 is an integer, and S2 is an integer;
or
The processor is specifically configured to truncate S cyclic shift sequences from the J first cyclic shift sequences, where the truncation includes any one of: intercepting S cyclic shift sequences from back to front according to the bit sequence, and intercepting S cyclic shift sequences from front to back according to the bit sequence;
and sequentially transforming the S intercepted cyclic shift sequences, and taking the S sequentially transformed cyclic shift sequences as a second cyclic shift sequence.
11. The apparatus of claim 10, wherein the processor is specifically configured to include a bit value of a multiple or fraction of a bit value corresponding to the first cyclically shifted sequence in the second cyclically shifted sequence, or to sequentially transform the first cyclically shifted sequence.
12. The apparatus of claim 10, wherein the processor is specifically configured to obtain the first cyclically shifted sequence from L longest cyclically shifted sequences configured in advance; and acquiring the second cyclic shift sequence from L longest cyclic shift sequences configured in advance, wherein J is less than L, S is less than L, and L is an integer.
13. A storage medium characterized by storing a program capable of implementing the method of any one of claims 1 to 3 when executed by a computer device.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810087141.XA CN110098891B (en) | 2018-01-30 | 2018-01-30 | Interleaving method and interleaving apparatus |
| PCT/CN2019/073575 WO2019149180A1 (en) | 2018-01-30 | 2019-01-29 | Interleaving method and interleaving device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810087141.XA CN110098891B (en) | 2018-01-30 | 2018-01-30 | Interleaving method and interleaving apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110098891A CN110098891A (en) | 2019-08-06 |
| CN110098891B true CN110098891B (en) | 2021-09-07 |
Family
ID=67442308
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810087141.XA Active CN110098891B (en) | 2018-01-30 | 2018-01-30 | Interleaving method and interleaving apparatus |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN110098891B (en) |
| WO (1) | WO2019149180A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110445582B (en) * | 2019-08-12 | 2020-10-23 | 广东工业大学 | Code interleaving method, system, device and computer readable storage medium |
| CN112910473B (en) * | 2019-12-04 | 2024-01-26 | 中国科学院上海高等研究院 | Block interleaving method and system based on cyclic shift |
| CN114268410B (en) * | 2020-09-16 | 2023-10-31 | 中国科学院上海高等研究院 | Interleaving method, system, equipment and computer storage medium based on cyclic shift |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1492589A (en) * | 1997-07-30 | 2004-04-28 | 三星电子株式会社 | Engine encoder and channel encoding method |
| CN101047393A (en) * | 2006-05-12 | 2007-10-03 | 华为技术有限公司 | Method for generating interlever/de-interleaver and its application |
| CN101594212A (en) * | 2008-05-30 | 2009-12-02 | 上海贝尔阿尔卡特股份有限公司 | The data repeating method and the device thereof that adopt interlacing rule to reset in the communication system |
| CN101719810A (en) * | 2009-11-13 | 2010-06-02 | 清华大学 | Simulation generation method for parallel interleaver |
| CN101911504A (en) * | 2007-11-26 | 2010-12-08 | 索尼公司 | Data process device and data process method |
| CN102355271A (en) * | 2011-10-31 | 2012-02-15 | 南京邮电大学 | Coding/decoding method of random row/column cyclic shift interleaver |
| CN106059974A (en) * | 2012-01-19 | 2016-10-26 | 松下电器产业株式会社 | Transmission method, transmitter, reception method, and receiver |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP2879318A1 (en) * | 2013-11-29 | 2015-06-03 | Panasonic Corporation | Efficient component interleaving for rotated constellations with time-frequency slicing |
| CN106936541B (en) * | 2015-12-30 | 2019-12-17 | 上海东软载波微电子有限公司 | RS coding and byte interleaving method and system |
-
2018
- 2018-01-30 CN CN201810087141.XA patent/CN110098891B/en active Active
-
2019
- 2019-01-29 WO PCT/CN2019/073575 patent/WO2019149180A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1492589A (en) * | 1997-07-30 | 2004-04-28 | 三星电子株式会社 | Engine encoder and channel encoding method |
| CN101047393A (en) * | 2006-05-12 | 2007-10-03 | 华为技术有限公司 | Method for generating interlever/de-interleaver and its application |
| CN101911504A (en) * | 2007-11-26 | 2010-12-08 | 索尼公司 | Data process device and data process method |
| CN101594212A (en) * | 2008-05-30 | 2009-12-02 | 上海贝尔阿尔卡特股份有限公司 | The data repeating method and the device thereof that adopt interlacing rule to reset in the communication system |
| CN101719810A (en) * | 2009-11-13 | 2010-06-02 | 清华大学 | Simulation generation method for parallel interleaver |
| CN102355271A (en) * | 2011-10-31 | 2012-02-15 | 南京邮电大学 | Coding/decoding method of random row/column cyclic shift interleaver |
| CN106059974A (en) * | 2012-01-19 | 2016-10-26 | 松下电器产业株式会社 | Transmission method, transmitter, reception method, and receiver |
Non-Patent Citations (1)
| Title |
|---|
| On PDCCH structure;Ericsson;《3GPP TSG-RAN WG1 AH-1801》;20180126;全文 * |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2019149180A1 (en) | 2019-08-08 |
| CN110098891A (en) | 2019-08-06 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109861694B (en) | Processing method and equipment of polarization code | |
| CN109075799B (en) | Coding and decoding method and device for Polar codes | |
| RU2691885C2 (en) | Method of matching rate of polar code and device for matching speed of polar code | |
| CN110113132B (en) | Coding and decoding method and terminal | |
| CN107078748A (en) | The coding method of polar code and code device | |
| CN108880566B (en) | Polar code transmission method and device | |
| CN110098891B (en) | Interleaving method and interleaving apparatus | |
| US11139918B2 (en) | Interleaving method and interleaving apparatus | |
| CN110690941B (en) | Polar code rate matching method and device | |
| US11362760B2 (en) | Polar code rate matching method and apparatus | |
| CN111385059B (en) | Method and apparatus for polar coded modulation | |
| KR20170094285A (en) | Data processing method, apparatus and device | |
| EP3734874B1 (en) | Coding mode indication method and device | |
| CN114079530A (en) | Encoding method and device | |
| EP3641139A1 (en) | Interleaving processing method and device for polar codes | |
| CN109391353B (en) | Method and device for rate matching | |
| CN108574562B (en) | Data transmission method and device | |
| CN109787707B (en) | Interleaving method and interleaving apparatus | |
| CN111525980B (en) | Decoding method and device | |
| CN109150200B (en) | Channel interleaving method and device | |
| CN110167154B (en) | Method for transmitting uplink signal, communication device and computer readable storage medium | |
| CN109088698B (en) | Coding method and communication equipment | |
| CN116711243A (en) | Interleaver for constellation shaping | |
| KR20190073489A (en) | Data processing method and transmitting device | |
| CN111490797B (en) | Encoding method, device and equipment |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |