CN111490797B

CN111490797B - Encoding method, device and equipment

Info

Publication number: CN111490797B
Application number: CN201910087281.1A
Authority: CN
Inventors: 张朝阳; 郑灯; 秦康剑; 张韵梅; 于天航
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-01-29
Filing date: 2019-01-29
Publication date: 2022-07-22
Anticipated expiration: 2039-01-29
Also published as: CN111490797A

Abstract

The embodiment of the application provides a coding method, a device and equipment, wherein the method comprises the following steps: acquiring N bits to be coded, wherein the N bits to be coded comprise K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is less than or equal to N; acquiring a generating matrix of the N bits to be coded; determining the position of the information bit according to the linear independent measurement between the row vectors in the generating matrix; and coding the bit to be coded according to the position of the information bit. The reliability of the encoding is improved.

Description

Coding method, device and equipment

Technical Field

The present application relates to the field of communications technologies, and in particular, to a coding method, apparatus, and device.

Background

In the field of communications technologies, a communication device (e.g., a terminal device, a base station, etc.) may perform channel coding and decoding by means of a Polar code (Polar code).

In the prior art, a polar code is usually constructed in a manner based on the reliability of a subchannel, and the construction manner based on the reliability of the subchannel includes a Gaussian Approximation (GA) manner, a Polarization Weight (PW) manner, and the like. However, the above-mentioned manner of constructing the polar code can optimize the performance under Serial Cancellation (SC) Decoding, but cannot optimize the performance of Serial Cancellation List (SCL) Decoding and hierarchical statistical Decoding (OSD) Decoding, which results in poor performance of the conventional coding method.

Disclosure of Invention

The application provides a coding method, a coding device and coding equipment, which improve the reliability of coding.

In a first aspect, an embodiment of the present application provides an encoding method, where the method includes: acquiring N bits to be coded, wherein the N bits to be coded comprise K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is less than or equal to N; acquiring a generating matrix of N bits to be coded; determining the position of an information bit according to the linear irrelevant measurement between the row vectors in the generated matrix; and coding the bits to be coded according to the positions of the information bits.

In the process, the position of the information bit is determined according to the linear independence measurement between the row vectors in the generating matrix, so that the possibility of linear independence between the row vectors in the generating matrix corresponding to the position of the information bit is high, the probability of SCL decoding error and the probability of OSD decoding error are low, and the reliability of coding is improved.

In one possible implementation, the linearly independent measure is a linearly independent probability.

In one possible implementation, the position of the information bit may be determined according to a linear independence metric between the row vectors in the generator matrix by the following feasible implementation: initializing a first position set, wherein the initialized first position set comprises a row sequence number of a row vector with the maximum row weight in a generating matrix; initializing a second position set, wherein the initialized second position set comprises at least one row sequence number; and determining the position of the information bit according to the linear independence measurement between the row vector corresponding to each row sequence number in the second position set in the generated matrix and the row vector corresponding to the row sequence number in the first position set in the generated matrix.

In the above process, the initialized first position set includes the row sequence number of the row vector with the largest row weight in the generating matrix, and the row sequence number corresponding to the row vector with the largest possibility of linear independence between the row vectors corresponding to the row sequence numbers in the first position set in the second position set is sequentially moved to the first position set, so that the code weight of the row vector in the generating matrix corresponding to the row sequence number in the first position set is larger, and the possibility of linear independence between the row vectors in the generating matrix corresponding to the row sequence number in the first position set is maximum, that is, the possibility of linear independence between the row vectors corresponding to the information bits in the generating matrix is maximum, and thus, the SCL decoding error probability is smaller and the OSD decoding error probability is smaller, and further, the encoding reliability is improved.

In a possible implementation manner, the initialized second location set includes a row sequence number corresponding to the K + L subchannels with the highest reliability; wherein, L is the reserved path number of the serial cancellation list SCL decoding, and the reserved path number is the maximum path number reserved in each step of decoding in SCL decoding.

In the above process, since the second location set includes the row sequence number corresponding to the K + L sub-channels with the highest reliability, and the row sequence number in the first location set is selected from the initialized second location set, the reliability of the sub-channel corresponding to the row sequence number in the first location set is higher, and further, the reliability of the sub-channel corresponding to the information bit is higher, so that the reliability of the encoding is higher.

In one possible embodiment, the K + L subchannels are the K + L subchannels with the highest reliability among the N subchannels.

In a possible implementation manner, the K + L subchannels are K + L subchannels with the highest reliability among the N-X subchannels, where X is the number of row sequence numbers included in the initialized first location set, and the N-X subchannels are subchannels except subchannels corresponding to the row sequence numbers in the first location set among the N subchannels. In this way, the line sequence numbers included in the initialized first location set and the initialized second location set may be made not to be repeated, thereby avoiding performing unnecessary operations.

In one possible implementation, the generated matrix is a polar code matrix of bits to be encoded, and the polar code matrix comprises N rows and N columns; the initialized first position set comprises sequence numbers of rows with row weights larger than a first Hamming distance in the generator matrix; the first Hamming distance is the maximum value of the minimum Hamming distances when the information bits and the fixed bits are arranged according to different modes, the information bits and the fixed bits are arranged according to a mode and correspond to one minimum Hamming distance, the minimum Hamming distance when the information bits and the fixed bits are arranged according to a mode is the minimum row weight of a row corresponding to the information bits in the generated matrix when the information bits and the fixed bits are arranged according to the mode.

In the above process, the line weight of the line corresponding to the line sequence number included in the initialized first position set may be made larger, so that the encoding performance is made higher.

In a possible embodiment, the initialized second location set comprises sequence numbers of rows in the generator matrix with row weights equal to the first hamming distance. In this way, the line weight of the line corresponding to the line sequence number included in the initialized second position set can be made larger, so that the line weight of the line corresponding to the line sequence number selected in the first position set is also made higher, and further, the encoding performance is made higher.

In one possible embodiment, the initialized second set of locations includes all row numbers in the generator matrix; alternatively, the initialized second set of locations includes a row sequence number in the generator matrix in addition to the row sequence number in the initialized first set of locations.

In a possible implementation, determining the position of the information bit according to a linear independence metric between the row vector corresponding to each row sequence number in the second position set in the generator matrix and the row vector corresponding to the row sequence number in the first position set in the generator matrix includes:

performing a first operation, the first operation comprising: determining a target row sequence number in the current second position set according to the linear independence measurement between the row vector corresponding to each row sequence number in the current second position set in the generated matrix and the row vector corresponding to the row sequence number in the current first position set in the generated matrix; in the current second position set, the linear independence measure between the row vector in the generating matrix corresponding to the target row sequence number and the row vector corresponding to the row sequence number in the current first position set in the generating matrix is the largest;

performing a second operation, the second operation comprising: adding the target row sequence number to the current first position set to obtain a new first position set, and deleting the target row sequence number in the current second position set to obtain a new second position set;

and repeatedly executing the first operation and the second operation until the new first position set comprises K row sequence numbers, and determining the row sequence number in the current first position set as the position of the information bit.

In the above process, it can be ensured that the row number with the largest linear independent metric of the row vector corresponding to the row number in the first position set in the second position set is added to the first position set, so that the linear independent metric of the row vector corresponding to the row number in the first position set is the largest, and the reliability of the encoding is higher.

In one possible embodiment, adding the target row sequence number to the current first location set and deleting the target row sequence number in the current second location set includes: when Y is larger than Z, Z target row serial numbers are determined in the Y target row serial numbers, Y is the number of the target row serial numbers, Z is K-T, T is the number of the row serial numbers in the current first position set, Y is an integer larger than 1, and Z is a positive integer smaller than or equal to K; and adding the Z target row serial numbers to the current first position set, and deleting the Z target row serial numbers in the current second position set.

In the above process, the maximum number of row numbers included in the first position set may be K, and the number of row numbers included in the first position set is avoided to be greater than K.

In a possible implementation manner, the Z target row serial numbers are row serial numbers corresponding to Z subchannels with the highest reliability in the Y target row serial numbers; or the Z target row serial numbers are the Z row serial numbers with the largest row serial number in the Y target row serial numbers; or the Z target row serial numbers are the Z row serial numbers with the smallest row serial number in the Y target row serial numbers.

In one possible embodiment, the information bits comprise cyclic redundancy check, CRC, bits and/or parity check, PC, bits.

In a second aspect, an embodiment of the present application provides an encoding apparatus, including:

a first obtaining module, configured to obtain N bits to be encoded, where the N bits to be encoded include K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is less than or equal to N;

a second obtaining module, configured to obtain a generator matrix of the N bits to be encoded;

a determining module, configured to determine a position of the information bit according to a linear independence metric between row vectors in the generator matrix;

and the coding module is used for coding the bits to be coded according to the positions of the information bits.

In one possible embodiment, the linearly independent measure is a linearly independent probability.

In a possible implementation, the determining module is specifically configured to:

initializing a first position set, wherein the initialized first position set comprises a row sequence number of a row vector with the maximum row weight in the generating matrix;

initializing a second position set, wherein the initialized second position set comprises at least one row sequence number;

and determining the position of the information bit according to the linear independence measurement between the row vector corresponding to each row sequence number in the second position set in the generating matrix and the row vector corresponding to the row sequence number in the first position set in the generating matrix.

In a possible implementation manner, the initialized second location set includes a row sequence number corresponding to the K + L subchannels with the highest reliability;

and L is the reserved path number of the serial cancellation list SCL decoding, and the reserved path number is the maximum path number reserved for each step of decoding in the SCL decoding.

In a possible implementation manner, the K + L subchannels are K + L subchannels with the highest reliability among the N subchannels; alternatively, the first and second electrodes may be,

the K + L sub-channels are K + L sub-channels with the highest reliability in N-X sub-channels, where X is the number of row sequence numbers included in the initialized first location set, and the N-X sub-channels are sub-channels of the N sub-channels except sub-channels corresponding to the row sequence numbers in the first location set.

In a possible implementation, the generating matrix is a polar code matrix of the bits to be encoded, and the polar code matrix includes N rows and N columns;

the initialized first position set comprises sequence numbers of rows with row weights larger than a first Hamming distance in the generator matrix; the first hamming distance is a maximum value of minimum hamming distances when the information bits and the fixed bits are arranged in different manners, the information bits and the fixed bits are arranged in a manner corresponding to one minimum hamming distance, the minimum hamming distance when the information bits and the fixed bits are arranged in a manner is a minimum line repetition of a line corresponding to an information bit in the generator matrix when the information bits and the fixed bits are arranged in the manner.

In a possible implementation, the initialized second location set includes sequence numbers of rows in the generator matrix with row weights equal to the first hamming distance.

In a possible embodiment, the initialized second location set includes all row numbers in the generator matrix; alternatively, the first and second electrodes may be,

the initialized second location set includes a row sequence number in the generator matrix except for a row sequence number in the initialized first location set.

In one possible embodiment, the determining module is configured to:

performing a first operation, the first operation comprising: determining a target row sequence number in the current second position set according to a linear independence measure between a row vector corresponding to each row sequence number in the current second position set in the generated matrix and a row vector corresponding to a row sequence number in the current first position set in the generated matrix; in the current second position set, the linear independence metric between the row vector corresponding to the target row sequence number in the generating matrix and the row vector corresponding to the row sequence number in the current first position set in the generating matrix is the largest;

and repeatedly executing the first operation and the second operation until the new first position set comprises K line sequence numbers, and determining the line sequence number in the current first position set as the position of the information bit.

In one possible embodiment, the determining module is configured to:

when Y is larger than Z, Z target row serial numbers are determined in the Y target row serial numbers, Y is the number of the target row serial numbers, Z is K-T, T is the number of the row serial numbers included in the current first position set, Y is an integer larger than 1, and Z is a positive integer smaller than or equal to K;

and adding the Z target row serial numbers to the current first position set, and deleting the Z target row serial numbers in the current second position set.

In a possible implementation manner, the Z target row sequence numbers are row sequence numbers corresponding to Z subchannels with the highest reliability in the Y target row sequence numbers; alternatively, the first and second electrodes may be,

the Z target row serial numbers are Z row serial numbers with the largest row serial number in the Y target row serial numbers; alternatively, the first and second electrodes may be,

and the Z target row serial numbers are the Z row serial numbers with the minimum row serial number in the Y target row serial numbers.

In a third aspect, an embodiment of the present application provides an encoding apparatus, including: memory, a processor and a computer program, the computer program being stored in the memory, the processor running the computer program to perform the method according to any of the first aspect.

In a fourth aspect, the present application provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the method according to any one of the first aspect.

The encoding method, the encoding device and the encoding equipment are characterized in that N bits to be encoded are obtained firstly, the N bits to be encoded comprise K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is smaller than or equal to N; acquiring a generating matrix of N bits to be coded; determining the position of information bits according to the linear irrelevant measurement between the row vectors in the generated matrix; and coding the bits to be coded according to the positions of the information bits. In the above process, the position of the information bit is determined according to the linear independence measure between the row vectors in the generator matrix, so that the probability of the linear independence between the row vectors in the generator matrix corresponding to the position of the information bit is higher, the probability of the SCL decoding error and the probability of the OSD decoding error are lower, and the reliability of the coding is improved.

Drawings

Fig. 1 is an architecture diagram of a communication system provided in an embodiment of the present application;

fig. 2 is a flow chart of channel transmission according to an embodiment of the present application;

fig. 3 is a schematic flow chart of an encoding method provided in the present application;

fig. 4 is a schematic flowchart of determining the position of an information bit according to the present application;

FIG. 5 is a schematic diagram of a simulation provided herein;

FIG. 6 is a schematic diagram of a simulation provided herein;

FIG. 7 is a schematic diagram of a simulation provided herein;

fig. 8 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present application;

fig. 9 is a schematic hardware structure diagram of an encoding apparatus according to an embodiment of the present application.

Detailed Description

The embodiment of the present application may be applied to various fields adopting Polar coding, for example: the field of data storage, the field of optical network communication, the field of wireless communication, and the like. The wireless communication system mentioned in the embodiments of the present application includes, but is not limited to: narrowband Band-Internet of Things (NB-IoT), Global System for Mobile Communications (GSM), Enhanced Data rates for GSM Evolution (EDGE), Wideband Code Division Multiple Access (WCDMA), Code Division Multiple Access (Code Division Multiple Access, CDMA2000), Time Division synchronous Code Division Multiple Access (Time Division-synchronous Code Division Multiple Access, emtd-SCDMA), Long Term Evolution (Long Term Evolution, LTE), and the next generation 5G Mobile Communication systems' triple application scenario Mobile broadband (Enhanced Mobile broadband Band, eMBB), Ultra-Reliable and Low Latency Communication (Ultra-wide Communication, mtc) and mtc large-scale Communication (llc-mtc). Of course, the field of using Polar coding may be other, and the present application is not limited to this.

The communication device related to the present application mainly includes a network device or a terminal device. The sending device in the present application may be a network device, and the receiving device is a terminal device. In the present application, the sending device is a terminal device, and the receiving device is a network device.

In the embodiment of the present application, a Terminal device (Terminal device) includes, but is not limited to, a Mobile Station (MS), a Mobile Terminal (MT), a Mobile phone (MT), a handset (handset), and a portable device (portable equipment), and the Terminal device may communicate with one or more core networks through a Radio Access Network (RAN). For example, the terminal device may be a mobile telephone (or "cellular" telephone), a computer with wireless communication capabilities, etc., and the terminal device may also be a portable, pocket, hand-held, computer-included, or vehicle-mounted mobile device or apparatus.

In this embodiment of the application, the Network device may be an evolved Node B (eNB) or an eNodeB in an LTE system, or the Network device may be a gNB or a Transmission and Reception Point (TRP), a micro base station, or the like in a 5G communication system, or the Network device may be a relay station, an access point, a vehicle-mounted device, a wearable device, a Network device in a Public Land Mobile Network (PLMN) for future evolution, or a Network in which other technologies are converged, or a base station in other various evolved networks, or the like.

For example, the network device may be a Base Station (BS) which may provide communication services to a plurality of Mobile Stations (MSs), and the Base Station may be further connected to a core network device. Wherein, the base station includes a Baseband Unit (BBU) and a Remote Radio Unit (RRU). BBU and RRU can be placed in different places, for example: RRU is remote and placed in an area with high telephone traffic, and BBU is placed in a central machine room. The BBU and the RRU can also be placed in the same machine room. The BBU and RRU may also be different components under one chassis.

Fig. 1 is an architecture diagram of a communication system according to an embodiment of the present application. Referring to fig. 1, a transmitting device 101 and a receiving device 102 are included.

Optionally, when the sending device 101 is a terminal device, the receiving device 102 is a network device. When the sending device 101 is a network device, the receiving device is a terminal device.

Referring to fig. 1, the sending device 101 includes an encoder therein, and the sending device 101 may perform encoding by the encoder and transmit the encoded sequence to the receiving device 102 through a channel. The receiving device 102 includes a decoder, and the receiving device can decode the received sequence through the decoder.

It should be noted that fig. 1 illustrates an architecture diagram of a communication system by way of example only, and does not limit the architecture diagram of the communication system.

Fig. 2 is a flowchart of channel transmission according to an embodiment of the present disclosure. Referring to fig. 2, a transmitting device performs source coding and channel coding on transmitted data, and the coded sequence is transmitted to a receiving device on a channel after being subjected to mapping modulation. The receiving device may perform demapping demodulation processing, channel decoding processing, and source decoding processing on the received sequence to recover the data sent by the sending device.

Because the current coding method cannot enable the SCL decoding performance and the OSD decoding performance to be optimal, the coding method provided by the application can improve the SCL decoding performance and the OSD decoding performance. For the sake of understanding of the present application, the OSD decoding method, the OSD decoding error probability, the SCL decoding method, and the SCL decoding error probability will be explained first.

The OSD decoding process may include the steps of:

step one, obtaining a receiving sequence, and sequencing the receiving sequence in a descending order according to the reliability of the hard judgment value of each bit to be decoded in the receiving sequence to obtain a first sequence y₁And determining a first transformation operation matrix (or transformation operation vector) lambda of the received sequence into a first sequence₁。

Alternatively, the received sequence may be a set of log-Likelihood ratios (LLRs), and one bit to be decoded may be one LLR.

Optionally, the hard decision value of the bit to be decoded is 0 or 1. For example, if the bit to be decoded (LLR) is greater than 0, the hard decision value of the bit to be decoded may be 0, and if the bit to be decoded (LLR) is less than 0, the hard decision value of the bit to be decoded is 1.

Alternatively, the reliability of the hard decision value of the bit to be decoded may be an absolute value of the bit to be decoded (LLR).

For example, assuming that the received sequence is L1(LLR1, LLR2, LLR3, LLR4) and the first sequence is L2(LLR4, LLR1, LLR2, LLR3), the first transformation operation matrix may be:

that is to say that the temperature of the molten steel,

the first transformation operation matrix may also be (4,1,2,3), and the elements in the first transformation operation matrix indicate the sorting mode in the received sequence, and as known from the first transformation operation matrix, the 4 th element in the received sequence is sorted to the 1 st bit, and the 4 th element in the received sequence is sorted to the 1 st bitThe 1 st element of (b) is arranged to the 2 nd bit, the 2 nd element of the received sequence is arranged to the 3 rd bit, and the 2 nd element of the received sequence is arranged to the 4 th bit.

And step two, performing column conversion on a generating matrix corresponding to the receiving sequence according to the first conversion operation matrix to obtain a first matrix G1.

In the OSD decoding, the number of rows included in the generator matrix is the same as the number of information bits, and the rows in the generator matrix correspond to the positions of the row information bits.

For example, assuming that the bits to be coded include K information bits and N-K fixed bits, the generated matrix in the OSD decoding includes a row corresponding to the position of the information bit in an N × N matrix (including N rows and N columns), that is, the generated matrix in the OSD decoding is a K × N matrix (including K rows and N columns).

For example, assuming that the bits to be encoded include 2 information bits and 2 frozen bits, the generator matrix is

Assuming that the first transformation operation matrix is (4,1,2,3), the 4 th column of the generated matrix is exchanged with the 1 st column, the 1 st column is exchanged with the 2 nd column, the 2 nd column is exchanged with the 3 rd column, the 3 rd column is exchanged with the 4 th column, and the obtained first matrix is

Step three, performing Gaussian elimination on the first matrix G1 from left to right, wherein mutually independent columns are pre-generated to generate a new second matrix G2, and determining a second conversion operation matrix (or conversion operation vector) lambda from the first matrix G1 to the second matrix G2₂。

By this step, since the first K columns of the first matrix G1 are not necessarily independent (uncorrelated) from each other, the matrix λ is operated on by the second conversion₂The column sequence of the first matrix G1 is finely adjusted to obtain a second matrix G2, and the first K columns of the second matrix G2 are independent (uncorrelated).

It should be noted that, the process of determining the second transformation operation matrix may participate in the process of determining the first transformation operation matrix, and details are not described herein again.

Step four, operating the matrix lambda through second conversion₂For the first sequence y₁Performing conversion operation to obtain a converted second sequence y₂。

E.g. y₂＝λ₂*y₁。

Step five, for a given 0 ≦ l ≦ K, for all positions in K less than or equal to l in the second sequence y₂The bit hard decisions of (a) are flipped.

And sixthly, for each error mode, recoding the K bits based on the second matrix G2 and calculating a corresponding decoding metric.

And step seven, selecting the code word with the best decoding metric in all error modes to determine as the decoding result.

In addition to the OSD decoding described above, the following describes the error probability of OSD decoding.

In the above-mentioned OSD decoding, the OSD decoding error probability includes a Maximum Likelihood (ML) decoding error probability and an I-level decoding error probability, and the OSD decoding error probability

Satisfy the relationship shown in equation one:

wherein, the first and the second end of the pipe are connected with each other,

for ML decoding error probability, P_e(I) Is the I-level decoding error probability.

The ML decoding error probability is related to the weight spectrum of the codeword, wherein the weight spectrum is related to the likelihood of linear independence between the row vectors used for transmitting the information bits in the generator matrix, e.g., the greater the likelihood of linear independence between the row vectors used for transmitting the information bits in the generator matrix, the better the weight spectrum,

can be shown as formula two:

wherein, P (x)₁→x₂) To code word x₁Decoding with errors into code words x₂Probability of (d)_hIs the hamming distance between the code words,

is an AND code word x₁Hamming distance between d_hF (d) number of code words of_h) To code word x₁Error decoding into a codeword x₁Has a Hamming distance of d_hOf other codewords. Code word x₁And code word x₂The larger the Hamming distance between them, the larger the codeword x₁Decoding with errors into code words x₂The smaller the probability of (c) is, i.e. d_hThe larger, f (d)_h) The smaller. One characteristic of Polar codes is that the minimum hamming distance of a codeword is equal to the minimum row weight of the row corresponding to the information bits in the generator matrix, the row weight being the number of non-0 elements included in a row. Therefore, the better the weight spectrum of the code word, the larger the minimum code weight of the code word, the fewer the code words with lower code weights, and the optimal ML decoding performance (the minimum ML decoding error probability) can be achieved.

The I-order decoding error probability is related to the distribution of d, where d is the number of linearly related columns before the K-th linearly independent column is obtained, i.e., the number of extra columns needed to form K uncorrelated columns. For example, assuming that the K-1 column is linearly independent and the K-th column is linearly dependent on the first K-1 column, the K-th column needs to be swapped with the K + 3-th column to make the first K column linearly independent, then d is 3.

As known from the above OSD decoding process, the OSD decoding is performed according to K irrelevant elements, but in practical application, the first K columns cannot be guaranteed to be linearly irrelevant, and therefore, P is estimated_e(I) When considering the front K + d positionsError condition, P_e(I) The relationship shown in the following formula three is satisfied:

wherein P (d) is the distribution of d,

indicating that, in order to obtain K linearly uncorrelated columns, the maximum number of columns that need to be considered in addition,

is the minimum Hamming distance, P, of the codeword₁The probability of more than I errors in the first K + d elements. Obviously, when the reliability of the Most Reliable Bits (MRB) is higher, the probability of errors is lower, i.e., the probability P of more than I errors occurring in the first K + d elements is lower₁Increases with increasing d, so that the smaller d, the larger P (d) and thus the smaller P_e(I)。

P (d) is consistent with the distribution of the weight spectrum, i.e. the better the weight spectrum, the larger p (d) when d is smaller. P (d) generally satisfies the characteristic shown in equation four below:

and is

Denotes the average number of codewords of which K bits are all 0, N (d)_x) Indicates Hamming weight as d_xOf code words, it can be seen that d_xThe smaller, N (d)_x) The larger the coefficient of the front, and thus

Is mainly determined by the number of codewords having a small weight, the smaller the number of codewords having a small weight,

the smaller, the larger p, the more left (more preferred) the distribution of d. As can be seen from the above, the optimal I-order coding performance (I-order coding error is minimum) and the optimal ML coding performance (ML coding performance is minimum) are consistent.

The greater the probability that any of the K columns in the generator matrix will be linearly independent, the better the distribution of d. Because the linear independence between the rows in the generated matrix is positively correlated with the linear independence of any K columns, the positions corresponding to the linearly independent rows in the generated matrix are selected as information bits as much as possible, so that the linear independence possibility of any K columns can be maximized, and the OSD decoding performance is optimal (the OSD decoding error probability is minimum).

The SCL decoding process may include the steps of:

step one, a receiving sequence is obtained, wherein the receiving sequence comprises a plurality of bits to be decoded.

Alternatively, the received sequence may be a set of LLRs, and one bit to be decoded is one LLR.

And step two, dividing the bits to be decoded in the received sequence into P groups of bits to be decoded.

For example, assume that the received sequence includes 2^aA plurality of bits to be decoded, each group of bits to be decoded including m bits, 2^aP is a positive integer greater than 1, and m is a positive integer greater than or equal to 1.

And thirdly, performing P-step decoding by taking P groups of bits to be decoded as a decoding object until a decoding result is obtained.

For any ith decoding step, m + 1-level LLRs for each information bit to be decoded in the ith set of bits to be decoded can be calculated according to the received sequence (a set of LLRs). And according to the m + 1-level LLR of each information bit in the ith group of bits to be decoded, calculating the path metric values of all possible decoding paths of the ith decoding step in parallel. At least one reserved decoding path is selected based on the path metric values of all possible decoding paths.

In addition to the above-described SCL decoding, the following describes the SCL decoding error probability.

In the SCL decoding process, SCL decoding errors comprise two types of errors, wherein the first type of errors are path selection errors, namely, correct decoding paths do not exist in at least one selected reserved decoding path; the second type of errors are ML errors, i.e., the Path Metric (PM) value of the correctly decoded Path is not minimal. The first type of errors is mainly related to the reliability of the information bit sub-channel, the higher the reliability of the information bit sub-channel, the lower the probability of path selection errors. The second type of errors is related to the weight spectrum of the codeword, the better the weight spectrum of the codeword, the lower the probability of ML errors occurring.

As can be seen from the above, the higher the reliability of the sub-channel corresponding to the information bit is, and the better the weight spectrum is (the higher the possibility of linear independence between the row vectors used for transmitting the information bit in the generator matrix is), the smaller the SCL decoding error probability can be made.

Hereinafter, the technical means shown in the present application will be described in detail by specific examples. It should be noted that several embodiments below may be combined with each other, and descriptions of the same or similar contents are not repeated in different embodiments.

Fig. 3 is a flowchart illustrating an encoding method provided in the present application. Referring to fig. 3, the method may include:

s301, obtaining N bits to be coded.

The N bits to be coded comprise K information bits and N-K fixed bits, wherein N is a positive integer, K is a positive integer, and K is smaller than or equal to N.

Optionally, the information bits are bits for carrying information.

Optionally, the information bits may include Cyclic Redundancy Check (CRC) bits and/or Parity Check (PC) bits.

Alternatively, the fixed bits may also be referred to as padding bits, frozen bits, etc. The fixed bit may be 0.

Alternatively, N may be a positive integer power of 2.

S302, obtaining a generating matrix of N bits to be coded.

Alternatively, the generator matrix may be an N × N matrix, that is, the generator matrix includes N rows and N columns.

For example, the generator matrix may be

Is n times Kronecker power, i.e. the generator matrix can make Kronecker products for n matrices F in succession, n being log₂N。

For example, when N equals 4, the generator matrix may be:

when N equals 8, the generator matrix may be:

s303, determining the position of the information bit according to the linear irrelevant measurement between the row vectors in the generating matrix.

Alternatively, the linearly independent metric may be a linearly independent likelihood, or the linearly independent metric may also be referred to as a linearly independent likelihood.

Optionally, the information bits have K positions.

Alternatively, the position of the information bit may be the row number of the row vector that generates the greater likelihood (e.g., maximum) of being linearly independent in the matrix.

In the present application, a row vector may also be referred to as a row, a row sequence number of a row vector may also be referred to as a row sequence number of a row, and a row weight of a row vector may also be referred to as a row weight of a row.

For example, assuming that N is 8 and K is 4, assuming that the linear independence metric between the 1 st, 2 nd, 5 th, and 8 th rows in the generator matrix is the largest, the information bit position can be determined to be {1,2,5,8 }.

Optionally, for a row vector x of length N, the row vector x is associated with the preceding K₁The linearly independent measure of the individual row vectors can be shown as equation five:

where i is the column number of the column in which element 1 in vector x is located, for example, if the element in the 1 st, 3 rd, 4 th, and 5 th columns in vector x is 1, i sequentially takes 1,3,4, and 5. q. q.s_iIs front K₁The dimension of a row is K₁The ratio of 1's included in the ith column in the xN matrix, e.g., q if m 1's are included in the ith column_i＝m/K₁。

And S304, coding the bits to be coded according to the positions of the information bits.

Optionally, the information bits and the fixed bits may be sorted according to positions of the information bits, and the sorted information bits and the fixed bits may be encoded according to the generator matrix.

For example, assume that N is 8, K is 4, and the information bit is i₁、i₂、i₃And i₄Since the information bits have the positions {4,6,7,8} and the fixed bits have 0, the information bits and the fixed bits are ordered according to the positions of the information bits to obtain a sequence

Can be sequenced

Multiplying by a generating matrix, and carrying out bit reverse order rearrangement to realize the encoding of the bits to be encoded.

According to the coding method, the position of the information bit is determined according to the linear independence measurement between the row vectors in the generating matrix, so that the possibility of linear independence between the row vectors in the generating matrix corresponding to the position of the information bit is high, the probability of SCL (Single Gate driver) decoding errors and the probability of OSD (on Screen display) decoding errors are low, and the reliability of coding is improved.

On the basis of any of the above embodiments, the position of the information bit may be determined by the following feasible implementation manners. Specifically, please refer to the embodiment shown in fig. 4.

Fig. 4 is a schematic flowchart of determining the position of an information bit according to the present application. Referring to fig. 4, the method may include:

s401, initializing a first position set.

The initialized first position set comprises row sequence numbers of row vectors with the largest row weight in the generated matrix.

Optionally, the row weight of the row vector refers to the number of non-zero elements included in the row vector. For example, the row weight of a row vector in the generator matrix refers to the number of 1's included in the row vector.

The elements in the last row of the generator matrix are typically all 1's, so the row weight of the last row vector in the generator matrix is the largest.

Optionally, the initialized first location set may include at least two cases:

one possible scenario is:

the initialized first position set only comprises row sequence numbers of the last row in the generating matrix.

In this possible case, the number of line sequence numbers included in the initialized first location set is 1.

For example, assuming that the generator matrix includes 8 rows, only the row number 8 is included in the first location set.

Optionally, when the decoding algorithm is an SCL decoding algorithm, the initialized first location set may be the possible case.

Another possible scenario is:

when the generating matrix is a polar code matrix of bits to be coded, and the polar code matrix comprises N rows and N columns, the initialized first position set comprises serial numbers of rows in the generating matrix, wherein the row weight of the rows is greater than the first Hamming distance.

The first hamming distance is the maximum value of the minimum hamming distances when the information bits and the fixed bits are arranged according to different modes, the information bits and the fixed bits are arranged according to a mode and correspond to one minimum hamming distance, the minimum hamming distance when the information bits and the fixed bits are arranged according to a mode is the minimum line weight of the lines corresponding to the information bits in the generated matrix when the information bits and the fixed bits are arranged according to the mode.

In this possible case, the number of row numbers included in the initialized first location set is 1 or more.

Alternatively, the minimum hamming distance when the information bits and the fixed bits are arranged in one way may be determined as follows: when the information bits and the fixed bits are arranged in one manner, the information bits (positions of the information bits) can be determined based on the arrangement manner, and the minimum row of the rows corresponding to the information bits in the generator matrix can be determined as the minimum hamming distance in the arrangement.

For example, assume that the information bit is i₁、I₂、I₃And i₄The information bits and the fixed bits (0) are arranged as follows: (0,0,0, i)₁,0,i₂,i₃,i₄) Then, the information bits (positions of the information bits) can be determined to be 4,6,7, and 8, and the information bits correspond to the 4 th, 6 th, 7 th, and 8 th rows in the generator matrix, so that the row weight with the smallest row weight among the row weight of the 4 th row, the row weight of the 6 th row, the row weight of the 7 th row, and the row weight of the 8 th row in the generator matrix can be determined as the smallest hamming distance in this arrangement.

Optionally, the information bits and the fixed bits may be arranged in a plurality of ways, one arrangement may correspond to one minimum hamming distance, and a maximum value of the minimum hamming distances corresponding to all the arrangements of the information bits and the fixed bits is determined as the first hamming distance.

For example, assuming that the information bits and the fixed bits may have Q permutations, Q minimum hamming distances may be determined, and the maximum value of the Q minimum hamming distances is determined as the first hamming distance.

Optionally, when the decoding algorithm is an OSD decoding algorithm, the initialized first location set may be the possible case.

It should be noted that the initialized first location set may be preconfigured.

S402, initializing a second position set.

And the initialized second position set comprises at least one row sequence number.

Optionally, the initialized second location set may include at least the following three cases:

one possible scenario is:

the initialized second position set comprises a row sequence number corresponding to the K + L sub-channels with the highest reliability; wherein, L is the reserved path number of the serial cancellation list SCL decoding, and the reserved path number is the maximum path number reserved in each step of decoding in the SCL decoding.

Optionally, the K + L sub-channels are K + L sub-channels with the highest reliability among the N sub-channels.

Optionally, the K + L subchannels are K + L subchannels with the highest reliability among the N-X subchannels, where X is the number of row sequence numbers included in the initialized first location set, and the N-X subchannels are subchannels except subchannels corresponding to the row sequence numbers in the first location set among the N subchannels. I.e. the process is repeated. The row number in the initialized first location set is not included in the initialized second location set.

Optionally, L may be 4, 8, 16, and the like, and in an actual application process, the size of L may be set according to actual needs.

Optionally, the row sequence number corresponding to the sub-channel may be an identifier of the sub-channel. For example, if the K + L subchannels with the highest reliability are the 1 st, 4 th, 6 th, and 7 th subchannels, the row numbers corresponding to the K + L subchannels with the highest reliability are 1,4 th, 6 th, and 7 th subchannels.

Optionally, when the decoding algorithm is the SCL decoding algorithm, the initialized second location set may be the possible case.

The second position set of the possible initialization is very suitable for a short code scene (a scene with a smaller N and/or a smaller K), and therefore, a threshold NT of N (or a threshold of K, which is consistent in principle and not described herein) may also be set, the information bit position is determined by the construction method described in the above embodiment when the N is smaller than or equal to NT, and the information bit position is selected by the conventional method according to the reliability principle or other principles when the N is greater than or equal to NT.

Another possible scenario is:

the initialized second position set comprises sequence numbers of rows with row weights equal to the first Hamming distance in the generating matrix.

It should be noted that the first hamming distance may be referred to as S401, and is not described herein again.

Optionally, when the decoding algorithm is an OSD decoding algorithm, the initialized second location set may be the possible case.

Yet another possible scenario is:

the initialized second position set comprises all row serial numbers in the generated matrix; alternatively, the initialized second set of locations includes a row sequence number in the generator matrix in addition to the row sequence number in the initialized first set of locations.

It should be noted that the initialized second location set may be pre-configured.

S403, determining a target row sequence number in the current second position set according to the possibility of linear independence between the row vector corresponding to each row sequence number in the current second position set in the generated matrix and the row vector corresponding to the row sequence number in the current first position set in the generated matrix.

In the current second position set, the probability of linear independence between the row vector in the generator matrix corresponding to the target row sequence number and the row vector corresponding to the row sequence number in the current first position set in the generator matrix is the largest.

It should be noted that, in the present application, the row sequence number included in the first location set may be changed by executing S404, and the row sequence number included in the second location set may be changed by executing S405. That is, the first location set and the second location set in this application are constantly changing, the row sequence numbers included in the first location set at different time instants may be different, and the row sequence numbers included in the second location set at different time instants may be different.

The current first location set shown in this application refers to a first location set at the current time, where if S404 has not been executed, the current first location set is an initialized first location set, and if S404 has been executed, the current location set is a new first location set obtained after S404 has been executed last time.

The current second location set shown in this application refers to a second location set at the current time, where if S405 is not executed yet, the current second location set is an initialized second location set, and if S405 is executed, the current location set is a new second location set obtained after S405 is executed last time.

Optionally, the possibility that the first row vector corresponding to one row sequence number in the current second position set in the generator matrix is linearly independent of the second row vector corresponding to the row sequence number in the current first position set in the generator matrix may be: the sum of the linearly independent possibilities between the first row vector and each second row vector or the average of the linearly independent possibilities between the first row vector and all second row vectors.

It should be noted that, through the above formula five, the possibility that the row vector corresponding to each row sequence number in the current second position set in the generator matrix is linearly independent from the row vector corresponding to the row sequence number in the current first position set in the generator matrix is determined.

Optionally, for the row sequence numbers in the current second location set, the possibility of linear independence between the row vector corresponding to each row sequence number and the row vector corresponding to the row sequence number in the current first location set in the generator matrix may be respectively calculated, and the row sequence number with the highest possibility of linear independence between the row vectors corresponding to the row sequence numbers in the current first location set in the current second location set is determined as the target row sequence number.

For example, assuming that the

row numbers

2,3,4 are included in the second position set and the row numbers 1,8 are included in the first position set, the possibility that the 2 nd row in the generator matrix is not linearly related to the 1 st row and the 8 th row (denoted as possibility 1) may be calculated, the possibility that the 3 rd row in the generator matrix is not linearly related to the 1 st row and the 8 th row (denoted as possibility 2) may be calculated, the possibility that the 4 th row in the generator matrix is not linearly related to the 1 st row and the 8 th row (denoted as possibility 3) may be calculated, and if the value of possibility 2 is the largest among possibility 1, possibility 2, and possibility 3, the row number 3 may be determined as the target row number.

S404, adding the sequence number of the target row to the current first position set to obtain a new first position set.

Optionally, if the number of the target row sequence numbers is 1, the target row sequence numbers are directly added to the current first position set.

Optionally, if the number of the target row sequence numbers is greater than 1, adding the target row sequence number in the current first position set according to the number of the target row sequence numbers and the number of the row sequence numbers included in the current first position set.

Optionally, it is assumed that the number of the target row sequence numbers is Y, the number of the row sequence numbers included in the current first position set is T, and K-T is Z; and when Y is larger than Z, determining Z target row serial numbers in the Y target row serial numbers, and adding the Z target row serial numbers to the current first position set. Y is an integer greater than 1, and Z is a positive integer less than or equal to K. In this way, the first position set can be made to include K row sequence numbers at most, so as to avoid that the number of row sequence numbers included in the first position is greater than K.

When Y is greater than Z, Z target row sequence numbers may be selected from the Y target row sequence numbers by a rule, which may include, but is not limited to, any one of the following rules: the Z target row serial numbers are row serial numbers corresponding to the Z sub-channels with the highest reliability in the Y target row serial numbers; or the Z target row serial numbers are the Z row serial numbers with the largest row serial number in the Y target row serial numbers; or the Z target row serial numbers are the Z row serial numbers with the smallest row serial number in the Y target row serial numbers.

Of course, in the actual application process, a rule for selecting Z target row serial numbers from Y target row serial numbers may be set according to actual needs, which is not specifically limited in this application.

And S405, deleting the sequence number of the target row in the current second position set to obtain a new second position set.

It should be noted that the sequence number of the target row added in the current first location set is the same as the sequence number of the target row deleted in the current second location set.

For example, if Z target row numbers are added to the current first location set, Z target row numbers are deleted from the current second location set, and the Z target row numbers added to the current first location set are the same as the Z target row numbers deleted from the current second location set.

S406, judging whether the number of the row sequence numbers in the new first position set is K.

If yes, go to step S407.

If not, go to step S403.

S407, determining the line sequence number in the current first position set as the position of the information bit.

In the embodiment shown in fig. 4, the initialized first set of locations comprises the row sequence number of the row vector with the largest row weight in the generator matrix, and sequentially moving the row sequence number corresponding to the row vector with the highest possibility of linear independence between the row vectors corresponding to the row sequence numbers in the first position set in the second position set to the first position set, so that, the code weight of the row vector in the generator matrix corresponding to the row sequence number in the first position set can be made larger, and maximizes the likelihood of linear independence between the row vectors in the generator matrix corresponding to the row sequence numbers in the first set of locations, i.e., to maximize the likelihood of linear independence between the row vectors corresponding to the information bits in the generator matrix, therefore, the decoding error probability of SCL is smaller, the OSD decoding error probability is smaller, and the reliability of coding is improved.

The method shown in the embodiment of fig. 4 will be described below by specific examples.

Example 1, assume that the decoding algorithm is the SCL decoding algorithm, N is 16, K is 4, and L is 4.

Initializing a first set of locations: it is determined that the initialized first set of locations includes the row number (16) of the last row of the generator matrix, i.e., the initialized first set of locations is {16 }.

Initializing a second set of locations: and determining that the initialized second position set comprises a line sequence number corresponding to the K + L (8) subchannel with the highest subchannel reliability in the 16 channels, and assuming that the initialized second position set is {1,3,4,5,8,9,12,15 }.

Respectively acquiring the possibility that each row in the 1 st, 3 rd, 4 th, 5 th, 8 th, 9 th, 12 th and 15 th rows in the generated matrix is not linearly related to the 16 th row, and if the possibility that the 3 rd row in the generated matrix is not linearly related to the 16 th row is the maximum, adding the row sequence number 3 to the current first position set to obtain a new first position set, and deleting the row sequence number 3 from the current second position set to obtain a new second position set. The new first set of positions is 16,3 and the new second set of positions is 1,4,5,8,9,12, 15.

Respectively obtaining the possibility that each row in the 1 st, 4 th, 5 th, 8 th, 9 th, 12 th and 15 th rows in the generated matrix is not linearly related to the 16 th and 3 th rows, and if the possibility that the 9 th row in the generated matrix is not linearly related to the 16 th and 3 th rows is the maximum, adding the row sequence number 9 to the current first position set to obtain a new first position set, and deleting the row sequence number 9 from the second position set to obtain a new second position set. The new first set of positions is 16,3,9 and the new second set of positions is 1,4,5,8,12, 15.

The above process is repeated until K is 4 row numbers in the current first position set. Assuming that the current first set of locations is 16,3,9,8, the location of the information bit is determined to be 3,8,9, 16.

Example 2, assume that the decoding algorithm is an OSD decoding algorithm, N is 16, and K is 8.

First, the first hamming distance is calculated, and the calculation process of the first hamming distance can be referred to as S401, which is not described herein again.

Initializing a first set of locations: it is determined that the initialized first location set includes a row number of rows having a row weight greater than the first hamming distance. Assume that the initialized first set of locations is 2,3,8,10, 16.

Initializing a second set of locations: it is determined that the initialized second set of locations includes a row number for rows having a row weight equal to the first hamming distance. Assume that the initialized second set of locations is 4,7,9,13, 15.

And respectively acquiring the possibility that each row in the 4 th, 7 th, 9 th, 13 th and 15 th rows in the generated matrix is linearly independent of all rows (2,3,8,10 and 16) in the first position set, and if the possibility that the 7 th row in the generated matrix is linearly independent of all rows (2,3,8,10 and 16) in the first position set is the maximum, adding the row sequence number 7 to the current first position set to obtain a new first position set, and deleting the row sequence number 7 from the current second position set to obtain a new second position set. The new first set of positions is {2,3,8,10,16, 7}, and the new second set of positions is {4,9,13,15 }.

The above process is repeated until the current first position set includes K ═ 8 row sequence numbers. Assuming that the current first set of locations is {2,3,8,10,16,7,4,9}, then the location of the information bit is determined to be 2,3,4,7,8,9,10, 16.

On the basis of any of the above embodiments, the decoding efficiency based on the encoding method shown in the present application will be described below with reference to simulation data shown in fig. 5 to 6.

When the simulation parameters corresponding to the coding of the present application and the simulation parameters corresponding to the existing coding are shown in table 1, the simulation results by the coding method shown in the present application and the existing coding method can be shown in fig. 5.

TABLE 1

/	Simulation parameters corresponding to the coding of the application	Simulation parameters corresponding to existing codes
			Channel with a plurality of channels	AWGN	AWGN
Modulation system	BPSK	BPSK
			Construction method	New Code	GA
Cascade code	NO CRC	NO CRC
			Decoding algorithm	SCL(L＝8)	SCL(L＝8)
Information bit length K	64	64
			Codeword length N	128	128

Referring to table 1, in simulation parameters corresponding to the present application Code and the existing Code, channels are both Additive White Gaussian Noise (AWGN) channels, modulation modes are both Binary Phase Shift Keying (BPSK), a codeword construction mode of the present application becomes a New Code mode, an existing codeword construction mode is Gaussian Approximation (GA), a CRC Code is not used, decoding algorithms are both SCL decoding algorithms (both reserved decoding paths L are 8), information bit length K is 64, and codeword length N is 128.

Fig. 5 is a schematic simulation diagram provided in the present application. Referring to fig. 5, the horizontal axis represents signal to noise ratio (SNR) and the vertical axis represents Block Error Rate (BLER).

Referring to fig. 5, the dashed line represents the decoded block error rate when the encoding method of the prior art is used, and the solid line represents the decoded block error rate when the encoding method of the present application is used. As can be seen from fig. 5, when CRC is not used, the coding method of the present application can significantly reduce the block error rate in the decoding process, so that the decoding performance is higher.

When the simulation parameters corresponding to the coding of the present application and the simulation parameters corresponding to the existing coding are shown in table 2, the simulation results by the coding method shown in the present application and the existing coding method can be shown in fig. 6.

TABLE 2

/	Simulation parameters corresponding to the coding of the application	Simulation parameters corresponding to existing codes
			Channel with a plurality of channels	AWGN	AWGN
Modulation system	BPSK	BPSK
			Construction method	New Code	GA
Cascade code	NO CRC	CRC-4
			Decoding algorithm	SCL(L＝8)	SCL(L＝8)
Information bit length K	64	64
			Codeword length N	128	128

Referring to table 2, in the simulation parameters corresponding to the present application encoding and the existing encoding, the channels are AWGN channels, the modulation modes are BPSK, the codeword structure mode of the present application becomes a New Code mode, the existing codeword structure mode is GA, the present application does not use CRC codes, the existing encoding uses 4 CRC codes, the decoding algorithms are SCL decoding algorithms (both reserved decoding paths L are 8), the information bit lengths K are 64, and the codeword lengths N are 128.

Fig. 6 is a schematic simulation diagram provided in the present application. Referring to fig. 6, the horizontal axis represents SNR and the vertical axis represents BLER.

Referring to fig. 6, the dashed line represents the decoded block error rate when the encoding method of the prior art is used, and the solid line represents the decoded block error rate when the encoding method of the present application is used. As can be seen from fig. 6, when the present application does not use CRC, and the existing code uses 4-bit CRC code, the coding method of the present application can significantly reduce the block error rate in the decoding process, so that the decoding performance is higher, and the complexity caused by CRC check can be reduced.

When the simulation parameters corresponding to the coding of the present application and the simulation parameters corresponding to the existing coding are shown in table 3, the simulation results by the coding method shown in the present application and the existing coding method can be shown in fig. 7.

TABLE 3

/	Simulation parameters corresponding to the coding of the application	Simulation parameters corresponding to existing codes
			Channel with a plurality of channels	AWGN	AWGN
Modulation system	BPSK	BPSK
			Construction method	New Code	GA
Concatenated codes	NO CRC	NO CRC
			Decoding algorithm	OSD-3	OSD-3
Information bit length K	32	32
			Codeword length N	64	64

Referring to table 3, in the simulation parameters corresponding to the present application encoding and the existing encoding, the channels are AWGN channels, the modulation modes are BPSK, the codeword structure mode of the present application becomes a New Code mode, the existing codeword structure mode is GA, no CRC Code is used, the decoding algorithms are OSD decoding algorithms, the information bit length K is 32, and the codeword length N is 64.

Fig. 7 is a schematic simulation diagram provided in the present application. Referring to fig. 7, the horizontal axis represents SNR and the vertical axis represents Block Error Rate (BLER).

Referring to fig. 7, the dashed line represents the decoded block error rate when the encoding method of the prior art is used, and the solid line represents the decoded block error rate when the encoding method of the present application is used. As can be seen from fig. 7, when CRC is not used, the coding method of the present application can significantly reduce the block error rate in the decoding process, so that the decoding performance is higher.

Fig. 8 is a schematic structural diagram of an encoding apparatus according to an embodiment of the present application. Referring to fig. 8, the encoding apparatus 10 may include:

a first obtaining module 11, configured to obtain N bits to be encoded, where the N bits to be encoded include K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is less than or equal to N;

a second obtaining module 12, configured to obtain a generator matrix of the N bits to be encoded;

a determining module 13, configured to determine the position of the information bit according to a linear independence metric between row vectors in the generator matrix;

and an encoding module 14, configured to encode the bits to be encoded according to the positions of the information bits.

Optionally, the first obtaining module 11 may execute S301 in the embodiment of fig. 3.

Optionally, the second obtaining module 12 may execute S302 in the embodiment of fig. 3.

Alternatively, the determining module 13 may execute S303 in the embodiment of fig. 3 and the embodiment shown in fig. 4.

Optionally, the encoding module 14 may execute S304 in the embodiment of fig. 3.

Optionally, the encoding apparatus 10 may further include a sending module, configured to send the encoded information.

It should be noted that the encoding apparatus shown in the embodiment of the present application may execute the technical solutions shown in the foregoing method embodiments, and the implementation principle and the beneficial effects thereof are similar, and are not described herein again.

In one possible embodiment, the linearly independent measure is a linearly independent likelihood.

In a possible implementation, the determining module 13 is specifically configured to:

and determining the position of the information bit according to a linear independence measure between a row vector corresponding to each row sequence number in the second position set in the generated matrix and a row vector corresponding to a row sequence number in the first position set in the generated matrix.

and L is the reserved path number of the serial cancellation list SCL decoding, wherein the reserved path number is the maximum path number reserved in each step of decoding in the SCL decoding.

In a possible implementation, the generator matrix is a polar code matrix of the bits to be encoded, and the polar code matrix includes N rows and N columns;

In one possible embodiment, the initialized second set of locations includes all row numbers in the generator matrix; alternatively, the first and second electrodes may be,

In a possible implementation, the determining module 13 is configured to:

performing a first operation, the first operation comprising: determining a target row sequence number in the current second position set according to a linear independence measure between a row vector corresponding to each row sequence number in the current second position set in the generated matrix and a row vector corresponding to a row sequence number in the current first position set in the generated matrix; in the current second position set, the linear independence measure between the row vector corresponding to the target row sequence number in the generating matrix and the row vector corresponding to the row sequence number in the current first position set in the generating matrix is the largest;

In a possible implementation, the determining module 13 is configured to:

when Y is larger than Z, Z target row sequence numbers are determined in the Y target row sequence numbers, Y is the number of the target row sequence numbers, Z is K-T, T is the number of the row sequence numbers included in the current first position set, Y is an integer larger than 1, and Z is a positive integer smaller than or equal to K;

and adding the Z target row sequence numbers to the current first position set, and deleting the Z target row sequence numbers in the current second position set.

the Z target row serial numbers are the Z row serial numbers with the largest row serial number in the Y target row serial numbers; alternatively, the first and second liquid crystal display panels may be,

Fig. 9 is a schematic hardware structure diagram of an encoding apparatus according to an embodiment of the present disclosure. Referring to fig. 9, the encoding apparatus 20 may include: a processor 21 and a memory 22; wherein the content of the first and second substances,

a memory 22 for storing computer programs and sometimes also intermediate data;

a processor 21 for executing the computer program stored in the memory to realize the steps of the above coding method. Reference may be made in particular to the description relating to the previous method embodiments.

Alternatively, the memory 22 may be separate or integrated with the processor 21. In some embodiments, the memory may even be located outside the device.

When the memory 22 is a device separate from the processor 21, the receiving apparatus 20 may further include a bus 23 for connecting the memory 22 and the processor 21.

The encoding apparatus of fig. 9 may further include a transmitter for transmitting the encoded information.

The encoding device provided in this embodiment may be a terminal device or a network device, and may be configured to execute the encoding method, which has similar implementation and technical effects, and this embodiment is not described herein again.

An embodiment of the present application further provides a storage medium, where the storage medium includes a computer program, and the computer program is used to implement the encoding method described above.

An embodiment of the present application further provides a chip or an integrated circuit, including: a memory and a processor;

the memory is used for storing program instructions and sometimes intermediate data;

the processor is used for calling the program instructions stored in the memory to realize the coding method.

Alternatively, the memory may be separate or integrated with the processor. In some embodiments, the memory may also be located outside of the chip or integrated circuit.

An embodiment of the present application further provides a program product, which includes a computer program, where the computer program is stored in a storage medium, and the computer program is used to implement the above coding method.

The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied in hardware or may be embodied in software instructions executed by a processor. The software instructions may be comprised of corresponding software modules that may be stored in Random Access Memory (RAM), flash Memory, Read Only Memory (ROM), Erasable Programmable Read Only Memory (EPROM), Electrically Erasable Programmable Read Only Memory (EEPROM), registers, a hard disk, a removable disk, a compact disc Read Only Memory (CD-ROM), or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. Of course, the storage medium may also be integral to the processor. The processor and the storage medium may reside in an ASIC. In addition, the ASIC may reside in a base station or a terminal. Of course, the processor and the storage medium may reside as discrete components in a receiving device.

It should be understood that the Processor may be a Central Processing Unit (CPU), other general purpose Processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), etc. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor, or in a combination of hardware and software modules.

The memory may comprise a high speed RAM memory, and may further comprise a non-volatile storage NVM, such as at least one magnetic disk memory, and may also be a usb disk, a removable hard disk, a read-only memory, a magnetic or optical disk, or the like.

The bus may be an Industry Standard Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, an Extended ISA (EISA) bus, or the like. The bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, the buses in the figures of the present application are not limited to only one bus or one type of bus.

The storage medium may be implemented by any type or combination of volatile and non-volatile memory devices, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disks. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

In the present application, "at least one" means one or more, "a plurality" means two or more. "and/or" describes the association relationship of the associated object, indicating that there may be three relationships, for example, a and/or B, which may indicate: a alone, A and B together, and B alone, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of the singular or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or multiple.

Those skilled in the art will recognize that the functionality described in embodiments of the invention may be implemented in hardware, software, firmware, or any combination thereof, in one or more of the examples described above. When implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer.

In the embodiments provided in the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described device embodiments are merely illustrative, and for example, the division of the modules is only one logical division, and other divisions may be realized in practice, for example, a plurality of modules may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or modules, and may be in an electrical, mechanical or other form.

The modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical units, may be located in one position, or may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of the present embodiment.

In addition, functional modules in the embodiments of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The unit formed by the modules can be realized in a hardware form, and can also be realized in a form of hardware and a software functional unit.

Claims

1. A method of encoding, comprising:

acquiring N bits to be coded, wherein the N bits to be coded comprise K information bits and N-K fixed bits, N is a positive integer, K is a positive integer, and K is less than or equal to N;

acquiring a generating matrix of the N bits to be coded;

determining the position of the information bit according to the linear irrelevance measurement between the row vectors in the generating matrix;

and coding the bit to be coded according to the position of the information bit.

2. The method of claim 1, wherein the linearly independent metric is a linearly independent likelihood.

3. The method of claim 1 or 2, wherein determining the position of the information bit according to a linear independence metric between row vectors in the generator matrix comprises:

4. The method according to claim 3, wherein the initialized second location set comprises a row sequence number corresponding to the K + L subchannels with the highest reliability;

5. The method of claim 4,

the K + L sub-channels are K + L sub-channels with the highest reliability in the N sub-channels; alternatively, the first and second liquid crystal display panels may be,

6. The method of claim 3, wherein the generator matrix is a polar code matrix of the bits to be encoded, and the polar code matrix comprises N rows and N columns;

7. The method of claim 6, wherein the initialized second set of locations comprises sequence numbers of rows in the generator matrix with row weights equal to the first Hamming distance.

8. The method of claim 3,

the initialized second location set comprises all row sequence numbers in the generator matrix; alternatively, the first and second liquid crystal display panels may be,

the initialized second set of locations comprises a row sequence number in the generator matrix except for a row sequence number in the initialized first set of locations.

9. The method according to any of claims 4-8, wherein said determining the position of the information bit according to a linear independence metric between the row vector corresponding to each row sequence number in the second set of positions in the generator matrix and the row vector corresponding to the row sequence number in the first set of positions in the generator matrix comprises:

and repeatedly executing the first operation and the second operation until the new first position set comprises K row serial numbers, and determining the row serial number in the current first position set as the position of the information bit.

10. The method of claim 9, wherein adding the target row sequence number to a current first location set and deleting the target row sequence number from a current second location set comprises:

11. The method of claim 10,

the Z target row serial numbers are row serial numbers corresponding to Z sub-channels with highest reliability in the Y target row serial numbers; alternatively, the first and second electrodes may be,

the Z target row serial numbers are the Z row serial numbers with the largest row serial number in the Y target row serial numbers; alternatively, the first and second electrodes may be,

12. The method according to any of claims 1-2, 4-8, 10-11, characterized in that the information bits comprise cyclic redundancy check, CRC, bits and/or parity check, PC, bits.

13. An encoding apparatus, comprising:

14. The apparatus of claim 13, wherein the linearly independent metric is a linearly independent likelihood.

15. The apparatus according to claim 13 or 14, wherein the determining module is specifically configured to:

16. The apparatus according to claim 15, wherein the initialized second location set includes a row sequence number corresponding to K + L subchannels with highest reliability;

17. The apparatus of claim 16,

the K + L sub-channels are K + L sub-channels with the highest reliability in the N sub-channels; alternatively, the first and second electrodes may be,

18. The apparatus of claim 15, wherein the generator matrix is a polar code matrix of the bits to be encoded, and wherein the polar code matrix comprises N rows and N columns;

the initialized first position set comprises sequence numbers of rows with row weights larger than a first Hamming distance in the generator matrix; the first hamming distance is the maximum value of the minimum hamming distances when the information bits and the fixed bits are arranged in different ways, the information bits and the fixed bits are arranged in a way corresponding to one minimum hamming distance, the minimum hamming distance when the information bits and the fixed bits are arranged in a way is the minimum line weight of the lines corresponding to the information bits in the generating matrix when the information bits and the fixed bits are arranged in the way.

19. The apparatus of claim 18, wherein the initialized second set of locations comprises sequence numbers of rows in the generator matrix with row weights equal to the first hamming distance.

20. The apparatus of claim 15,

21. The apparatus according to any of claims 16-20, wherein the determining module is configured to:

22. The apparatus of claim 21, wherein the determining module is configured to:

23. The apparatus of claim 22,

24. The apparatus according to any of claims 13-14, 16-20, 22-23, wherein the information bits comprise cyclic redundancy check, CRC, bits and/or parity check, PC, bits.

25. An encoding apparatus, comprising: memory, a processor and a computer program, the computer program being stored in the memory, the processor running the computer program to perform the method of any of claims 1 to 12.

26. A storage medium, characterized in that the storage medium comprises a computer program for implementing the method according to any one of claims 1 to 12.