CN110098891A - Deinterleaving method and interlaced device - Google Patents
Deinterleaving method and interlaced device Download PDFInfo
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- CN110098891A CN110098891A CN201810087141.XA CN201810087141A CN110098891A CN 110098891 A CN110098891 A CN 110098891A CN 201810087141 A CN201810087141 A CN 201810087141A CN 110098891 A CN110098891 A CN 110098891A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Abstract
This application provides a kind of deinterleaving methods, can promote the random interleaving of interleaving apparatus in the case where not increasing intertexture complexity.This method comprises: generating the first interleaver matrix according to N number of first bit sequence, first matrix is l × l,Expression rounds up；First circulation displacement is carried out to first matrix according to first circulation shift sequence, obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；Second circulation displacement is carried out to second matrix according to second circulation shift sequence, obtains third matrix, wherein the second circulation shift sequence includes S bit, S >=2 and be integer；According to the third matrix, N number of second bit sequence is obtained；Export second bit sequence.
Description
Technical field
This application involves field of channel coding more particularly to a kind of deinterleaving methods and interlaced device.
Background technique
Digital communication system generallys use the reliability of channel coding improve data transfer, wherein some channel codings are adopted
With interleaving technology, further to promote the interference free performance in data transmission procedure.It is many occur simultaneously random error and
On the compound channel of burst error, in case of a mistake, often involve burst of data, leading to burst error is more than channel
Error correcting capability, error correcting capability decline.And if burst error is separated into random error first, then random error error correction is carried out,
Then the interference free performance of system will be further enhanced.
At this stage, according to the difference of deinterleaving method, deinterleaving method is broadly divided into random interleaving and ranks interweave.Random interleaving
In off-line calculation cyclically shifted sequences, need to store constant series for interweaving and deinterleaving use, in the longer situation of code length
Under, storage resource needed for random interleaving is very big or even unacceptable.And ranks interweave for error correcting capability wrong in one's power
Weaker, error-correcting performance is poor.
Summary of the invention
The application provides a kind of deinterleaving method and interlaced device, can be promoted and be entangled in the case where not increasing intertexture complexity
Wrong performance.
In a first aspect, the application provides a kind of deinterleaving method, this method comprises: obtaining N number of first bit sequence, the N
For integer；
According to N number of first bit sequence, the first interleaver matrix is generated, first matrix is l × l, Expression rounds up；First circulation displacement is carried out to first matrix according to first circulation shift sequence, obtains the second square
Battle array, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；According to second circulation shift sequence to institute
It states the second matrix and carries out second circulation displacement, obtain third matrix, wherein the second circulation shift sequence includes S bit,
S >=2 and be integer；According to the third matrix, N number of second bit sequence is obtained；Export second bit sequence.
The deinterleaving method of the embodiment of the present application, compared with random interleaving, intertexture complexity is low, but felt properties but with
Machine felt properties are quite even more excellent.Therefore, error-correcting performance can be promoted in the case where not increasing intertexture complexity.
With reference to first aspect, in certain implementations of first aspect, the method also includes:
According to a cyclically shifted sequences, the second circulation shift sequence is generated.
With reference to first aspect, in certain implementations of first aspect, in the implementation of second aspect, the side
Method specifically includes:
The bit value that the second circulation shift sequence includes is the corresponding bit value of the first circulation shift sequence
Perhaps score or the second circulation shift sequence pass through to the first circulation shift sequence carry out sequence change multiple
Change acquisition.
With reference to first aspect, in certain implementations of first aspect, in the implementation of the third aspect, the side
Method specifically includes:
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, shift sequence as the second circulation
Column；Institute's interception way includes any one following combination: according to the sequencing of bit intercept from back to front S bit,
It intercepts S bits from front to back according to the sequencing of bit, or according to the sequencing of bit, intercepts S1 from back to front
A bit and the sequencing according to bit intercept S2 bits from front to back, wherein and S1+S2=S, S1 are integer,
S2 is integer.
With reference to first aspect, in certain implementations of first aspect, in the implementation of fourth aspect, the side
Method specifically includes:
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, institute's interception way includes following appoints
Anticipate a kind of combination: according to the sequencing of bit intercept from back to front S cyclically shifted sequences, according to bit sequencing from
S cyclically shifted sequences are intercepted after forward direction；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, by S cyclically shifted sequences after sequential transformations
As second circulation shift sequence.
With reference to first aspect, in certain implementations of first aspect, in the implementation of the 5th aspect, the side
Method specifically includes:
The first circulation shift sequence and the second circulation shift sequence can be recycled from preconfigured L longest
It is obtained in shift sequence, the J is less than L, and the S is less than L, and the L is integer.
The deinterleaving method of the embodiment of the present application, compared with random interleaving, intertexture complexity is low, but felt properties but with
Machine felt properties are quite even more excellent.Therefore, error-correcting performance can be promoted in the case where not increasing intertexture complexity.
Second aspect provides a kind of interlaced device, for executing any possible realization of first aspect, first aspect
Method in mode.Specifically, which includes in any possible implementation for execute first aspect or first aspect
The unit of method.
The third aspect, the application provide a kind of interleaving apparatus, and the interleaving apparatus includes: one or more processors, and one
A or multiple memories, one or more transceivers (each transceiver includes transmitter and receiver).Transceiver is for passing through
Antenna receiving and transmitting signal.Memory is for storing computer program instructions (in other words, code).Processor is for executing in memory
The instruction of storage, when executed, processor execute in any possible implementation of first aspect or first aspect
Method.
Fourth aspect, the application provide a kind of computer readable storage medium, store in the computer readable storage medium
There is instruction, when run on a computer, so that computer executes any possible of above-mentioned first aspect or first aspect
Method in implementation.
5th aspect, the application provide a kind of chip (in other words, chip system), including memory and processor, store
Device is for storing computer program, and processor from memory for calling and running the computer program, so that being equipped with this
The communication equipment of chip executes the method in above-mentioned first aspect and its any one possible implementation.
6th aspect, the application provide a kind of computer program product, and the computer program product includes: computer journey
Sequence code, when the computer program code is run on computers, so that computer executes above-mentioned first aspect and its appoints
A kind of method anticipated in possible implementation.
7th aspect, the application provides a kind of code device, which, which has, realizes above-mentioned first aspect and its
On the one hand the function of the method in any one possible implementation.These functions can also be led to by hardware realization
It crosses hardware and executes corresponding software realization.The hardware or software include one or more modules corresponding with above-mentioned function.
In addition, the code device should also have and encode relevant performance, for example, coding, rate-matched etc..
In a possible design, when some or all of these functions pass through hardware realization, code device includes:
Input interface circuit, for obtaining N number of first bit sequence, the N is integer；Logic circuit, for executing above-mentioned first party
Deinterleaving method in the possible design of any one of face and its first aspect；Output interface circuit, for exporting the second bit
Sequence.
Optionally, code device can be chip or integrated circuit.
In a possible design, when some or all of these functions pass through software realization, code device includes:
Memory, for storing computer program；Processor, for executing the computer program of the memory storage, when the meter
Calculation machine program is performed, any one possible design of above-mentioned first aspect and its first aspect may be implemented in code device
Described in deinterleaving method.
In a possible design, when some or all of these functions pass through software realization, code device includes
Processor, the memory for storing computer program are located at except code device, and processor passes through circuit/electric wire and memory
Connection, for reading and executing the computer program stored in the memory.
Optionally, above-mentioned memory can be physically separate unit, can also be integral to the processor together.
It should be noted that the application implement described in deinterleaving method be interleaving apparatus by data and/or information
It is performed.In the receiving end of data and/or information, need to be deinterleaved the bit sequence received.Art technology
Known in personnel, deinterleaving is the inverse process to interweave.It is described in above-mentioned first aspect and its any one possible implementation
Deinterleaving method on the basis of, the method that those skilled in the art are easy to get deinterleaving is not described further herein.
In addition, the application provides a kind of device of deinterleaving, specifically, the device of deinterleaving includes executing the side deinterleaved
The unit of method.
In addition, the application also provides a kind of equipment of deinterleaving, which includes one or more processors, one or more
A memory, one or more transceivers (transceiver includes transmitter and receiver).Transmitter or receiver are received by antenna
It signals.Memory is for storing computer program instructions (alternatively, code).Processor is for executing the finger stored in memory
It enables, when executed, processor executes the method deinterleaved.
In addition, the application provides a kind of computer readable storage medium, meter is stored in the computer readable storage medium
Calculation machine instruction, when run on a computer, so that computer executes the method deinterleaved.
The application also provides a kind of computer program product, which includes: computer program code, when
When the computer program code is run on computers, so that computer executes the method deinterleaved.
The application also provides a kind of chip (in other words, chip system), including memory and processor, and memory is for depositing
Computer program is stored up, processor from memory for calling and running the computer program, so that being equipped with the logical of the chip
Letter equipment executes the deinterleaving method in the application each method embodiment.
The application also provides a kind of code translator, which, which has, realizes deinterleaving described in the embodiment of the present application
Method function.These functions can also execute corresponding software realization by hardware realization by hardware.Except this it
Outside, code translator also has the correlation function realized and decoded, for example, solution rate-matched, decoding etc..
In the embodiment of the present application, a kind of deinterleaving method simple to operation is proposed, the complexity that interweaves can not increased
Error-correcting performance is promoted in the case where degree.
Detailed description of the invention
Fig. 1 is the wireless communication system 100 suitable for the embodiment of the present application.
Fig. 2 is the basic flow chart communicated using wireless technology.
Fig. 3 is the flow chart of the deinterleaving method of the embodiment of the present application.
Fig. 4 is the schematic diagram of another deinterleaving method of the embodiment of the present application.
The schematic diagram of the interlaced device 500 of Fig. 5 the embodiment of the present application.
Fig. 6 is the schematic diagram of the interleaving apparatus 600 of the embodiment of the present application.
Fig. 7 is the schematic diagram of the terminal device 700 of the embodiment of the present application.
Specific embodiment
Below in conjunction with attached drawing, the technical solution in the application is described.
Fig. 1 is the wireless communication system 100 suitable for the embodiment of the present application.It may include at least in the wireless communication system
One network equipment 101, the network equipment and one or more terminal devices (for example, terminal device 102 shown in Fig. 1 and
Terminal device 102) it is communicated.The network equipment 101 can be base station, be also possible to setting after base station is integrated with base station controller
It is standby, it can also be other equipment with similar communication function.
The wireless communication system that the embodiment of the present application refers to includes but is not limited to: narrowband Internet of things system (Narrow
Band-Internet of Things, NB-IoT), global system for mobile communications (Global System for Mobile
Communications, GSM), enhanced data rates for gsm evolution system (Enhanced Data rate for GSM
Evolution, EDGE), broadband CDMA system (Wideband Code Division Multiple Access,
WCDMA), CDMA 2000 system (Code Division Multiple Access, CDMA2000), time division synchronous code division
Multi-address system (Time Division-Synchronization Code Division Multiple Access, TD-
SCDMA), long evolving system (Long Term Evolution, LTE), next generation's 5G mobile communication system three big applied fields
Scape eMBB, URLLC and eMTC or the new communication system occurred in the future.
Involved terminal device may include various there is the hand-held of wireless communication function to set in the embodiment of the present application
Standby, mobile unit, wearable device calculate equipment or are connected to other processing equipments of radio modem.Terminal device
It can be mobile station (Mobile Station, MS), subscriber unit (subscriber unit), cellular phone (cellular
Phone), smart phone (smart phone), wireless data card, personal digital assistant (Personal Digital
Assistant, PDA) it is computer, plate computer, radio modem (modem), handheld device (handset), on knee
Computer (laptop computer), machine type communication (Machine Type Communication, MTC) terminal etc..
It is communicated between the network equipment 101 and terminal device in Fig. 1 using wireless technology.Believe when the network equipment is sent
Number when, be interleaving apparatus, terminal device is receiving end.It is receiving end, terminal device is when the network equipment receives signal
Interleaving apparatus.
Fig. 2 is the basic flow chart communicated using wireless technology.The information source of interleaving apparatus successively pass through message sink coding,
It is issued on channel after channel coding, rate-matched and modulation.Receiving end receives successively demodulated, solution rate after signal
Match, obtain the stay of two nights after channel decoding and source coding.
Channel coding is one of core technology of wireless communication system, the improvement of performance will directly be promoted the network coverage and
User's transmission rate.In order to improve the anti-interference of signal, interleaving technology can be further introduced.The think of of interleaving technology
Think to separate symbol in time, a channels with memory is changed into memoryless channel, so that entangling the volume of random error
Code also can be suitably used for burst of noise channel.
Common deinterleaving method includes that random interleaving and ranks interweave.Random interleaving is more excellent in average behavior, but by
In the randomness of intertexture, not can guarantee to interweave every time all has preferably performance.And it in the case where offline interweave, needs to deposit
A large amount of constant series are stored up for interweaving and deinterleaving use.When code length is longer, storage resource needed for random interleaving is larger, gives
Encoder causes very big hardware load or even unacceptable.In addition, the complexity of random interleaving is higher.And what ranks interweaved
Project plan comparison is simple, but weaker for the randomization of data, and felt properties are not satisfactory.
For this purpose, the application proposes a kind of deinterleaving method, error correction can be promoted in the case where not increasing intertexture complexity
Energy.The deinterleaving method of the embodiment of the present application is described in detail below.
It is the flow chart of the deinterleaving method of the embodiment of the present application referring to Fig. 3, Fig. 3.
310, interleaving apparatus obtains N number of first bit sequence.
Wherein, the first bit sequence includes N number of bit, wherein N is integer.
320, interleaving apparatus generates the first interleaver matrix according to N number of first bit sequence, and first matrix is l
× l, Expression rounds up.
330, interleaving apparatus carries out first circulation displacement to first matrix according to first circulation shift sequence, obtains the
Two matrixes, wherein the first circulation shift sequence includes J bit, J >=2 and be integer.
Specifically, the method that interleaving apparatus generates the second circulation shift sequence are as follows: according to the cyclic shift sequence
Column, generate the second circulation shift sequence.
Still optionally further, the method that interleaving apparatus generates the second circulation shift sequence are as follows:
The bit value that the second circulation shift sequence includes is the corresponding bit value of the first circulation shift sequence
Perhaps score or the second circulation shift sequence pass through to the first circulation shift sequence carry out sequence change multiple
Change acquisition；Alternatively,
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, shift sequence as the second circulation
Column；Institute's interception way includes any one following combination: according to the sequencing of bit intercept from back to front S bit,
It intercepts S bits from front to back according to the sequencing of bit, or according to the sequencing of bit, intercepts S1 from back to front
A bit and the sequencing according to bit intercept S2 bits from front to back, wherein and S1+S2=S, S1 are integer,
S2 is integer；Alternatively,
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, institute's interception way includes following appoints
Anticipate a kind of combination: according to the sequencing of bit intercept from back to front S cyclically shifted sequences, according to bit sequencing from
S cyclically shifted sequences are intercepted after forward direction；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, by S cyclically shifted sequences after sequential transformations
As second circulation shift sequence；Alternatively,
The first circulation shift sequence and the second circulation shift sequence can be recycled from preconfigured L longest
It is obtained in shift sequence, the J is less than L, and the S is less than L, and the L is integer.
340, second circulation displacement is carried out to second matrix according to second circulation shift sequence, obtains third matrix,
Wherein, the second circulation shift sequence includes S bit, S >=2 and be integer.
350, according to the third matrix, N number of second bit sequence is obtained, sends second bit sequence.
360, second bit sequence is exported.
Above-mentioned interleaving apparatus includes interleaving apparatus, specifically, above-mentioned method is executed by interleaving apparatus；Above-mentioned intertexture is set
Standby can be the network equipment, or terminal device.
In the embodiment of the present application, a kind of deinterleaving method simple to operation is proposed, the complexity that interweaves can not increased
In the case where degree, the bit sequence by treating intertexture carries out row or column cyclic shift, then carries out column or row cyclic shift
This twice successive cyclic shift, so that the performance and random interleaving performance after interweaving are close, it especially can under high order modulation
To reach the performance close with random interleaving equipment, and then the error-correcting performance of lifting system；The program also belongs to a kind of true simultaneously
Sizing interleaving apparatus, meets the design requirement of interleaving apparatus.
Below with reference to Fig. 4, the interleaving process that interleaving apparatus in the embodiment of the present application treats cyclically shifted sequences is made detailed
Explanation.
The embodiment of the present invention is the form of square matrix given a line-column matrix, and provides cyclically shifted sequences, such as the
The specific generating mode of one bit sequence and the second bit sequence, but the generation and initialization of actual cycle shift sequence can be with
There are many forms, are not limited to following methods in the present embodiment.
Step 1: interleaving apparatus obtains N number of bit sequence to be interweaved, and N is integer.
Step 2: the line number and columns of interleaving apparatus is arranged according to N number of bit sequence to be interweaved in interleaving apparatus, and
Line number and columns are equal
It is denoted as l；Then Expression rounds up.
As shown in figure 4, interleaving apparatus size, which is arranged, according to the N is by taking N=16 bit sequences to be interweaved as an example
4x4, i.e. l=4.
Step 3: interleaving apparatus generates the first matrix according to bit sequence to be interweaved, and the size of first matrix is l
×l。
As shown in (1) in Fig. 4, interleaving apparatus obtains bit sequence setting to be interweaved here are as follows: X=1,2,3,4,
5,6,7,8,9,10,11,12,13,14,15,16}；
In the way of l bit of a line or one column l bit in the way of, by bit sequence to be interweaved line by line or
Person reads in interleaving apparatus column by column, and rest position fills in NULL bit；NULL bit is skipped not when being read from interleaving apparatus
It is read out, and then generates the first matrix of l × l.As Fig. 4 reads in interweave line by line in such a way that every row reads 4 bits
In equipment, the first matrix is generated, such as matrix (1) in Fig. 4.
Step 4: interleaving apparatus carries out cyclic shift to the first matrix.
Specifically, circulative shift operation is carried out to the bit sequence in interleaving apparatus according to cyclically shifted sequences:
Firstly, first introduce under above-mentioned cyclically shifted sequences generation:
Cyclically shifted sequences include that first circulation shift sequence and second circulation shift sequence are denoted as S and S ' respectively.
For to the N number of bit of interleaving bits number,
(1) element-specific in S, such as S are initialized1=a, S2=b；
(2) for Si: calculation formula is optional are as follows: Si=(Si-1+Si-2)&l；3≤i≤l；
(3) sequence S ' is the inverted sequence of S, i.e. Si'=Sl-i+1；1≤i≤l.
Sequence S ' obtain can also by new calculation formula, but when interleaver matrix be square matrix when, sequence S ' be S it is anti-
Sequence or other mutation are more convenient in realization succinct.
For being 16, X={ 1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 } with N, according to step (2) and
(3) formula generates cyclically shifted sequences S, S ':
(1) S1=1, S2=2；S3=(S2+S1) &4=3；S4=(S3+S2) &4=1；That is S={ 1,2,3,1 }；
(2) S ' is the backward of S, then S '={ 1,3,2,1 }；
Secondly, the bit for treating intertexture by row and in the way of column carries out cyclic shift:
(1) cyclic shift is carried out by row to matrix (1) according to sequence S and obtains the second matrix, such as Fig. 4 matrix (2)；
(2) cyclic shift is carried out by column to matrix (2) according to sequence S ' and obtains third matrix, such as Fig. 4 matrix (3)；
Step 5: interleaving apparatus reads the third matrix sequence by row or in the way of column, skips NULL bit
It sets, exports the bit sequence of reading.
By taking above-mentioned N is 16 as an example, if reading line by line to third matrix in the way of row, bit sequence X=is exported
{16,8,12,15,4,11,14,3,7,13,2,6,10,1,5,9}。
Above-mentioned interleaving apparatus includes interleaving apparatus, and the interleaving apparatus can be the network equipment, or terminal device.
The interleaving process for treating cyclically shifted sequences to interleaving apparatus in the embodiment of the present application specifically can also be as follows:
The present embodiment and previous embodiment the difference is that: the form of the line-column matrix of use not instead of square matrix,
Line number and columns are in multiple proportion, then when obtaining a cyclically shifted sequences, it, can according to multiple proportion or fractional relationship
To obtain another cyclically shifted sequences by repeating or truncating.
Step 1: interleaving apparatus obtains N number of to interleaving bits number；
Step 2: the size of interleaving apparatus is arranged according to the N in interleaving apparatus are as follows: line number r, columns c are the l of line number
Times,
C=l*r, then Expression rounds up；
Step 3: interleaving apparatus is r × c according to the size of interleaving apparatus, will press row to interleaving bits or in the way of column
Progressively or column by column is read in, and rest position fills in NULL bit, generates the first matrix.
Step 4: interleaving apparatus carries out cyclic shift to the first matrix:
Such as: row and column carries out the cyclic shift of unequal length, and shift sequence is denoted as S and S ' respectively；
Cyclically shifted sequences sequence S, S ' calculation method are as follows, in which:
(1) element-specific in S is initialized；Such as S1=a, S2=b；
(2) S is calculatedi；Such as calculation formula is optional are as follows: Si=(Si-1+Si-2)&l；3≤i≤l；
(3) repetition after the sequential transformations that sequence S ' is S is cumulative.
It is optional:
Cyclically shifted sequences S, S ' calculation method are as follows, in which:
((12)) just count the calculationization S that beginsi'；Element-specific in S '；
(3) sequence S is the interception of S', and interception way can be the sequence for intercepting S length from back to front, or from forward direction
Afterwards, or from specific position the cyclically shifted sequences of corresponding length are intercepted, and then obtain S'；Alternatively,
It is intercepted from S, then the sequence again after the interception does inverted sequence or the operation of other sequential transformations, obtains S'.
Step 5: interleaving apparatus carries out cyclic shift to the first matrix.
The bit that intertexture is treated by row and in the way of column carries out cyclic shift:
(1) cyclic shift is carried out by row to matrix (1) according to sequence S and obtains the second matrix, such as Fig. 4 matrix (2)；
(2) cyclic shift is carried out by column to matrix (2) according to sequence S ' and obtains third matrix, such as Fig. 4 matrix (3)；
Step 6: interleaving apparatus reads the third matrix sequence by row or in the way of column, skips NULL bit
It sets, exports the bit sequence of reading.
The interleaving process for treating cyclically shifted sequences to interleaving apparatus in the embodiment of the present application specifically can also be as follows:
The present embodiment and previous embodiment are the difference is that consider the maximum female code length definition of current control channel
Coded bit is then obtained using repeated encoding when coded bit is greater than 1024 for 1024 bits.Accordingly, it is considered to
This kind of situation, it may be considered that longest available interleaver matrix or longest cyclically shifted sequences are designed, when required cyclic shift
When sequence is less than maximum interleaver matrix or longest cyclically shifted sequences for cyclic shift, from the maximum interleaver matrix or
In person's longest cyclically shifted sequences, first circulation shift sequence and second circulation shift sequence are intercepted.Other related step
Rapid same as the previously described embodiments, so it will not be repeated.
Further, specific method is exemplified below:
Firstly, the method for obtaining maximum interleaver matrix is as follows:
1, if to interleaving bits number be Nmax, interleaving apparatus be dimensioned to line number be r, columns c, r*c >=
Nmax；
2, interleaving apparatus is sized to r × c, and interleaver matrix is defined as A, will read in and interweave by row to interleaving bits
Equipment, rest position fill in NULL bit；
Secondly, the method for interleaver matrix needed for obtaining is as follows:
1, if being N to interleaving bits number, the line number that is dimensioned to of interleaving apparatus is r1, columns c1, r1*c1 >=N；
2, the size of interleaving apparatus is r1 × c1, and interleaver matrix is defined as B, will read in intertexture by row to interleaving bits and set
Standby, rest position fills in NULL bit；
The acquisition of interleaver matrix B be based on above-mentioned matrix A obtain, optionally, matrix B can be to matrix A from top to bottom from
The interception of left-to-right, optionally, matrix B can be the interception to matrix A from top to bottom from right to left, and matrix B can be to square
Battle array A interception from top to bottom from right to left, matrix B can be the interception to matrix A from top to bottom from left to right, and matrix B can be with
It is the interception of the correspondence ranks number started to the starting of matrix A specific position.
Need to illustrate it is above-mentioned be being further described to cyclically shifted sequences in the form of interleaver matrix,
It is different that so-called matrix and sequence difference are the mode showed, but is all made of bit, and can exchange mutually.
The process for specifically carrying out circulative shift operation to the matrix refers to further describing for the above embodiments, this
In repeat no more.
The embodiment of the present application proposes a kind of deinterleaving method simple to operation, can be in the feelings for not increasing intertexture complexity
Under condition, by treat intertexture bit sequence carry out row or column cyclic shift, then carry out column or row cyclic shift this successively
Cyclic shift twice especially can achieve under high order modulation so that the performance and random interleaving performance after interweaving are close
The close performance with random interleaving equipment, and then the error-correcting performance of lifting system；The program also belongs to a kind of deterministic type friendship simultaneously
Equipment is knitted, the design requirement of interleaving apparatus is met.
Fig. 1 to Fig. 4 is combined above, the process of the deinterleaving method of the embodiment of the present application is explained in detail, below to this
The interlaced device of application embodiment is described.
Fig. 5 is the schematic diagram of the interlaced device 500 of the embodiment of the present application.As shown in figure 5, device 500 includes receiving unit
500, processing unit 520 and transmission unit 530.Wherein,
Receiving unit 510, for obtaining N number of first bit sequence, the N is integer；
Processing unit 520, for generating the first interleaver matrix, first matrix according to N number of first bit sequence
For l × l, Expression rounds up；First circulation is carried out to first matrix according to first circulation shift sequence
Displacement obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；According to second
Cyclically shifted sequences carry out second circulation displacement to second matrix, obtain third matrix, wherein the second circulation displacement
Sequence includes S bit, S >=2 and be integer；According to the third matrix, N number of second bit sequence is obtained；
Transmission unit 530, for sending second bit sequence.
Each unit in the device 500 of the embodiment of the present application and above-mentioned other operations or function are respectively in order to realize the application
Deinterleaving method in each embodiment.For sake of simplicity, details are not described herein again.
The interlaced device of the embodiment of the present application can promote error-correcting performance in the case where not increasing intertexture complexity.
Fig. 6 is the schematic diagram of the interleaving apparatus 600 of the embodiment of the present application.As shown in fig. 6, equipment 600 includes: one
A or multiple processors 601, one or more memories 602, one or more transceivers 603.Processor 601 is received for controlling
603 receiving and transmitting signal of device is sent out, memory 602 is for storing computer program, and processor 601 from memory 602 for calling simultaneously
The computer program is run, so that interleaving apparatus 600 executes the corresponding process and/or operation of each embodiment of deinterleaving method.In order to
Succinctly, details are not described herein again.
It should be noted that interlaced device 500 shown in Fig. 5 can be real by interleaving apparatus 600 shown in Fig. 6
It is existing.For example, receiving unit 510, transmission unit 530 can be realized by the transceiver 603 in Fig. 6.Processing unit 520 can be by
Manage realization of device 601 etc..
Interleaving apparatus can be the network equipment or terminal device shown in Fig. 1.In uplink, interleaving apparatus is specific
For terminal device, terminal device has the function of realizing deinterleaving method described in the various embodiments described above.These functions can lead to
Hardware realization is crossed, corresponding software realization can also be executed by hardware.The hardware or software include it is one or more with it is upper
State the corresponding unit of function.In downlink transfer, interleaving apparatus is specially the network equipment (for example, base station), network equipment tool
There is the function of realizing deinterleaving method described in the various embodiments described above.Similarly, these functions can be by hardware realization, can also
To execute corresponding software realization by hardware.The hardware or software include one or more lists corresponding with above-mentioned function
Member.
When interleaving apparatus 600 is specially terminal device, the structure of terminal device can be as shown in Figure 7.Fig. 7 is the application
The schematic diagram of the terminal device 700 of embodiment.
As shown in fig. 7, terminal device 700 includes: transceiver 708 and processing unit 704.Terminal device 700 can also wrap
Memory 719 is included, memory 819 is for storing computer instruction.
Transceiver 708, for obtaining N number of first bit sequence, the N is integer.
Processor 704, for generating the first interleaver matrix according to N number of first bit sequence, first matrix is
L × l,
Expression rounds up；First is carried out to first matrix according to first circulation shift sequence to follow
Ring displacement, obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；According to
Two cyclically shifted sequences carry out second circulation displacement to second matrix, obtain third matrix, wherein the second circulation is moved
Bit sequence includes S bit, S >=2 and be integer；According to the third matrix, N number of second bit sequence is obtained；
Transceiver 708 sends the second bit sequence for the instruction according to processing unit 704.
Further, above-mentioned processing unit 704 can be used for executing described in previous methods embodiment by interleaving apparatus
Inside realize movement, and transceiver 708 can be used for executing interleaving apparatus described in previous methods embodiment reception or
Sending action.Specifically see the description in previous methods embodiment, details are not described herein again.
Above-mentioned processing unit 704 and memory 719 can integrate as a processor, and processor is for executing memory
The program code stored in 719 realizes above-mentioned function.When specific implementation, which also be can integrate in the processor.
Above-mentioned terminal device 700 can also include power supply 812, for the various devices or circuit in terminal device 700
Power supply is provided.Above-mentioned terminal device 700 may include antenna 710, and the data or information for exporting transceiver 808 pass through nothing
Line signal is sent.
In addition to this, in order to keep the function of terminal device 800 more perfect, terminal device 800 can also include that input is single
Member 714, display unit 716, voicefrequency circuit 718, one or more of camera 720 and sensor 722 etc..Voicefrequency circuit is also
It may include loudspeaker 7182, microphone 7184 etc..
It should be noted that the deinterleaving method provided in the embodiment of the present application can be adapted for various channel codings, for example,
LDPC code, Turbo code code, polarization (Polar) code etc..The embodiment of the present application is not construed as limiting this.
In addition, deinterleaving method provided by the present application can be used as an individual interleaving block, for realizing interleaving treatment.
The mode of bit is read when can also be used as rate-matched, can will thus interweave and rate-matched integrates realization,
Individually designed interleaving block is not needed, equally can achieve error-correcting performance identical with random interleaving yet.
In addition, the deinterleaving method of the embodiment of the present application, the intertexture for symbol (symbol) sequence is also to be applicable in, ability
Field technique personnel can also be applied to the friendship of symbol sebolic addressing according to the method described above being interleaved to bit sequence
It knits, is no longer described in detail herein.
In addition, the application provides a kind of computer readable storage medium, finger is stored in the computer readable storage medium
It enables, when run on a computer, so that computer executes the deinterleaving method in the various embodiments described above.
The application also provides a kind of computer program product, which includes: computer program code, when
When the computer program code is run on computers, so that computer executes deinterleaving method described in above-described embodiment.
The application also provides a kind of chip, including memory and processor, and memory is handled for storing computer program
Device from memory for calling and running the computer program, so that the communication equipment for being equipped with the chip executes above-mentioned implementation
Deinterleaving method described in example.
Wherein, communication equipment mentioned here can be the network equipment or terminal device.
The application also provides a kind of code device, which, which has, realizes deinterleaving method described in above-described embodiment
Function.These functions can also execute corresponding software realization by hardware realization by hardware.The hardware is soft
Part includes one or more modules corresponding with above-mentioned function.In addition to this, code device also has the correlation realized and encoded
Function.Code device is treated after coded sequence encoded, using the deinterleaving method of the embodiment of the present application, to the sequence after coding
It is interleaved.It, in this way can be with alternatively, the code device can also apply the deinterleaving method of the embodiment of the present application in rate-matched
Save interleaving block, but can equally play the role of improving error-correcting performance.
In a possible design, when some or all of these functions pass through hardware realization, code device includes:
Input interface circuit, for obtaining the first bit sequence；
Logic circuit, for executing deinterleaving method described in above-described embodiment.It is specifically used for: according to described N number of first
Bit sequence generates the first interleaver matrix, and first matrix is l × l,
Expression rounds up；First is carried out to first matrix according to first circulation shift sequence to follow
Ring displacement, obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；According to
Two cyclically shifted sequences carry out second circulation displacement to second matrix, obtain third matrix, wherein the second circulation is moved
Bit sequence includes S bit, S >=2 and be integer；According to the third matrix, N number of second bit sequence is obtained；
Output interface circuit, for exporting second bit sequence；
Optionally, code device can be chip or integrated circuit.
In a possible design, when some or all of these functions pass through software realization, code device includes:
Memory, for storing computer program；Processor, for executing the computer program of memory storage, when the computer
Program is performed, and deinterleaving method described in the possible design of any one in above-described embodiment may be implemented in code device.
In a possible design, when some or all of these functions pass through software realization, code device includes
Processor.Memory for storing computer program is located at except code device, and processor passes through circuit/electric wire and memory
Connection, for reading and executing the computer program stored in memory.
It should be noted that the application implement described in deinterleaving method be interleaving apparatus by data and/or information
It is performed.In the receiving end of data and/or information, need to be deinterleaved the bit sequence received.Art technology
Known in personnel, deinterleaving is the inverse process to interweave.It is described in above-mentioned first aspect and its any one possible implementation
Deinterleaving method on the basis of, the method that those skilled in the art are easy to get deinterleaving is not described further herein.
Correspondingly, the application provides a kind of device of deinterleaving, for realizing the corresponding function in the method for deinterleaving.
These functions can also execute corresponding software realization by hardware realization by hardware.
In addition, the application provides a kind of computer readable storage medium, meter is stored in the computer readable storage medium
Calculation machine instruction, when run on a computer, so that computer executes the method deinterleaved.
The application also provides a kind of computer program product, which includes: computer program code, when
When the computer program code is run on computers, so that computer executes the method deinterleaved.
The application also provides a kind of chip (in other words, chip system), including memory and processor, and memory is for depositing
Computer program is stored up, processor from memory for calling and running the computer program, so that being equipped with the logical of the chip
Letter equipment executes the deinterleaving method in the application each method embodiment.
The application provides a kind of equipment of deinterleaving, which includes one or more processors, one or more storage
Device, one or more transceivers (each transceiver includes transmitter and receiver).Transmitter or receiver are received and dispatched by antenna
Signal.Memory is for storing computer program instructions (alternatively, code).Processor is for executing the finger stored in memory
It enables, when executed, processor executes the method deinterleaved.
The application also provides a kind of code translator, which, which has, realizes deinterleaving described in the embodiment of the present application
Method function.These functions can also execute corresponding software realization by hardware realization by hardware.Except this it
Outside, code translator also has the correlation function realized and decoded, for example, solution rate-matched, decoding etc..
Optionally, memory described in above embodiments and memory can be physically independent unit, or
Person, memory can also be integrated with processor.
In above embodiments, processor can be central processing unit (Central Processing Unit, CPU), micro- place
Manage device, application-specific integrated circuit (Application-Specific Integrated Circuit, ASIC) or one or
Multiple integrated circuits etc. for being used to control the execution of application scheme program.For example, processor may include digital signal processor
Equipment, micro processor device, analog-digital converter, digital analog converter etc..Processor can according to the respective function of these equipment and
The control of mobile device and the function of signal processing are distributed among these devices.In addition, processor may include operation one
Or the function of multiple software programs, software program can store in memory.
The function of processor can also execute corresponding software realization by hardware realization by hardware.Institute
It states hardware or software includes one or more modules corresponding with above-mentioned function.
Memory can be read-only memory (Read-Only Memory, ROM) or can store static information and instruction
Other kinds of static storage device, random access memory (Random Access Memory, RAM) or can store information
With the other kinds of dynamic memory of instruction.It is also possible to Electrically Erasable Programmable Read-Only Memory (Electrically
Erasable Programmable Read-Only Memory, EEPROM), CD-ROM (Compact Disc Read-
Only Memory, CD-ROM) or other optical disc storages, optical disc storage (including compression optical disc, laser disc, optical disc, digital universal
Optical disc, Blu-ray Disc etc.), magnetic disk storage medium or other magnetic storage apparatus or can be used in carrying or store to have referring to
Enable or data structure form desired program code and can by any other medium of computer access, but not limited to this.
In conjunction with the description of front, those skilled in the art it is to be appreciated that embodiment hereof method, can be by hard
The combination of part (for example, logic circuit) perhaps software or hardware and software is realized.These methods actually with hardware still
Software mode executes, specific application and design constraint depending on technical solution.Professional technician can be to each
Specific application is to use different methods to achieve the described function, but this realization is it is not considered that exceed the model of the application
It encloses.
When above-mentioned function is realized and when sold or used as an independent product by way of software, can store one
In a computer-readable storage medium.In this case, the technical solution of the application is substantially in other words to the prior art
The part to contribute or the part of the technical solution can be embodied in the form of software products, which produces
Product are stored in a storage medium, including some instructions are used so that a computer equipment (can be personal computer, take
Be engaged in device or the network equipment etc.) execute each embodiment the method for the application all or part of the steps.And storage above-mentioned
Medium includes: USB flash disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random
Access Memory, RAM), the various media that can store program code such as magnetic or disk.
The above, the only specific embodiment of the application, but the protection scope of the application is not limited thereto, it is any
Those familiar with the art within the technical scope of the present application, can easily think of the change or the replacement, and should all contain
Lid is within the scope of protection of this application.Therefore, the protection scope of the application should be based on the protection scope of the described claims.
Claims (24)
1. a kind of deinterleaving method characterized by comprising
N number of first bit sequence is obtained, the N is integer；
According to N number of first bit sequence, the first interleaver matrix is generated, first matrix is l × l,
Expression rounds up；
First circulation displacement is carried out to first matrix according to first circulation shift sequence, obtains the second matrix, wherein described
First circulation shift sequence includes J bit, J >=2 and be integer；
Second circulation displacement is carried out to second matrix according to second circulation shift sequence, obtains third matrix, wherein described
Second circulation shift sequence includes S bit, S >=2 and be integer；
According to the third matrix, N number of second bit sequence is obtained；
Export second bit sequence.
2. the method according to claim 1, wherein the method also includes:
According to a cyclically shifted sequences, the second circulation shift sequence is generated.
3. according to the method described in claim 2, it is characterized in that, the method specifically includes:
The bit value that the second circulation shift sequence includes is the multiple of the corresponding bit value of the first circulation shift sequence
Perhaps score or the second circulation shift sequence are obtained by carrying out sequential transformations to the first circulation shift sequence
?.
4. according to the method described in claim 2, it is characterized in that, the method specifically includes:
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, as the second circulation shift sequence；
Institute's interception way includes any one following combination: according to the sequencing of bit, intercepting S bits from back to front, presses
According to the sequencing of bit, S bits are intercepted from front to back, alternatively, intercepting S1 from back to front according to the sequencing of bit
A bit and the sequencing according to bit intercept S2 bits from front to back, wherein and S1+S2=S, S1 are integer,
S2 is integer, or according to the sequencing of bit, intercepts S1 bits and the sequencing according to bit from back to front,
Interception S2 bits from front to back, wherein S1+S2=S, S1 are integer, and S2 is integer.
5. according to the method described in claim 2, it is characterized in that, the method specifically includes:
S cyclically shifted sequences are intercepted from the J first circulation shift sequence, institute's interception way includes following any one
Kind of combination: intercept S cyclically shifted sequences from back to front according to the sequencing of bit, according to the sequencing of bit from forward direction
S cyclically shifted sequences are intercepted afterwards；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, using S cyclically shifted sequences after sequential transformations as
Second circulation shift sequence.
6. the method according to claim 1, wherein the first circulation shift sequence and the second circulation are moved
Bit sequence can be obtained from preconfigured L longest cyclically shifted sequences, and the J is less than L, and the S is less than L, and the L is
Integer.
7. a kind of interlaced device characterized by comprising
Input interface circuit, for obtaining N number of first bit sequence, the N is integer；
Logic circuit, for generating the first interleaver matrix according to N number of first bit sequence, first matrix is l × l,
Expression rounds up；First circulation shifting is carried out to first matrix according to first circulation shift sequence
Position obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；It is followed according to second
Ring shift sequence carries out second circulation displacement to second matrix, obtains third matrix, wherein the second circulation shifts sequence
Column include S bit, S >=2 and for integer；According to the third matrix, N number of second bit sequence is obtained；
Output interface circuit, for exporting second bit sequence.
8. device according to claim 7, which is characterized in that the logic circuit is also used to, and is moved according to a circulation
Bit sequence generates the second circulation shift sequence.
9. device according to claim 8, which is characterized in that the logic circuit is specifically used for, and the second circulation is moved
The bit value that bit sequence includes is multiple perhaps score or the institute of the corresponding bit value of the first circulation shift sequence
Second circulation shift sequence is stated by carrying out sequential transformations acquisition to the first circulation shift sequence.
10. device according to claim 8, which is characterized in that the logic circuit is specifically used for, from the J first
S cyclically shifted sequences are intercepted in cyclically shifted sequences, as the second circulation shift sequence；Institute's interception way includes following
Any one combination: according to the sequencing of bit intercept from back to front S bit, according to bit sequencing in the past
Interception S bits backward, alternatively, intercepting S1 bits from back to front and according to bit according to the sequencing of bit
Sequencing, intercept the bit of S2 from front to back, wherein S1+S2=S, S1 are integer, and S2 is integer.
11. device according to claim 8, which is characterized in that the logic circuit is specifically used for, from the J first
S cyclically shifted sequences are intercepted in cyclically shifted sequences, institute's interception way includes any one following combination: according to bit
Sequencing intercepts S cyclically shifted sequences from back to front, intercepts S cyclic shift from front to back according to the sequencing of bit
Sequence；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, using S cyclically shifted sequences after sequential transformations as
Second circulation shift sequence.
12. device according to claim 8, which is characterized in that the logic circuit is specifically used for, from preconfigured L
The first circulation shift sequence is obtained in a longest cyclically shifted sequences；And from preconfigured L longest cyclic shift
The second circulation shift sequence is obtained in sequence, the J is less than L, and the S is less than L, and the L is integer.
13. a kind of interlaced device, which is characterized in that described device includes:
Processor, for generating the first interleaver matrix according to N number of first bit sequence, first matrix is l × l,
Expression rounds up；First circulation shifting is carried out to first matrix according to first circulation shift sequence
Position obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；It is followed according to second
Ring shift sequence carries out second circulation displacement to second matrix, obtains third matrix, wherein the second circulation shifts sequence
Column include S bit, S >=2 and for integer；According to the third matrix, N number of second bit sequence is obtained.
14. device according to claim 13, which is characterized in that the processor is also used to, and is moved according to a circulation
Bit sequence generates the second circulation shift sequence.
15. device according to claim 14, which is characterized in that the processor is specifically used for, and the second circulation is moved
The bit value that bit sequence includes is multiple perhaps score or the institute of the corresponding bit value of the first circulation shift sequence
Second circulation shift sequence is stated by carrying out sequential transformations acquisition to the first circulation shift sequence.
16. device according to claim 14, which is characterized in that the processor is specifically used for, and follows from the J first
S cyclically shifted sequences are intercepted in ring shift sequence, as the second circulation shift sequence；Institute's interception way includes following
Any one combination: intercept the bit of S from back to front according to the sequencing of bit, according to the sequencing of bit from forward direction
Interception S bits afterwards, or according to the sequencing of bit, S1 bits and the elder generation according to bit are intercepted from back to front
Sequence afterwards intercepts S2 bits, wherein S1+S2=S, S1 are integer, and S2 is integer from front to back.
17. device according to claim 14, which is characterized in that the processor is specifically used for, and follows from the J first
S cyclically shifted sequences are intercepted in ring shift sequence, institute's interception way includes any one following combination: according to the elder generation of bit
Sequence intercepts S cyclically shifted sequences from back to front, intercepts S cyclic shift sequence from front to back according to the sequencing of bit afterwards
Column；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, using S cyclically shifted sequences after sequential transformations as
Second circulation shift sequence.
18. device according to claim 14, which is characterized in that the processor is specifically used for, from preconfigured L
The first circulation shift sequence is obtained in longest cyclically shifted sequences；And from preconfigured L longest cyclic shift sequence
The second circulation shift sequence is obtained in column, the J is less than L, and the S is less than L, and the L is integer.
19. a kind of interlaced device, which is characterized in that described device includes:
Receiving unit, for receiving N number of first bit sequence, the N is integer；
Processing unit, for generating the first interleaver matrix according to N number of first bit sequence, first matrix is l × l,
Expression rounds up；First circulation shifting is carried out to first matrix according to first circulation shift sequence
Position obtains the second matrix, wherein the first circulation shift sequence includes J bit, J >=2 and be integer；It is followed according to second
Ring shift sequence carries out second circulation displacement to second matrix, obtains third matrix, wherein the second circulation shifts sequence
Column include S bit, S >=2 and for integer；According to the third matrix, N number of second bit sequence is obtained；
Transmission unit, for exporting second bit sequence.
20. device according to claim 19, which is characterized in that the processing unit is also used to, according to a circulation
Shift sequence generates the second circulation shift sequence.
21. device according to claim 20, which is characterized in that the processor is specifically used for, and the second circulation is moved
The bit value that bit sequence includes is multiple perhaps score or the institute of the corresponding bit value of the first circulation shift sequence
Second circulation shift sequence is stated by carrying out sequential transformations acquisition to the first circulation shift sequence.
22. device according to claim 20, which is characterized in that the processor is specifically used for, and follows from the J first
S cyclically shifted sequences are intercepted in ring shift sequence, as the second circulation shift sequence；Institute's interception way includes following
Any one combination: intercept the bit of S from back to front according to the sequencing of bit, according to the sequencing of bit from forward direction
Interception S bits afterwards, or according to the sequencing of bit, S1 bits and the elder generation according to bit are intercepted from back to front
Sequence afterwards intercepts S2 bits, wherein S1+S2=S, S1 are integer, and S2 is integer from front to back.
23. device according to claim 20, which is characterized in that the processor is specifically used for, and follows from the J first
S cyclically shifted sequences are intercepted in ring shift sequence, institute's interception way includes any one following combination: according to the elder generation of bit
Sequence intercepts S cyclically shifted sequences from back to front, intercepts S cyclic shift sequence from front to back according to the sequencing of bit afterwards
Column；
Sequential transformations are carried out to S cyclically shifted sequences of the interception, using S cyclically shifted sequences after sequential transformations as
Second circulation shift sequence.
24. device according to claim 20, which is characterized in that the processor is specifically used for, from preconfigured L
The first circulation shift sequence is obtained in longest cyclically shifted sequences；And from preconfigured L longest cyclic shift sequence
The second circulation shift sequence is obtained in column, the J is less than L, and the S is less than L, and the L is integer.
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| PCT/CN2019/073575 WO2019149180A1 (en) | 2018-01-30 | 2019-01-29 | Interleaving method and interleaving device |
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| WO2019149180A1 (en) | 2019-08-08 |
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