CN105187151B - A kind of production method and system of WCDMA system downlink scrambling code sequence - Google Patents
A kind of production method and system of WCDMA system downlink scrambling code sequence Download PDFInfo
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Abstract
The production method of a kind of WCDMA system downlink scrambling code sequence disclosed by the invention, it is characterised in that the step of comprising following order：The original position for producing the X/Y sequence states needed for corresponding scrambler sequence and storing is inquired about by scrambling code number skew and data length；Take partial data to carry out computing to fast memory by segmentation, the X/Y status datas required for producing current time slots are moved as time slot data length；An I/Q data will be represented with 2 bits, wherein lowest bit represents I roads, and highest bit represents Q roads, places and exports from lowest bit to the highest-order bit in units of 32 bits successively per 32 road I/Q scrambler sequences caused by time slot.The method of the present invention, the scrambler sequence of corresponding plural numberization can be quickly produced for arbitrary downlink scrambling code number.
Description
Technical field
The present invention relates to communication technical field, the production method of more particularly to a kind of WCDMA system downlink scrambling code sequence and
System.
Background technology
In WCDMA (Wide Band Code Division Multiple Access, WCDMA) system,
Base station determines the scope of coverage cell by the coverage of broadcast message.Different base station is distinguished descending to disturb mainly by different
Code, each cell transmission down link signal carry out scrambling processing using different scrambler sequences.
3GPP TS 25.213(the 3rd Generation Partner Project Technical
Specifications 25.213) in the m-sequence that is made up of two 18 rank shift register X/Y of regulation scrambler sequence, then
The Gold code sequences that two m-sequences are added again.Gold code sequences are the compound key sequences of m-sequence, often change two m-sequences
Relative phase will obtain a new Gold code sequence.WCDMA downlink scrambling code comparisons are more, using scrambling code number as two m
Sequence relative phase difference, to produce different Gold code sequences, then by two Gold code reality sequences scrambler is combined into, that is, realized not
Different scrambler sequences is corresponded to downlink scrambling code.Mode caused by WCDMA downlink scrambling codes, determine that WCDMA scrambler sequences have
Standby good auto-correlation and cross correlation.X and Y sequence constructs method and scrambler generating process are as follows：
Primary condition：
X sequence Xs (0)=1, X (1)=X (2)=... X (16)=X (17)=0 is formed, Y sequences
Y (0)=Y (1)=...=Y (16)=Y (17)=1.
X/Y sequence other values are obtained by the way that mode is calculated as below：
X (i+18)=(X (i+7)+X (i)) mod2, i=0,1 ... 218-20.N-th of Gold
Code sequence Zn, n=0,1,2 ..., 218- 2 are defined as：
Zn(i)=(X ((i+n) mod (218- 1))+Y (i)) mod2, i=0 ... 218-2。
Binary sequence is converted into real sequence Zn：
Scrambling code number is that scrambler corresponding to n is calculated as follows：
Sdl,n(i)=Zn(i)+jZn((i+M)mod(218), -1) i=0,1 ..., 38399.
Wherein j represents imaginary unit, and the M=131072 sequences can produce 2 altogether18- 1 scrambler, it is used only at present wherein
8192 scramblers, scrambling code number k=0,1 ..., 8191.
A 10ms radio frames are formed by 38400 chips in a wcdma system, a radio frames divide 15 time slots, often
2560 chips of time slot.Scrambler sequence is produced by single time slot, if the caused time is more than the duration of 1 time slot, then
Gross error occurs by time slot scrambling in transmitting terminal, if the every chip of single time slot scrambler sequence is with Word (every Word 32 in addition
Bit) stored for unit and also relatively expend internal memory.
Speed caused by scrambler directly influences down channel treatment effeciency, although prior art provides several scrambler productions
Raw specific way, but caused speed, resource occupation, power consumption all existing defects.
" multiple disturbing code parallel generator and its method in WCDMA cell searchings " patent, disclose a kind of disturbing code parallel and produce
Method, but every time output only produce a 8 road I/Q data, that is, export 8 plural numberization scrambler sequences, parallel output it is inefficient.
A kind of " scrambling generator and its implementation for WCDMA system " patent, scrambler produce process and used very
More X/Y status registers, occupy more hardware resource, only export 3 road I/Q data during each scrambler output in addition, parallel defeated
Go out 3 plural numberization scrambler sequences, treatment effeciency is low.
“Method and apparatus for generation of downlink scrambling code in
Wideband CDMA mobile devices " patents, the mode that this foreign language patent also allows for segment processing export scrambler sequence
Row, but disturbing code parallel output is less efficient.
The content of the invention
The shortcomings that it is an object of the invention to overcome prior art and deficiency, there is provided a kind of WCDMA system downlink scrambling code sequence
The production method of row.
Another object of the present invention is to provide a kind of generation system of WCDMA system downlink scrambling code sequence.
The purpose of the present invention is realized by following technical scheme：
A kind of production method of WCDMA system downlink scrambling code sequence, the step of comprising following order：
S1. deposited by scrambling code number skew and data length to inquire about the X/Y sequence states produced needed for corresponding scrambler sequence
The original position of storage；
S2. by segmentation take partial data to fast memory carry out computing, by time slot data length move generation it is current when
X/Y status datas required for gap；
S3. an I/Q data, wherein lowest bit table will be represented with 2 bits per 32 road I/Q scrambler sequences caused by time slot
Show I roads, highest bit represents Q roads, places and exports from lowest bit to the highest-order bit in units of 32 bits successively.
Described step S1 is specially：Scrambler generation device produces the rank shift LDs of X/Y 18 using X/Y sequences initial value
X/Y state values required for device state value, every time slot complex scrambling code Sequence Operation Theory, and state value is pressed into bit storage, root respectively
Status data required for calculating scrambler sequence real and imaginary parts according to scrambling code number and per time slot complex scrambling code sequence length offset lookup
Original position.
Described X/Y sequence initial values are according to as defined in agreement 3GPP TS 25.213.
The described rank shift register state values of X/Y 18 storage and internal memory at a slow speed, described every time slot complex scrambling code sequence
X/Y state values required for computing are stored in fast memory.
The scope of described scrambling code number is 0~8191.
Described step S2 is specially：When current time slots are producing scrambler, next time slot X/Y states storage starting is obtained
X/Y status datas are simultaneously moved fast memory by position, for producing next time slot complex scrambling code sequence.
Described next time slot X/Y states storage original position is obtained by 18 rank X/Y shift register state inquiry units
Take.
Described step S3 is specially：The operation of scrambler output each time needs to take two group of 32 bit X/Y state value, according to disturbing
Code calculation formula can calculate the real and imaginary parts of 32 scrambler sequences respectively, then 32 bit imaginary parts and 32 bit real parts are intersected
Storage, form 2 32 bit complex scrambling codes outputs.
Another object of the present invention is realized by following technical scheme：
A kind of generation system of WCDMA system downlink scrambling code sequence, including
18 rank X/Y shift register state inquiry units, corresponded to by scrambling code number skew and data length to inquire about to produce
The original position of X/Y sequence states storage needed for scrambler sequence；
Status data Filtting device, partial data is taken to carry out computing to fast memory by segmentation, by time slot data length
Move the X/Y status datas required for generation current time slots；
And generation and the road plural numberization scrambler sequence device of parallel output 32, will be per 32 road I/Q scrambler sequences caused by time slot
Row, an I/Q data is represented with 2 bits, wherein lowest bit represents I roads, and highest bit represents Q roads, successively using 32 bits to be single
Placed from lowest bit to the highest-order bit position.
The generation system of described WCDMA system downlink scrambling code sequence, in addition to scrambler generation device, utilize X/Y sequences
Initial value produces the rank shift register state values of X/Y 18, per the X/Y state values required for time slot complex scrambling code Sequence Operation Theory.
The present invention compared with prior art, has the following advantages that and beneficial effect：
1st, the present invention can quickly produce the scrambler sequence of corresponding plural numberization for arbitrary downlink scrambling code number.This method is every
Energy 32 complex scrambling code sequences of parallel output during secondary progress scrambler sequence of complex numbers output, while the I/Q after generation plural numberization is disturbed
Code data press bit storage, i.e., a scrambler sequence of complex numbers is represented per dibit.Downlink scrambling code sequence is deposited by bit-wise output
On the one hand storage purpose is to compress memory space, on the other hand carry out spread spectrum code sequence and scrambler during Scrambling Operation for convenience
The operation of sequence multiplication replaces with xor operation so as to improve processing speed.
2nd, X/Y status register values of the present invention need not calculate in real time during scrambler generation, reduce cyclic shift meter
The number of calculation, reduce shift register resource occupation.
3rd, processor pipeline feature is taken into full account during data-moving of the present invention, improves treatment effeciency, in addition once
Scrambler can export 32 road complex scrambling code sequences simultaneously when exporting, quick to improve scrambler delivery efficiency.
Brief description of the drawings
Fig. 1 is a kind of structural representation of the generation system of WCDMA system downlink scrambling code sequence of the present invention.
Fig. 2 is the circuit diagram of scrambler generation device of the present invention.
Embodiment
With reference to embodiment and accompanying drawing, the present invention is described in further detail, but embodiments of the present invention are unlimited
In this.
Embodiment one
A kind of production method of WCDMA system downlink scrambling code sequence, the step of comprising following order：
S1. according to as defined in agreement 3GPP TS 25.213 scrambler generation device as shown in Fig. 2 utilizing the device and agreement
Defined X/Y sequences initial value, can produce the rank shift register state values of X/Y 18 respectively, state value respectively by bit storage and
It is stored in internal memory at a slow speed.Produce the X/Y state values required for per time slot complex scrambling code Sequence Operation Theory and be located at fast memory, according to disturbing
Code number (scope 0~8191) and every time slot complex scrambling code sequence length offset lookup are calculated required for scrambler sequence real and imaginary parts
The original position of status data；
S2. the X/Y status switches according to needed for being obtained in step 1 and produce every time slot complex scrambling code sequence real and imaginary parts are deposited
The position of storage, the X/Y status datas produced needed for current time slots complex scrambling code sequence real and imaginary parts are moved using Filtting device.
When current time slots are producing scrambler, next time slot X/Y states are obtained by inquiry unit and store original position and by X/Y states
Data-moving is to fast memory, for producing next time slot complex scrambling code sequence；
S3. obtain calculating time slot complex scrambling code sequence real part as step 2 in being operated, X/Y state values needed for imaginary part, each time
Scrambler output operation is needed to take two group of 32 bit X/Y state value, and 32 scrambler sequences can be calculated respectively according to scrambler calculation formula
The real and imaginary parts of row, then 32 bit imaginary parts and 32 bit real part interleaveds, 2 32 bit complex scrambling codes of formation are exported.
Such as Fig. 1, a kind of generation system of WCDMA system downlink scrambling code sequence, including
18 rank X/Y shift register state inquiry units, corresponded to by scrambling code number skew and data length to inquire about to produce
The original position of X/Y sequence states storage needed for scrambler sequence；
Status data Filtting device, partial data is taken to carry out computing to fast memory by segmentation, by time slot data length
Move the X/Y status datas required for generation current time slots；
And generation and the road plural numberization scrambler sequence device of parallel output 32, will be per 32 road I/Q scrambler sequences caused by time slot
Row, an I/Q data is represented with 2 bits, wherein lowest bit represents I roads, and highest bit represents Q roads, successively using 32 bits to be single
Placed from lowest bit to the highest-order bit position.
Embodiment two
The present invention provides one kind and is used for method caused by WCDMA system downlink scrambling code, can quickly produce arbitrarily descending disturb
Complex scrambling code sequence corresponding to code number.
(1) 18 rank X/Y buffer status values pre-stored first, X/Y state values are currently according to scrambler hair as shown in Figure 2
Raw circuit produces, with reference to X/Y status register initial phase X (0)=1, X (1)=X (2)=... X (16)=X (17)=0, Y
(0)=Y (1)=...=Y (16)=Y (17)=1, sequentially successively store X Y status registers value, a total of 218It is individual
State.It is about 8192Word by bit storage, it is 16384Word that X/Y sequences take memory space altogether, considers space-consuming ratio
It is more, therefore X/Y status register tables are placed on outside internal memory at a slow speed.According to downlink scrambling code number and time slot scrambler length computation X/
Y state values are offset, is searched using position deviant in X/Y status register tables needed for the original position that stores of X/Y state values；
In Fig. 2, the scrambler generation device figure is mainly by based on generator polynomial 1+X7+X1818 rank cyclic shift X of generation
Gold sequence and based on generator polynomial 1+X5+X7+X10+X18The 18 rank cyclic shift Y Gold sequences composition of generation.X/Y sequences
WCDMA downlink scrambling codes number are equipped with respect to carry-out bit to determine, correspondence position X/Y sequence state values are obtained by corresponding scrambling code number,
So as to obtain the output of correspondence position complex scrambling code series I roads, there are 131072 state delays in the output of Q roads with the output of I roads.
(2) by above-mentioned 1 original position for obtaining the storage of X/Y state values, 80 Word X/Y state values are taken respectively to soon
Fast internal memory carries out complex scrambling code sequence single time slot real part and calculated, and 4096 Word are offset from X/Y state values original position is obtained,
Take 80Word X/Y status data values to calculate the imaginary part of single time slot complex scrambling code sequence respectively again, at the same record need to move it is next
The position of the X/Y status datas of individual time slot, when a upper time slot carries out disturbing code parallel output, immediately by next time slot institute
The X/Y state values needed move fast memory, are easy to next time slot complex scrambling code sequence to produce and export；
(3) according to downlink scrambling code representation formula (1) and formula (2):
Sdl,n(i)=Zn(i)+jZn((i+131072)mod(218), -1) i=0,1 ..., 38399 (1)
Zn(i)=(X ((i+n) mod (218- 1))+Y (i)) mod2, i=0 ..., 218-2 (2)
Complex scrambling code is produced to first have to calculate real part ZnAnd imaginary part Z (i)n(i+131072), the real part of this method scrambler
Calculated simultaneously with imaginary part, the imaginary part of each scrambler sequence is skew 131072 bits i.e. 4096 Word relative to real part, often
Take 2 group of 32 bit X/Y state value during the output of secondary scrambler, one group of X/Y carries out nodulo-2 addition computings by 32 and obtains real part, another group
Imaginary part is obtained by 32 nodulo-2 addition computings.The road I of Zai Jiang 32 and 32 road Q, storage is placed in the way of every 2 bit QI, it is final every
2 32 complex scrambling code sequences of secondary output, reference can be made to last output storage result as shown in Figure 1.
Above-described embodiment is the preferable embodiment of the present invention, but embodiments of the present invention are not by above-described embodiment
Limitation, other any Spirit Essences without departing from the present invention with made under principle change, modification, replacement, combine, simplification,
Equivalent substitute mode is should be, is included within protection scope of the present invention.
Claims (10)
1. a kind of production method of WCDMA system downlink scrambling code sequence, it is characterised in that the step of comprising following order：
S1. stored by scrambling code number skew and data length to inquire about the X/Y sequence states produced needed for corresponding scrambler sequence
Original position；
S2. take partial data to carry out computing to fast memory by segmentation, moved by time slot data length and produce current time slots institute
The X/Y status datas needed；
S3. an I/Q data will be represented with 2 bits, wherein lowest bit represents I per 32 road I/Q scrambler sequences caused by time slot
Road, highest bit represent Q roads, are placed and exported from lowest bit to the highest-order bit in units of 32 bits successively；
Specially：
(1) 18 rank X/Y buffer status values pre-stored first, X/Y state values are produced by disturbing code generating circuit, with reference to X/Y states
Register initial phase
X (0)=1, X (1)=X (2)=... X (16)=X (17)=0,
Y (0)=Y (1)=...=Y (16)=Y (17)=1,
Sequentially successively store X Y status registers value, a total of 218 states；It is about by bit storage
It is 16384Word that 8192Word, X/Y sequence take memory space altogether, therefore X/Y status register tables are placed on into outside at a slow speed
Internal memory；
Offset according to downlink scrambling code number and time slot scrambler length computation X/Y state values, using position deviant in X/Y Status registers
The original position of X/Y state values storage needed for being searched in device table；
(2) original position of X/Y state values storage is obtained by above-mentioned steps (1), takes 80 Word X/Y state values to arrive respectively
Fast memory carries out complex scrambling code sequence single time slot real part and calculated, and 4096 are offset from X/Y state values original position is obtained
Word, then the imaginary part for taking 80Word X/Y status data values to calculate single time slot complex scrambling code sequence respectively, while record needs and remove
The position of the X/Y status datas of next time slot is moved, immediately will be next when a upper time slot carries out disturbing code parallel output
X/Y state values required for time slot move fast memory, are easy to next time slot complex scrambling code sequence to produce and export；
(3) according to downlink scrambling code representation formula (1) and formula (2):
Sdl,n(i)=Zn(i)+jZn((i+131072)mod(218), -1) i=0,1 ..., 38399 (1)
Zn(i)=(X ((i+n) mod (218- 1))+Y (i)) mod 2, i=0 ..., 218-2 (2)
Complex scrambling code is produced to first have to calculate real part ZnAnd imaginary part Z (i)n(i+131072) real part and void of scrambler are calculated, while
Portion, the imaginary part of each scrambler sequence are skew 131072 bits i.e. 4096 Word relative to real part, take 2 groups during each scrambler output
32 bit X/Y state values, one group of X/Y carry out nodulo-2 addition computing by 32 and obtain real part, and another group is pressed 32 nodulo-2 addition computings
Obtain imaginary part；The road I of Zai Jiang 32 and 32 road Q, storage is placed in the way of every 2 bit QI, final 2 32 plural numbers of output every time
Scrambler sequence, that is, obtain output storage result.
2. the production method of WCDMA system downlink scrambling code sequence according to claim 1, it is characterised in that described step
Suddenly S1 is specially：Scrambler generation device produces the rank shift register state values of X/Y 18 using X/Y sequences initial value, answered per time slot
X/Y state values required for number scrambler sequence computing, and state value is pressed into bit storage respectively, answered according to scrambling code number and per time slot
The original position of status data required for number scrambling code sequence length offset lookup calculates scrambler sequence real and imaginary parts.
3. the production method of WCDMA system downlink scrambling code sequence according to claim 2, it is characterised in that described X/Y
Sequence initial value is according to as defined in agreement 3GPP TS 25.213.
4. the production method of WCDMA system downlink scrambling code sequence according to claim 2, it is characterised in that described X/Y
18 rank shift register state values are stored with internal memory at a slow speed, the X/Y shapes required for described every time slot complex scrambling code Sequence Operation Theory
State value is stored in fast memory.
5. the production method of WCDMA system downlink scrambling code sequence according to claim 2, it is characterised in that described disturbs
The scope of code number is 0~8191.
6. the production method of WCDMA system downlink scrambling code sequence according to claim 1, it is characterised in that described step
Suddenly S2 is specially：When current time slots are producing scrambler, next time slot X/Y states storage original position is obtained and by X/Y states
Data-moving is to fast memory, for producing next time slot complex scrambling code sequence.
7. the production method of WCDMA system downlink scrambling code sequence according to claim 6, it is characterised in that under described
One time slot X/Y states storage original position is obtained by 18 rank X/Y shift register states inquiry units.
8. the production method of WCDMA system downlink scrambling code sequence according to claim 1, it is characterised in that described step
Suddenly S3 is specially：The operation of scrambler output each time needs to take two group of 32 bit X/Y state value, can be distinguished according to scrambler calculation formula
The real and imaginary parts of 32 scrambler sequences are calculated, then 32 bit imaginary parts and 32 bit real part interleaveds, formation are compared for 2 32
Special complex scrambling code output.
9. production method for realizing WCDMA system downlink scrambling code sequence described in claim 1 to 8 any claim
A kind of generation system of WCDMA system downlink scrambling code sequence, it is characterised in that including
18 rank X/Y shift register state inquiry units, corresponding scrambler is produced to inquire about by scrambling code number skew and data length
The original position of X/Y sequence states storage needed for sequence；
Status data Filtting device, take partial data to carry out computing to fast memory by segmentation, moved by time slot data length
Produce the X/Y status datas required for current time slots；
And generation and the road plural numberization scrambler sequence device of parallel output 32, it will be used per 32 road I/Q scrambler sequences caused by time slot
2 bits represent an I/Q data, and wherein lowest bit represents I roads, and highest bit represents Q roads, successively in units of 32 bits from
Lowest bit is placed to the highest-order bit.
10. the generation system of WCDMA system downlink scrambling code sequence according to claim 9, it is characterised in that described
The generation system of WCDMA system downlink scrambling code sequence, in addition to scrambler generation device, X/Y is produced using X/Y sequences initial value
X/Y state values required for 18 rank shift register state values, every time slot complex scrambling code Sequence Operation Theory.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1925377A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Device and method for generation of WCDMA descending multiple scrambling codes |
| CN1929321A (en) * | 2005-09-05 | 2007-03-14 | 中兴通讯股份有限公司 | Multiple disturbing code parallel generator in WCDMA cell search and its method |
| CN101262296A (en) * | 2007-06-20 | 2008-09-10 | 中兴通讯股份有限公司 | A scrambled code generator for WCDMA system and its realization method |
| CN101562820A (en) * | 2008-04-16 | 2009-10-21 | 中兴通讯股份有限公司 | Device for measuring received signal code power in mobile communication system |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1925377A (en) * | 2005-08-29 | 2007-03-07 | 中兴通讯股份有限公司 | Device and method for generation of WCDMA descending multiple scrambling codes |
| CN1929321A (en) * | 2005-09-05 | 2007-03-14 | 中兴通讯股份有限公司 | Multiple disturbing code parallel generator in WCDMA cell search and its method |
| CN101262296A (en) * | 2007-06-20 | 2008-09-10 | 中兴通讯股份有限公司 | A scrambled code generator for WCDMA system and its realization method |
| CN101562820A (en) * | 2008-04-16 | 2009-10-21 | 中兴通讯股份有限公司 | Device for measuring received signal code power in mobile communication system |
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