CN1929321A - Multiple disturbing code parallel generator in WCDMA cell search and its method - Google Patents
Multiple disturbing code parallel generator in WCDMA cell search and its method Download PDFInfo
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- CN1929321A CN1929321A CNA200510098299XA CN200510098299A CN1929321A CN 1929321 A CN1929321 A CN 1929321A CN A200510098299X A CNA200510098299X A CN A200510098299XA CN 200510098299 A CN200510098299 A CN 200510098299A CN 1929321 A CN1929321 A CN 1929321A
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Abstract
This invention discloses one multiple interference codes in WCDMA area generator and its method, which comprises the following parts: X/Y sequence computation module, eight pairs of X shield module, one pair of Y shield module, odd and even computer and mode add machine, wherein, the X sequence computation module comprises register with X sequence initial phase values; the said Y sequence computation module compress the register with Y sequence initial phase. Through setting interference codes set zero codes initial phase value to generate designed phase X/Y sequence and the two add machine is to compute interference cods part and virtual part sequence.
Description
Technical field
The present invention relates to a kind of Wideband Code Division Multiple Access (WCDMA) WCDMA (Wide CodeMultiple Access) wireless communication system and method for communication field, what be specifically related to is multiple disturbing code parallel generation device and multiple disturbing code parallel production method thereof in the code character in the search of a kind of WCDMA system cell.
Background technology
Among 3-G (Generation Three mobile communication system), in order to realize communication good between mobile phone and the base station and transmission of Information each other, among the communication system between the downlink paths is very important synchronously, Europe employed WCDMA system, realize synchronous step because do not use GPS as U.S. CDMA2000 system, in order to reach the synchronous of downlink paths, just must have a kind of special mechanism to go to realize synchronous step, this step is referred to as Cell searching (cell search).
In the cell search process, mobile phone searching cell signal and obtain the down link scrambler sequence of current area and the frame synchronization of common signal channel comprises following three steps: 1) slot synchronization (SlotSynchronization); 2) frame synchronization and code group identification (Frame Synchronization ﹠amp; CodeGroup Identification); 3) scrambler identification (Scramble Code Identification).
Each sub-district in the WCDMA system is distinguished by the scrambler of down link, scrambler length 38,400 chips, and 38,400 chips constitute a wireless frame length, and a radio frames is divided into 15 time slots (slot), each time slot 2,560 chip.At least need to use three channels in the cell search process: primary synchronization channel (P-SCH), auxiliary synchronization channel (S-SCH), Common Pilot Channel (CPICH).Primary synchronization channel and auxiliary synchronization channel are referred to as synchronizing channel (SCH) together, and the base station utilizes synchronizing channel to mobile phone transmitting synchronous sign indicating number sequence.
Primary synchronization channel, each time slot begin to transmit 256 chip Primary Synchronisation Code sequences, unique identical Primary Synchronisation Code sequence is all transmitted in the beginning of all time slots in all sub-districts.
The code word binding sequence of the different code characters of auxiliary synchronous code Channel Transmission, one group 15 different sign indicating number sequences, the corresponding sign indicating number sequence of each time slot, the secondary synchronization code sequences that begins to transmit 256 chips of time slot, for identical code character, each frame data only need repeat corresponding sign indicating number sequence.In case mobile phone receives auxiliary synchronization channel, also just obtain corresponding frame synchronization, slot synchronization, cell scrambling code group information.
Common Pilot Channel is non-modulation encoding channel, and by the main scrambler sequence scrambler of current area, transmission is by the down public guide frequency symbol of base station scrambler sequence scrambling.
Three steps of the Cell searching of WCDMA system realize by following three passages: 1) utilize the Primary Synchronisation Code of synchronizing channel, by incoherent correlator related operation, realize the synchronous of boundary of time slot; 2) utilize the secondary synchronization code of synchronizing channel, by FHT correlator related operation, the achieve frame border synchronously and the scrambler group discern; 3) utilize Common Pilot Channel identification scrambler.
The length of down link scrambler sequence is 38,400 chips, and one has 2
18-1 scrambler sequence, the WCDMA system only uses the part scrambler sequence at present, these scrambler sequence are divided into 512 collection, each collection comprises 1 main scrambler sequence and 15 scrambler sequence, in order to reduce the complexity of WCDMA Cell searching, main scrambler collection is that unit is divided into 64 scrambler groups with the group, and every group comprises 8 main scrambler sequence, and each sub-district only disposes a main scrambler.
In the step 3 of cell search process, because step 2 has been confirmed the code character at current area scrambler place, so the required processing of this step, only need to detect the accurate main scrambler that current area is used, the affirmation of main scrambler is by doing the related operation of Symbol level to the data of CPICH channel, eight main scrambler sequence in the code character are input to correlation receiver, a Symbol in the cycle the scrambler group of having discerned in the I of all main scrambler sequence and receiving terminal input and Q sampled signal carry out correlation computations and survey the scrambler that CPICH uses, the third step of finishing search has promptly realized discerning the purpose of main scrambler.
Illustrate the structural representation of step 3 scrambler identification module in the cell searching system as Fig. 1, wherein portable terminal is by the antenna downlink data receiving, after a series of signal processing, I and Q circuit-switched data are input to correlator block 120, correlator block comprises a plurality of parallel correlators 121, mainly to the despreading of I/Q data de-scrambling.Scrambler generation module 110 parallel generations are measured 8 main scramblers that block number comprises simultaneously, and it is measured by step 2 frame synchronization and code group identification.Scrambler register initial value computing module 111 is used for calculating in this block number first and is offset the register 0 phase place initial value of main scrambler and time slot (slot) or symbol (symbol) level phase place initial value when locating fast, the main scrambler of its group disturbing code parallel generator 112 outputs.The input of single correlator 121 comprises the main scrambler of second deviation post in I/Q data and the block number, and each correlator is all imported the main scrambler and identical I/Q data of the deviation post in the corresponding block number.The dateout of correlator block is input to the performance number that power computation module 130 calculates the despread data of each main scrambler correspondence, relatively judge the power maximum through peak detection block 140, the main scrambler of its correspondence is the used main scrambler of current area.
Fig. 2 shows the conventional method of a scrambler generation module 110 of prior art, at first obtain first skew scrambler register initial phase, obtain the register initial phase of 8 scramblers in the code character then by all scrambler initial phase modules 220 of code character by first skew scrambler initial phase module 230 of code character.Be input to scrambler generator module 210 then and calculate 8 scramblers, this scrambler generator module comprises 8 single scrambler generators, and each scrambler generator calculates one of them scrambler in the code character.
In above-mentioned steps, the generation that need walk abreast of 8 main scrambler sequence, if utilize 8 main scrambler sequence of the parallel generation of 8 scrambler generators, it is very huge so just having caused taking of hardware resource, also needs the initial phase of extra 8 scramblers of logical resource calculating simultaneously or utilizes ROM to store the initial phase of scrambler.It is huge to cause hardware resource to expend like this, and simple algorithm is parallel rapidly to produce 8 main scrambler sequence so prior art need be used, and takies less hardware resource, to realize the requirements at the higher level to chip design.
Summary of the invention
The purpose of this invention is to provide and a kind ofly take less hardware resource, need not 8 scrambler initial phases of extra computation or utilize ROM storage scrambling code phase, only can walk abreast in conjunction with shroud module by the 0th scrambler initial phase in the code character produces the multiple disturbing code parallel generator and the multiple disturbing code parallel production method thereof of 8 scramblers in the code character.
Technical scheme of the present invention comprises:
Multiple disturbing code parallel generator in a kind of WCDMA Cell searching, wherein, comprise as lower module: X sequence computing module, Y sequence computing module, eight pairs of X shroud modules, a pair of Y shroud module, several parity calculations devices of correspondence and a plurality of modular two addition devices of correspondence;
Described X sequence computing module comprises the register of depositing X sequence initial phase place value, be used for by presetting the register initial phase place value of the 0th scrambler of scrambler code character, produce the X sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described Y sequence computing module comprises the register of depositing Y sequence initial phase place value, be used for by presetting the register initial phase place value of the 0th scrambler of scrambler code character, can produce the Y sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described shroud module is used for the inner link according to the register initial value phase place of each main scrambler of scrambler code character, the fixing logical operation formula in the realization scrambler code character between the register initial value phase place of the register initial value phase place of the 0th main scrambler and other main scramblers;
Described parity calculations device is used for calculating 16 Bit data results' 1 of above-mentioned a plurality of shroud modules number, and judges that number is even number or odd number;
Described modular two addition device is used for calculating the real part and the imaginary part sequence of scrambler by the output of parity calculations device the I road of correspondence and Q road is done mould two and added as a result.
Described parallel generator, wherein, described shroud module comprises 18, respectively corresponding 8 scramblers, the corresponding fixing logical operation value of each shroud module, be masking value, utilize masking value that 18 bit register values of the output of described X, Y sequence computing module are done masking operation by shroud module, parallel computation goes out to participate in the scrambler group the 0th～7 scrambler X, the Y sequential register related bits position of totally 8 scrambler computings.
Described parallel generator, wherein, the structure of described shroud module is set to corresponding sequence computing module register value and is input to corresponding shroud module, with the masking value step-by-step with, pick out the related bits position that needs to participate in the scrambler subsequent calculations, again each bit of calculated data is done XOR, obtaining in the result 1 expression data 1 number is odd number, and 0 expression is an even number.
Multiple disturbing code parallel production method in a kind of WCDMA Cell searching, it may further comprise the steps:
A, determine in the multiple disturbing code parallel generator in the corresponding scrambler group initial value of the register in the register initial value and Y sequence computing module in the X sequence computing module of the 0th scrambler, carry out the self feed back computing by primitive polynomial separately, export the value of register separately simultaneously;
The register value of B, described X, Y sequence computing module is input to eight pairs of X shroud modules, a pair of Y shroud module respectively, respectively parallel computation go out to participate in 8 scrambler computings through the X sequential register related bits position of the corresponding phase separately of being shifted and participate in the Y sequential register related bits position without displacement of 8 scrambler computings;
The result of calculation of C, described shroud module is input in 18 parity calculations devices totally, and calculating among each shroud module output result 1 number is odd number or even number;
The result of calculation of D, described parity calculations device is input to the modular two addition device to correspondence respectively carries out mould two and adds computing, generates the real part sequence and the imaginary part sequence of 8 scramblers respectively.
Multiple disturbing code parallel generator and multiple disturbing code parallel production method thereof in a kind of WCDMA Cell searching provided by the present invention, owing to utilize a scrambler generator in conjunction with 8 scrambler sequence of the parallel generation of masking value mode, by setting the register initial value of the 0th scrambler in the code character, produce 8 scrambler sequence of this code character in the masking value mode, only needing increases small number of logic gates on the basis of single scrambler generator, and on general structure, just 8 scrambler generators can be reduced to a scrambler generator, also reduce simultaneously the calculating and the storage of other scrambler generator initialization phase places, reduced a large amount of hardware resources.
Description of drawings
Below by in conjunction with the accompanying drawings realization of the present invention being described in detail, above-mentioned and other purposes, characteristic, advantage of the present invention will become clearer, wherein
Fig. 1 is the schematic diagram that the Wideband Code Division Multiple Access (WCDMA) of prior art inserts the function structure that scrambler is discerned in the Cell searching in (WCDMA) system;
Fig. 2 is the schematic diagram of 8 disturbing code parallel generation modules of code character conventional method in the Cell searching of prior art;
Fig. 3 is the electrical block diagram of single scrambler generation module in the multiple disturbing code parallel generator in the WCDMA Cell searching of the present invention;
Fig. 4 is the schematic diagram of 8 disturbing code parallel generation modules that code character comprises in the Cell searching of realizing according to the present invention;
Fig. 5 is the single scrambler generator realized according to the present invention circuit diagram in conjunction with the multiple disturbing code parallel generator of shroud module mode;
Fig. 6 is the shroud module structural representation of multiple disturbing code parallel generator in the WCDMA Cell searching of the present invention.
Embodiment
Hereinafter will be described further technical scheme of the present invention by the reference accompanying drawing and to the description of embodiment:
The core concept of multiple disturbing code parallel generator is in the WCDMA Cell searching of the present invention: according to the inner link of the initial value phase place of each main scrambler in the scrambler code character, derive the register initial value phase place of first main scrambler in the scrambler code character and the register initial value phase place of other main scramblers a fixing operational formula is arranged, here be referred to as shroud module for the time being, the register value conversion when this operation relation also is suitable for any phase place of other correspondences simultaneously.Utilize a scrambler generator in conjunction with 8 scrambler sequence of the parallel generation of shroud module mode, produce 8 scrambler sequence with shielding mode, only needing increase small number of logic gates on the basis of single scrambler generator.Just 8 scrambler generators can be reduced to a scrambler generator, also reduce the calculating and the storage of other scrambler generator initialization phase places simultaneously, will save a large amount of hardware resources.
Multiple disturbing code parallel generator of the present invention comprises as shown in Figure 5 as lower module: X sequence computing module, Y sequence computing module, the eight pairs of X shroud modules, a pair of Y shroud module, parity calculations device A～R, modular two addition device AC～AQ, modular two addition device BC～BQ.
Described X sequence computing module comprises the register of depositing X sequence initial phase place value, by presetting the register initial phase place value of the 0th scrambler in the scrambler code character, can produce the X sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described Y sequence computing module comprises the register of depositing Y sequence initial phase place value, by presetting the register initial phase place value of the 0th scrambler in the scrambler code character, can produce the Y sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described shroud module is according to the inner link of the register initial value phase place of each main scrambler in the scrambler code character, the register initial value phase place of the register initial value phase place of the 0th main scrambler and other main scramblers has a fixing logical operation formula respectively in the scrambler code character, shroud module is realized this logical relation exactly, 8 corresponding altogether 18 shroud modules of scrambler, the corresponding fixing logical operation value of each shroud module, be referred to as masking value, utilize masking value to X by shroud module, 18 bit register values of the output of Y sequence computing module are done masking operation, and parallel computation goes out to participate in the scrambler group the 0th～7 the scrambler X of totally 8 scrambler computings, Y sequential register related bits position.
Parity calculations device A～R: 1 number among the 16 Bit data results of a plurality of shroud modules that this part of module calculating is above-mentioned, and judge that number is even number or odd number;
Modular two addition device AC～AQ: this part of module calculates the real part sequence of scrambler by the output of parity calculations device A～R is done mould two and added in the I road of correspondence as a result;
Modular two addition device BC～BQ: this part of module calculates the imaginary part sequence of scrambler by the output of parity calculations device A～R is done mould two and added in the Q road of correspondence as a result.
The workflow of multiple disturbing code parallel generator of the present invention is as follows:
At first determine in the multiple disturbing code parallel generator in the corresponding scrambler group initial value of the register in the register initial value and Y sequence computing module in the X sequence computing module of the 0th scrambler, carry out the self feed back computing by primitive polynomial separately, export the value of register separately simultaneously.
The register value of X, Y sequence computing module is input to eight pairs of X shroud modules, a pair of Y shroud module respectively then, respectively parallel computation go out to participate in 8 scrambler computings through the X sequential register related bits position of the corresponding phase separately of being shifted and participate in the Y sequential register related bits position without displacement of 8 scrambler computings.
Then, the result of calculation of shroud module is input to parity calculations device A to parity calculations device R in totally 18 parity calculations devices, and calculating among each shroud module output result 1 number is odd number or even number.
At last, parity calculations device A is input to modular two addition device AC to modular two addition device AQ to the result of calculation of R to correspondence respectively, wherein parity calculations device B output as modular two addition device BD to one of input of modular two addition device BR, and parity calculations device C, D is to Q, R is respectively as modular two addition device AC, BD is to AQ, the another one input of BR, modular two addition device AC like this, BD is to AQ, BR does mould two to input and adds the sequence that generates 8 scramblers, the real part sequence SI0 that modular two addition device AC generates 8 scramblers respectively to modular two addition device AQ is to SI7, and modular two addition device BC generates the imaginary part sequence SQ0 of 8 scramblers respectively to SQ7 to modular two addition device BQ.
In the multiple disturbing code parallel generator, described scrambler sequence is that complex sequences obtains by the real sequence of synthetic two Gold sign indicating numbers in the WCDMA Cell searching of the present invention.The Gold sign indicating number is by two different m-sequence binary system moulds two are added, by two binary m sequences of generator polynomial generation on two 18 rank, and two real sequences of 38400 chip step-by-step exclusive-OR formations of these two m sequences.Sequence is formed Gold sequence sets fragment as a result.The radio frames of the every 10ms of scrambler repeats once, makes that x and y respectively are two m sequences, and the x sequence is by primitive polynomial 1+X
7+ X
18Generate, the y sequence is by primitive polynomial 1+X
5+ X
7+ X
10+ X
18Generate.
The real sequence nucleotide sequence of Gold sign indicating number that depends on selected scrambler sequence number n is designated as z
nIn addition, make x (i), y (i) and z
n(i) represent sequence x, y and z respectively
nI symbol.
The x of m sequence and y sequence construct method are as follows:
Initial condition:
-x is by x (0)=1, x (1)=x (2)=...=x (16)=x (17)=0 constitutes.
-y(0)＝y(1)＝...＝y(16)＝y(17)＝1。
The recursive definition of successive character:
-x(i+18)＝(x(i+7)+x(i))，i＝0，...，2
18-20。(1.0)
-y(i+18)＝(y(i+10)+y(i+7)+y(i+5)+y(i))，i＝0，...，2
18-20。(1.1)
N Gold sign indicating number sequence z
n, n=0,1,2 ..., 2
18-2, be defined as:
-z
n(i)＝x((i+n)mod(2
18-1))+y(i)，i＝0，...，2
18-2。(1.2)
Wherein i can be considered discrete-time variable, and n is a shift value, and different n represents different scrambler number,
By public affairs
Formula 1.2 as can be known this gold code character be the x sequence of cyclic shift n time add the y sequence and.
N multiple scrambler sequence S
Dl, nBe defined as:
-S
Dl, n(i)=Z
n(i)+jZ
n((i+131072) mould (2
18-1)), i=0,1 ..., 38399.(1.3)
For different scrambler sequence, the value of the y sequence of corresponding phase is always fixed, and just change has taken place the value of the x sequence of corresponding phase.And the logical operation acquisition of the value that relatively the x sequence of cyclic shift n time can be by acting on mask function in the shift register that generates the x sequence.Therefore, the x sequence by shroud module change out of phase realizes that a scrambler generator is in conjunction with a plurality of scramblers of the parallel generation of mask function.
Be the electrical block diagram of the single scrambler generation module of the present invention as shown in Figure 3.Module 310 comprises the register of depositing m sequence initial phase place value, by presetting different register initial phase place values, can produce the scrambler sequence of designated phase.The register 311 of 18 bits produces the y sequence by 1.1 feedback recurrent formula, the register 312 of 18 bits produces the x sequence by 1.0 feedback recurrent formula, total shroud module 320 comprises four masking values, each masking value is the parameter value of one 18 bit, the bit of masking value bit and register value is corresponding one by one., can realize function of shielding by step-by-step of corresponding bit position and operation, promptly extracting out in the mask function is the value of 1 the pairing register in position, wherein shroud module 321,322 act on register 311, register value obtains the y sequence by shroud module 321, add the real part sequence that produces the scrambler complex sequences with the x sequence of correspondence, register value is by the shroud module 322 imaginary part sequence that 131072 y sequence and corresponding x sequence addition produce the scrambler complex sequences that obtains being shifted.Shroud module 323,324 acts on register 312, register value obtains the x sequence by shroud module 323, be used to produce the real part sequence of scrambler complex sequences with the y sequence addition of correspondence, register value is by shroud module 324 obtain being shifted the x sequence of 131072 phase places and the imaginary part sequence that corresponding y sequence addition produces the scrambler complex sequences.Self mould two adds module 330 to be realized 18 Bit datas after each shroud module computing are done two add operations of 18 bits self mould, produce the binary sequence value, it comprises many bits XOR module 331,332,333,334, produce y sequence and x sequence respectively, do mould two as 331 pairs of y sequential registers of many bits XOR module value through each bit of the operation result of shroud module 321 shieldings and add, obtain the y sequence.332 pairs of y sequential registers of many bits XOR module value is done mould two through each bit of the operation result of shroud module 322 shieldings and is added, and obtains the y sequence of displacement 131072 phase places.Too much bit XOR module 342 xor operations of single-bit output result warp of the single-bit output result of many bits XOR module 331 and many bits XOR module 333 obtain the real part sequence of scrambler, and the single-bit output result of the single-bit output result of many bits XOR module 332 and many bits XOR module 334 operates the imaginary part sequence that obtains scrambler through too much bit XOR module 341 xor operations.This scrambler sequence register output long-time path to avoid hardware logic to cause.
Fig. 4 is the schematic diagram of 8 disturbing code parallel generation modules that code character comprises in the Cell searching of realizing according to the present invention, propose a kind of more optimize multiple disturbing code parallel generator, utilize a single scrambler generator to replace in conjunction with the multiple disturbing code parallel generator 410 of shroud module mode all scrambler initial phase modules 220 of code character and 8 groups of scrambler generators composition scrambler generation modules 230 on the basis of Fig. 2,410 specific design as shown in Figure 5.
Fig. 5 is the single scrambler generator realized according to the present invention circuit diagram in conjunction with the multiple disturbing code parallel generator of shroud module mode, comprises as lower module: X sequence computing module, Y sequence computing module, the eight pairs of X shroud modules, a pair of Y shroud module, parity calculations device A～R, modular two addition device AC～AQ, modular two addition device BC～BQ.
Described shroud module is for different scrambler sequence, and the value of the y sequence of corresponding phase is always fixed different scrambling codes, and just change has taken place the value of the x sequence of corresponding phase.And relatively the value of the register of the x sequence of cyclic shift n time can act on the logical operation acquisition of the value of the register that generates the x sequence by the logical value with correspondence.Inner link according to the register initial value phase place of each main scrambler in the scrambler code character, derive the register initial value phase place of the 0th main scrambler in the scrambler code character and the register initial value phase place of other main scramblers a fixing operational formula is arranged respectively, here be referred to as shroud module for the time being, 8 corresponding altogether 8 pairs of shroud modules of scrambler, each shroud module correspondence the logical value of each 18 fixing bit, this value is masking value, therefore, utilize this masking value that 18 bit register values of the output of X sequence computing module are done masking operation by shroud module, thereby the x sequential register value that obtains out of phase realize that a scrambler generator is in conjunction with a plurality of scramblers of the parallel generation of masking value.It comprises eight pairs of X shroud modules, a pair of Y shroud module: the X sequential register output valve in the corresponding scrambler group of X shroud module I0 and X shroud module Q0 in the 0th scrambler, through the shroud module operation, be equivalent to take out the X sequential register related bits position that participates in scrambler 0 computing without displacement.X sequential register output valve in the corresponding scrambler group of X shroud module I7 and X shroud module Q7 in the 7th scrambler through the shroud module operation, is equivalent to take out the X sequential register related bits position through 112 phase places that are shifted that participates in scrambler 7 computings.Middle abridged part is represented scrambler 1 to scrambler 6, all is with respect to the corresponding different masking values of the out of phase difference of scrambler 0, and principle is with the same with the shroud module operation of scrambler 7.Y sequential register output valve in the corresponding scrambler group of Y shroud module I0 and Y shroud module Q0 in 8 scramblers through the shroud module operation, is equivalent to take out the Y sequential register related bits position without displacement that participates in 8 scrambler computings.
The detailed operation flow process of this patent multiple disturbing code parallel generator is as follows:
At first determine the initial phase place value of register in the X sequence computing module in the multiple disturbing code parallel generator, this is worth the register initial value of out of phase of the 0th scrambler correspondence of corresponding main scrambler group, and the initial value of the register of out of phase in definite Y sequence computing module, carry out the self feed back computing according to primitive polynomial separately, export the value 512 of X sequence computing module register and the value 511 of Y sequence computing module register simultaneously.
The value 512 of X sequence computing module register is input to eight pairs of X shroud modules respectively: X shroud module I0 and X shroud module Q0 and X shroud module I7 and X shroud module Q7, through the operation of each shroud module, parallel calculate participate in respectively 8 scrambler computings through the X sequential register related bits position of corresponding phase separately that is shifted.The value 511 of register is input to a pair of Y shroud module respectively in the Y sequence computing module, Y sequential register output valve in the corresponding scrambler group of Y shroud module I0 and Y shroud module Q0 in 8 scramblers, through the shroud module operation, calculate the Y sequential register related bits position that participates in 8 scrambler computings without displacement.
The result of calculation of eight pairs of X shroud modules and a pair of Y shroud module is input to parity calculations device A to parity calculations device R in totally 18 parity calculations devices, the number that calculates 18 Bit datas 1 is odd number or even number, the corresponding Y sequence of parity calculations device A and B wherein, it participates in 8 scramblers in back and gets computing, A and the B real part and the imaginary part of corresponding back respectively calculate, 16 parity calculations device C are to the corresponding X sequence of R, wherein parity calculations device C and D calculate the masking operation data of scrambler 0, the real part of corresponding back and imaginary part are calculated respectively, the corresponding scrambler 7 of modular two addition device Q and R, the real part of corresponding back and imaginary part are calculated respectively, and wherein the abridged is that scrambler 1 is to scrambler 6.
Parity calculations device A arrives the parity calculations device R result of calculation of totally 18 parity calculations devices, wherein parity calculations device A output as modular two addition device AC to one of input of modular two addition device AQ, wherein parity calculations device B output as modular two addition device BD to one of input of modular two addition device BR, and modular two addition device C, D is to Q, R is respectively as modular two addition device AC, BD is to AQ, the another one input of BR, modular two addition device AC like this, BD is to AQ, BR does mould two to input and adds the sequence that generates 8 scramblers, modular two addition device AC generates the real part sequence SI0 of 8 scramblers respectively to SI7 to modular two addition device AQ, modular two addition device BC generates the imaginary part sequence SQ0 of 8 scramblers respectively to SQ7 to modular two addition device BQ, wherein SI0+jSQ0 is exactly the complex sequences of scrambler 0, SI7+jSQ7 is exactly the complex sequences of scrambler 7, and therefore walking abreast by this scrambler generator has generated 8 scramblers.
Export with register 8 scrambler sequence in long-time path for avoiding hardware logic to cause on Project Realization.
Be shroud module structural representation of the present invention as shown in Figure 6, sequence computing module register value is input to corresponding shroud module, with the masking value step-by-step with, pick out the related bits position that needs to participate in the scrambler subsequent calculations, again each bit of calculated data is done XOR, obtaining in the result 1 expression data 1 number is odd number, and 0 expression is an even number.
Although the present invention discerns the situation that 8 disturbing code parallels of certain code character produce with reference to the Cell searching scrambler to describe; but those skilled in the art is under the condition of the spirit and scope of the present invention that do not break away from the claims qualification; can carry out the various modifications of form and details to it; and all such modifications all should belong to the protection range of claims of the present invention.
Claims (4)
1, multiple disturbing code parallel generator in a kind of WCDMA Cell searching, it is characterized in that, comprise: X sequence computing module, Y sequence computing module, eight pairs of X shroud modules, a pair of Y shroud module, several parity calculations devices of correspondence and a plurality of modular two addition devices of correspondence as lower module;
Described X sequence computing module comprises the register of depositing X sequence initial phase place value, be used for by presetting the register initial phase place value of the 0th scrambler of scrambler code character, produce the X sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described Y sequence computing module comprises the register of depositing Y sequence initial phase place value, be used for by presetting the register initial phase place value of the 0th scrambler of scrambler code character, can produce the Y sequence of designated phase, register obtains the register value of sequence designated phase through the feedback recurrent formula simultaneously, and exports the register value of this phase place;
Described shroud module is used for the inner link according to the register initial value phase place of each main scrambler of scrambler code character, the fixing logical operation formula in the realization scrambler code character between the register initial value phase place of the register initial value phase place of the 0th main scrambler and other main scramblers;
Described parity calculations device is used for calculating 16 Bit data results' 1 of above-mentioned a plurality of shroud modules number, and judges that number is even number or odd number;
Described modular two addition device is used for calculating the real part and the imaginary part sequence of scrambler by the output of parity calculations device the I road of correspondence and Q road is done mould two and added as a result.
2, parallel generator according to claim 1, it is characterized in that, described shroud module comprises 18, respectively corresponding 8 scramblers, the corresponding fixing logical operation value of each shroud module, be masking value, utilize masking value that 18 bit register values of the output of described X, Y sequence computing module are done masking operation by shroud module, parallel computation goes out to participate in the scrambler group the 0th～7 scrambler X, the Y sequential register related bits position of totally 8 scrambler computings.
3, parallel generator according to claim 2, it is characterized in that, the structure of described shroud module is set to corresponding sequence computing module register value and is input to corresponding shroud module, with the masking value step-by-step with, pick out the related bits position that needs to participate in the scrambler subsequent calculations, again each bit of calculated data is done XOR, obtaining in the result 1 expression data 1 number is odd number, and 0 expression is an even number.
4, multiple disturbing code parallel production method in a kind of WCDMA Cell searching, it may further comprise the steps:
A, determine in the multiple disturbing code parallel generator in the corresponding scrambler group initial value of the register in the register initial value and Y sequence computing module in the X sequence computing module of the 0th scrambler, carry out the self feed back computing by primitive polynomial separately, export the value of register separately simultaneously;
The register value of B, described X, Y sequence computing module is input to eight pairs of X shroud modules, a pair of Y shroud module respectively, respectively parallel computation go out to participate in 8 scrambler computings through the X sequential register related bits position of the corresponding phase separately of being shifted and participate in the Y sequential register related bits position without displacement of 8 scrambler computings;
The result of calculation of C, described shroud module is input in 18 parity calculations devices totally, and calculating among each shroud module output result 1 number is odd number or even number;
The result of calculation of D, described parity calculations device is input to the modular two addition device to correspondence respectively carries out mould two and adds computing, generates the real part sequence and the imaginary part sequence of 8 scramblers respectively.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281116A (en) * | 2010-06-11 | 2011-12-14 | 重庆重邮信科通信技术有限公司 | Method and device for generating GOLD sequence |
| CN105187151A (en) * | 2015-09-30 | 2015-12-23 | 广州慧睿思通信息科技有限公司 | Method and system for generation of downlink scrambling code sequence in WCDMA system |
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2005
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102281116A (en) * | 2010-06-11 | 2011-12-14 | 重庆重邮信科通信技术有限公司 | Method and device for generating GOLD sequence |
| CN102281116B (en) * | 2010-06-11 | 2017-02-01 | 重庆重邮信科通信技术有限公司 | Method and device for generating GOLD sequence |
| CN105187151A (en) * | 2015-09-30 | 2015-12-23 | 广州慧睿思通信息科技有限公司 | Method and system for generation of downlink scrambling code sequence in WCDMA system |
| CN105187151B (en) * | 2015-09-30 | 2018-02-09 | 广州慧睿思通信息科技有限公司 | A kind of production method and system of WCDMA system downlink scrambling code sequence |
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| CN100530993C (en) | 2009-08-19 |
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Application publication date: 20070314 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Multiple disturbing code parallel generator in WCDMA cell search and its method Granted publication date: 20090819 License type: Common License Record date: 20190619 |