CN1925377B - Device and method for generation of WCDMA descending multiple scrambling codes - Google Patents
Device and method for generation of WCDMA descending multiple scrambling codes Download PDFInfo
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- CN1925377B CN1925377B CN2005100937439A CN200510093743A CN1925377B CN 1925377 B CN1925377 B CN 1925377B CN 2005100937439 A CN2005100937439 A CN 2005100937439A CN 200510093743 A CN200510093743 A CN 200510093743A CN 1925377 B CN1925377 B CN 1925377B
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Abstract
This invention discloses one WCDMA down interference generation device and method, wherein, the device comprises one x sequence generator, one y sequence generator and one x sequence mask array and 16 interference codes integrator, wherein, the said y sequence generator outputs two vectors and to input to the integrator; the said x sequence generator outputs x sequence bit values to the x mask array for processing these values to input to the 16 interference integrator; the said 16 interference integrator outputs 16 interference sequence values.
Description
Technical field
The present invention relates to the baseband processor technology of broadband CDMA system (WCDMA) base station, the implement device of a plurality of descending scramblers in particular same sub-district, with and the implementation method of application-specific integrated circuit (ASIC).
Background technology
The third generation moves partnership (3GPP) scrambler distribution principle, scrambler create-rule in sub-district of broadband CDMA system has all been done strict regulations.
3GPP has stipulated 8192 effective descending scramblers altogether, and wherein sign indicating number number is that 512 scramblers altogether of 16 integer multiple are defined as main scrambler, and uses n=16*i, and i=0...511 represents.If the scrambler sign indicating number number is n=16*i, then this scrambler is called as i main scrambler.With the scrambler of i main scrambler correspondence number be 16*i+k, and 15 scramblers altogether of k=1...15 are called as the individual auxiliary scrambler collection of i.
Scrambler distribution principle in sub-district of broadband CDMA system is: a main scrambler and corresponding auxiliary scrambler collection thereof are used and only used in a sub-district, if the main scrambler that uses is an i main scrambler, then the auxiliary scrambler collection of Shi Yonging is necessary for i auxiliary scrambler collection.Therefore, a sub-district can be used 16 scramblers at most, and these 16 scrambler sign indicating numbers number can be expressed as n=16*i+k, i=0, and 1 ... 511, k=0,1...15.
3GPP has stipulated the implementation method and the implementation structure of any descending scrambler simultaneously.
The descending scrambler of arbitrary WCDMA is two 18 synthetic sequence of complex numbers of rank m sequence set, and these two m sequences are hereinafter referred to as x sequence, y sequence.Wherein the primitive polynomial of x sequence is 1+X
7+ X
18, the primitive polynomial of y sequence is 1+X
5+ X
7+ X
10+ X
18When scrambler number is n, scrambler sequence S
Dl, nExpression.Sequence z
n, Z
nAn intermediate object program of expression x, y series processing is with x (i), y (i), z
n(i), Z
n(i), S
Dl, n(i) represent sequence x, y, z respectively
n, Z
nAnd S
Dl, nI symbol, scrambler sequence S then
Dl, nThe generation method is defined as:
At first, obtain two sequences of x, y.This need obtain by two steps.The first step obtains the initial condition value of x, two sequences of y, promptly is preceding 18 values of sequence.The initial condition of x sequence is x (0)=1, x (1)=x (2)=...=x (16)=x (17)=0, the initial condition of y sequence be y (0)=y (1)=...=y (16)=y (17)=1.Second step used the recurrence formula of x, y sequence to obtain the full sequence value of x, y sequence.The recurrence formula of x sequence is: x (i+18)=x (i+7)+x (i) modulo 2, and i=0 ..., 2
18-20, the recurrence formula of y sequence is: y (i+18)=y (i+10)+y (i+7)+y (i+5)+y (i) modulo 2, and i=0 ..., 2
18-20.
Use x, y sequence to generate z then
nSequence, the generating mode that regulation is used is: z
n(i)=x ((i+n) modulo (2
18-1))+and y (i) modulo 2, i=0 ..., 2
18-2.Promptly, select the out of phase of x sequence to carry out computing according to the difference of scrambler n.
Then with z
nThe sequence real numberization, the mode that regulation adopts is:
At last from sequence Z
nMiddle intercepting part value obtains scrambler sequence S
Dl, nReal part and imaginary part.The intercept method of regulation is:
S
dl，n(i)＝Z
n(i)+jZ
n((i+131072)modulo(2
18-1))，i＝0，1，...，38399
Be Z
nPreceding 38400 sequential values successively as 38400 values of scrambler sequence real part, Z
n38400 sequential values that begin from its 131072nd sequential value are successively as 38400 values of scrambler sequence imaginary part.S
Dl, nThe real part I road component that is otherwise known as, imaginary part is also referred to as Q road component.
Based on above-mentioned descending scrambler implementation method, 3GPP has also stipulated descending scrambler implementation structure, promptly descending scrambling generator structure.As shown in Figure 1, the first half among the figure is the x sequencer, and the latter half is the y sequencer, is placed in the solid line boxes expression with a small circle of two orthogonal straight liness among the figure xor operation is carried out in each input.
In the x sequencer wherein the initial value of 18 registers with the scrambler difference difference, therefore a descending scrambling generator can only generate a descending scrambler sequence.In the WCDMA system, a sub-district can be used 16 scramblers at most, and these 16 scrambler sign indicating numbers number can be expressed as n=16*i+k, i=0,1, ... 511, k=0,1...15, when in application-specific integrated circuit (ASIC), realizing these 16 scrambler sequence simultaneously, because scrambler number has nothing in common with each other, make the initial value of 18 registers in its x sequencer also different, therefore need 16 descending scrambling generators altogether.In these 16 scrambling generators, the initial condition of the structure of its y sequencer and 18 registers is all identical, can share; Because scrambler difference, the initial condition of x sequencer are also different, therefore need 16 x sequencers, the hardware resource expense is very big.
The purpose of this invention is to provide the apparatus and method that a kind of WCDMA descending multiple scrambling codes generates, in order to overcome in the existing WCDMA system base-station baseband processor, 16 x sequencers of 16 descending scrambling generators that need can not be multiplexing, consume the big shortcoming of hardware resource, a kind of new implementation structure is proposed, make these 16 scrambling generators share an x sequencer, thereby save the hardware resource of hardware resource expense, especially its application-specific integrated circuit (ASIC).
Technical scheme of the present invention comprises:
The device that a kind of WCDMA descending multiple scrambling codes generates, wherein, this device comprises an x sequence generator, a y sequence generator and an x sequence mask array and 16 scrambler synthesizers; Two components of described y sequence generator output are input in described 16 scrambler synthesizers simultaneously, and one of them component is used to calculate the I road component of each scrambler sequence, and another component is used to calculate the Q road component of each scrambler sequence; Each bit register values of described x sequence generator output x sequence generator is to described x sequence mask array, described x sequence mask array is handled these values, generates 16 scrambler sequence I road, Q road component separately and is input to described 16 scrambler synthesizers respectively; Described 16 scrambler synthesizers are exported 16 scrambler sequence values respectively; The I road component of described scrambler sequence is meant the real part of scrambler sequence, and the Q road component of described scrambler sequence is meant the imaginary part of scrambler sequence.
The method that a kind of WCDMA descending multiple scrambling codes generates, it comprises the steps:
X sequence generator, the y sequence generator of A, acquisition scrambling generator are posted separately
The initial value of storage;
B, when this scrambling generator is started working, carry out following steps:
B1 is loaded into the initial value of x, y sequence generator register separately in separately the register;
B2, described x sequence generator outputs to each bit register values of x sequence generator in the x sequence mask array, obtains the new register value of each bit register of x sequence generator simultaneously;
B3, described y sequence generator is handled each bit register values of y sequence generator, obtain two components in each scrambler synthesizer, one of them component is used to calculate the I road component of each scrambler sequence, another component is used to calculate the Q road component of each scrambler sequence, obtains the new register value of each bit register of y sequence generator simultaneously; The I road component of described scrambler sequence is meant the real part of scrambler sequence, and the Q road component of described scrambler sequence is meant the imaginary part of scrambler sequence;
B4, described x sequence mask array generate 16 scrambler sequence I road, Q road separately and calculate component, output in each self-corresponding scrambler synthesizer;
B5, described 16 scrambler synthesizers are worked simultaneously, export I, the Q road component value of corresponding scrambler sequence separately;
B6 judges whether to have generated the full sequence value of 16 scramblers of a frame, if then continue to carry out next frame; If not, then forward described step B2 to and continue to carry out.
Described method, wherein, described y sequence generator register initial value is 18 sequential values that 0 place begins for the y sequence phase, promptly y (0), y (1) ..., y (17), this initial value all is 1, produces in that application-specific integrated circuit (ASIC) is inner.
Described method, wherein, described x sequence generator register initial value is 18 sequential values of n place beginning for the x sequence phase, be x (n), x (n+1) ..., x (n+17), this initial value depends on given scrambler n value, and this initial value obtains in the inner generation of application-specific integrated circuit (ASIC) or from application-specific integrated circuit (ASIC) is outside, wherein, scrambler n is expressed as n=16*i+k, i=0,1 ... 511, k=0,1...15.
The apparatus and method that a kind of WCDMA descending multiple scrambling codes provided by the present invention generates, owing to adopt the scrambling generator of 16 descending scramblers in sub-district of WCDMA system, with 16 x sequencers that need originally, convert an x sequencer and an x sequence mask array to, and realize that the application-specific integrated circuit (ASIC) hardware resource that this x sequence mask array needs is far smaller than the resource of 15 x sequencers, thereby reached the purpose of saving the hardware resource expense; By adjusting this x sequence mask array structure and scrambler synthesizer quantity, can adjust the scrambler sequence quantity of this scrambling generator output flexibly simultaneously.
Description of drawings
Fig. 1 is the WCDMA system descending scrambling generator structural representation of existing 3GPP regulation;
Fig. 2 is a WCDMA system descending scrambling generator structural representation provided by the invention;
Fig. 3 is the x sequence generator structural representation of apparatus of the present invention and method;
Fig. 4 is the y sequence generator structural representation of apparatus of the present invention and method;
Fig. 5 is WCDMA system descending scrambling generator x sequence mask array structure schematic diagram that apparatus of the present invention and method provided;
Fig. 6 is a WCDMA system descending scrambling generator x sequence mask array structure principle schematic provided by the present invention.
Embodiment
Below in conjunction with accompanying drawing, will carry out comparatively detailed explanation to each preferred embodiment of the present invention.
The device that WCDMA descending multiple scrambling codes of the present invention generates, it is a device that generates 16 descending scramblers in sub-district of WCDMA system simultaneously, as shown in Figure 2, it comprises an x sequence generator, a y sequence generator, an x sequence mask array and 16 scrambler synthesizers.Two components of described y sequence generator output are input in described 16 scrambler synthesizers simultaneously.18 bit values of described x sequence generator output x sequence are to described x sequence mask array, and described x sequence mask array is handled these values, exports 32 components altogether, two one group, is input to respectively in 16 scrambler synthesizers.Described 16 scrambler synthesizers are exported 16 scrambler sequence values respectively.
The course of work of the descending scrambling generator of WCDMA of the present invention is:
At first, according to the regulation of 3GPP, the x sequence generator of acquisition scrambling generator, y sequence generator be the initial value of 18 bit registers separately.Y sequence generator 18 bit register initial values are 18 sequential values that 0 place begins for the y sequence phase, promptly y (0), y (1) ..., y (17).This initial value all is 1, can be in the inner generation of application-specific integrated circuit (ASIC).Described x sequence generator 18 bit register initial values are 18 sequential values of n place beginning for the x sequence phase, be x (n), x (n+1) ..., x (n+17), this initial value depends on given scrambler n value, this initial value both can also can obtain from application-specific integrated circuit (ASIC) is outside in the inner generation of application-specific integrated circuit (ASIC).
When this scrambling generator is started working then, carry out according to following steps:
The first step is loaded into x, y sequence generator register initial value separately in separately 18 bit registers.
In second step, the x sequence generator outputs to each bit register values in the x sequence mask array.Obtain the new register value of each bit register of x sequence generator simultaneously according to the mode of 3GPP regulation.
In the 3rd step, the y sequence generator is handled each bit register values, obtains two components in each scrambler synthesizer.One of them component is used to calculate the I road value of each scrambler sequence, and another component is used to calculate the Q road value of each scrambler sequence.Obtain the new register value of each bit register of y sequence generator in this step simultaneously according to the mode of 3GPP regulation.
In the 4th step, x sequence mask array generates 16 scrambler sequence I road, Q road separately and calculates component, outputs in each self-corresponding scrambler synthesizer.
In the 5th step, 16 scrambler synthesizers are worked simultaneously, export I, the Q road component value of corresponding scrambler sequence separately.
In the 6th step, judge whether to have generated the full sequence value of 16 scramblers of a frame.If then forward the first step to and continue to carry out; If not, then forward the continuation of second step to and carry out.
Be illustrated in figure 2 as WCDMA system descending scrambling generator structure provided by the invention, it comprises an x sequence generator, a y sequence generator, an x sequence mask array and 16 scrambler synthesizers, i.e. S
Dl, nSynthesizer, S
Dl, n+1Synthesizer ..., S
Dl, n+15Synthesizer.A sub-district can be used 16 scramblers at most, the scrambler of establishing these 16 scramblers number be respectively n, n+1 ..., n+15, then S
Dl, nThe synthesizer output code number is scrambler sequence, the S of n
Dl, n+1The synthesizer output code number be (n+1) scrambler sequence ..., S
Dl, n+15The synthesizer output code number is the scrambler sequence of (n+15).
Before this scrambling generator is started working, need at first according to the 3GPP regulation, the x sequence generator, y sequence generator that obtains this scrambling generator be the initial value of 18 bit registers separately.18 bit register initial values of y sequence generator are 18 sequential values that 0 place begins for the y sequence phase, promptly y (0), y (1) ..., y (17).These 18 sequential values all are 1, can be in the inner generation of application-specific integrated circuit (ASIC).18 bit register initial values of x sequence generator are 18 sequential values of n place beginning for the x sequence phase, be x (n), x (n+1) ..., x (n+17), this initial value depends on the n value in 16 given scramblers number, this initial value both can also can obtain from application-specific integrated circuit (ASIC) is outside in the inner generation of application-specific integrated circuit (ASIC).
The x sequence needs two steps to obtain.The first step obtains the initial condition value of x sequence, i.e. preceding 18 values of sequence, and x (0)=1, x (1)=x (2)=...=x (16)=x (17)=0.Second step used the recurrence formula of x sequence to obtain the full sequence value.The recurrence formula of x sequence is: x (i+18)=x (i+7)+x (i) modulo 2, and i=0 ..., 2
18-20.
When scrambling generator is started working then, carry out according to following steps:
The first step is loaded into acquired x, y sequence generator register initial value separately in separately 18 bit registers.
As Fig. 3 is the x sequence generator structure of scrambling generator of the present invention, Fig. 4 is the y sequence generator structure of scrambling generator of the present invention, be with each register of the box indicating sequence generator of numeral separately among the figure, numeral in the frame the high low level order of register, register 0 expression lowest order register, register 17 expression highest order registers.
When x sequence generator register initial value is loaded, carry out according to following rule: x (n) the lowest order register of packing into, promptly register 0, pack into time low bit register of x (n+1), promptly register 1 ..., the rest may be inferred, last x (n+17) the highest order register of packing into, and promptly register 17.
Behind y sequence generator register initial value loading, the value of each register of y sequence generator all is a value 1.
In second step, the x sequence generator outputs to each bit register values in the x sequence mask array, register 17, register 16 ..., to register 0 value and the line output of totally 18 registers.Obtain the new register value of each bit register of x sequence generator simultaneously according to the mode of 3GPP regulation, the acquisition mode is with reference to shown in Figure 3, for: the value of register 17 moves into register 16, value in the former register 16 moves into register 15, ..., value in the former register 1 moves into register 0, and the value of former register 0 and the value of former register 17 are carried out XOR simultaneously, and the XOR result is as the new value of register 17.
In the 3rd step, described y sequence generator is handled each bit register values, obtains two component 102I, 102Q, parallel outputing in 16 scrambler synthesizers.With reference to shown in Figure 4,102I, 102Q acquisition mode are: the 102I value is the value of the register 0 of y sequence generator, and the value of 102Q is the end value that 10 values such as the value of the register 5 of y sequence generator, the value of register 6, the value of register 8, the value of register 9, the value of register 10, the value of register 11, the value of register 12, the value of register 13, the value of register 14 and the value of register 15 are carried out xor operation.
This step obtains the new register value of each bit register of y sequence generator simultaneously according to the mode of 3GPP regulation, the acquisition mode is with reference to figure 4, for: the value of register 17 moves into register 16, value in the former register 16 moves into register 15, ..., value in the former register 1 moves into register 0, and value, the value of former register 5, the value of former register 7 and 4 values such as value of former register 10 of former register 0 are carried out XOR simultaneously, and the XOR result is as the new value of register 17.
In the 4th step, described x sequence mask array is handled each bit register values of x sequence generator of input, generates 16 scrambler sequence I road, Q road separately and calculates component, outputs in the scrambler synthesizer separately.Output to S
Dl, nTwo calculating components of synthesizer are 1000I, 1000Q, and 1000I is S
Dl, nComponent is calculated on the I road of synthesizer, and 1000Q is S
Dl, nComponent is calculated on the Q road of synthesizer; Output to S
Dl, n+1Two calculating components of synthesizer are 1001I, 1001Q, and 1001I is S
Dl, n+1Component is calculated on the I road of synthesizer, and 1001Q is S
Dl, n+1Component is calculated on the Q road of synthesizer; ...; Output to S
Dl, n+15Two calculating components of synthesizer are 10015I, 10015Q, and 10015I is S
Dl, n+15Component is calculated on the I road of synthesizer, and 10015Q is S
Dl, n+15Component is calculated on the Q road of synthesizer.
Be illustrated in figure 5 as the x sequence mask array structure of scrambling generator of the present invention, the straight-through output of low 16 bits of each bit register values of x sequence generator of input is as the I road component of each scrambler synthesizer, and the bit value with correspondence carries out the Q road calculating component of XOR as each scrambler synthesizer simultaneously.
As Fig. 6 is its principle schematic, and it provides 16 scrambler sequence I separately, the mode that component is calculated on the Q road of obtaining.
1000I, 1001I ..., 10015I be respectively register 0 from x sequence generator input, register 1 ..., the value of register 15;
1000Q is the result of the value xor operation of register 4, register 6 and the register 15 of the input of x sequence generator;
1001Q is the result of the value xor operation of register 5, register 7 and the register 16 of the input of x sequence generator;
1002Q is the result of the value xor operation of register 6, register 8 and the register 17 of the input of x sequence generator;
1003Q is the result of the value xor operation of the register 0 of x sequence generator input and register 9;
1004Q is the result of the value xor operation of the register 1 of x sequence generator input and register 10;
1005Q is the result of the value xor operation of the register 2 of x sequence generator input and register 11;
1006Q is the result of the value xor operation of the register 3 of x sequence generator input and register 12;
1007Q is the result of the value xor operation of the register 4 of x sequence generator input and register 13;
1008Q is the result of the value xor operation of the register 5 of x sequence generator input and register 14;
1009Q is the result of the value xor operation of the register 6 of x sequence generator input and register 15;
10010Q is the result of the value xor operation of the register 7 of x sequence generator input and register 16;
10011Q is the result of the value xor operation of the register 8 of x sequence generator input and register 17;
10012Q is the result of the value xor operation of register 0, register 7 and the register 9 of the input of x sequence generator;
10013Q is the result of the value xor operation of register 1, register 8 and the register 10 of the input of x sequence generator;
10014Q is the result of the value xor operation of register 2, register 9 and the register 11 of the input of x sequence generator;
10015Q is the result of the value xor operation of register 3, register 10 and the register 12 of the input of x sequence generator.
The 5th step, described 16 scrambler synthesizers are worked simultaneously, the structure of each scrambler synthesizer is identical, it carries out xor operation to the 102I that calculates component and the output of y sequence generator from the scrambler sequence I road of x sequence mask array output, with the I road component output of XOR result as corresponding scrambler sequence; The 102Q that the scrambler sequence Q road of x sequence mask array output is calculated component and the output of y sequence generator carries out xor operation simultaneously, with the Q road component output of XOR result as corresponding scrambler sequence.
Wherein:
S
Dl, nSynthesizer carries out XOR with 1000I with 102I, obtains S
Dl, n(i) I road component carries out XOR with 1000Q with 102Q simultaneously, obtains S
Dl, n(i) Q road component;
S
Dl, n+1Synthesizer carries out XOR with 1001I with 102I, obtains S
Dl, n+1(i) I road component carries out XOR with 1001Q with 102Q simultaneously, obtains S
Dl, n+1(i) Q road component;
... and so on
S
Dl, n+15Synthesizer carries out XOR with 10015I with 102I, obtains S
Dl, n+15(i) I road component carries out XOR with 10015Q with 102Q simultaneously, obtains S
Dl, n+15(i) Q road component.
In the 6th step, judge whether to have generated the full sequence value of 16 scramblers of a frame.If then forward the first step to and continue to carry out; If not, then forward the continuation of second step to and carry out.
The scrambling generator of 16 descending scramblers in sub-district of WCDMA system provided by the present invention, 16 x sequencers with needing originally convert an x sequencer and an x sequence mask array to.16 x sequencers, need 288 registers, and realize the x sequence mask array of scrambling generator provided by the invention, with reference to figure 5, the hardware resource that needs only is 7 three input XOR gate and 9 two input XOR gate, be far smaller than the resource of 15 x sequencers, therefore saved the hardware resource expense greatly.
By adjusting this x sequence mask array structure and scrambler synthesizer quantity, just can adjust the scrambler sequence quantity of this scrambling generator output flexibly simultaneously.
But should be understood that above-mentioned description at specific embodiment is comparatively concrete, can not therefore think the restriction to scope of patent protection of the present invention, scope of patent protection of the present invention should be as the criterion with claims.
Claims (4)
1. the device that the WCDMA descending multiple scrambling codes generates is characterized in that this device comprises an x sequence generator, a y sequence generator and an x sequence mask array and 16 scrambler synthesizers; Two components of described y sequence generator output are input in described 16 scrambler synthesizers simultaneously, and one of them component is used to calculate the I road component of each scrambler sequence, and another component is used to calculate the Q road component of each scrambler sequence; Each bit register values of described x sequence generator output x sequence generator is to described x sequence mask array, described x sequence mask array is handled these values, generates 16 scrambler sequence I road, Q road component separately and is input to described 16 scrambler synthesizers respectively; Described 16 scrambler synthesizers are exported 16 scrambler sequence values respectively; The I road component of described scrambler sequence is meant the real part of scrambler sequence, and the Q road component of described scrambler sequence is meant the imaginary part of scrambler sequence.
2. the method that generates of a WCDMA descending multiple scrambling codes, it comprises the steps:
A, the x sequence generator that obtains scrambling generator, y sequence generator be the initial value of register separately;
B, when this scrambling generator is started working, carry out following steps:
B1 is loaded into the initial value of x, y sequence generator register separately in separately the register;
B2, described x sequence generator outputs to each bit register values of x sequence generator in the x sequence mask array, obtains the new register value of each bit register of x sequence generator simultaneously;
B3, described y sequence generator is handled each bit register values of y sequence generator, obtain two components in each scrambler synthesizer, one of them component is used to calculate the I road component of each scrambler sequence, another component is used to calculate the Q road component of each scrambler sequence, obtains the new register value of each bit register of y sequence generator simultaneously; The I road component of described scrambler sequence is meant the real part of scrambler sequence, and the Q road component of described scrambler sequence is meant the imaginary part of scrambler sequence;
B4, described x sequence mask array generate 16 scrambler sequence I road, Q road separately and calculate component, output in each self-corresponding scrambler synthesizer;
B5, described 16 scrambler synthesizers are worked simultaneously, export I, the Q road component value of corresponding scrambler sequence separately;
B6 judges whether to have generated the full sequence value of 16 scramblers of a frame, if then continue to carry out next frame; If not, then forward described step B2 to and continue to carry out.
3. method according to claim 2, it is characterized in that described y sequence generator register initial value is 18 sequential values that 0 place begins for the y sequence phase, promptly y (0), y (1) ..., y (17), this initial value all is 1, in the inner generation of application-specific integrated circuit (ASIC).
4. method according to claim 2 is characterized in that, described x sequence generator register initial value is 18 sequential values of n place beginning for the x sequence phase, be x (n), x (n+1) ..., x (n+17), this initial value depends on given scrambler n value, and this initial value obtains in the inner generation of application-specific integrated circuit (ASIC) or from application-specific integrated circuit (ASIC) is outside, wherein, scrambler n is expressed as n=16*i+k, i=0,1 ... 511, k=0,1...15.
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| EP1168654A2 (en) * | 2000-06-28 | 2002-01-02 | Samsung Electronics Co. Ltd. | Pilot channel power measurement means for a mobile station in asynchronous CDMA communication system |
| CN1433173A (en) * | 2002-01-11 | 2003-07-30 | 华为技术有限公司 | Method of realizing subzone access in synchronous wideband CDMA system |
| CN1433171A (en) * | 2002-01-18 | 2003-07-30 | 华为技术有限公司 | Method of obtaining present access subzone main scramble in synchronous windeband CDMA system |
| CN1464658A (en) * | 2002-06-17 | 2003-12-31 | 上海贝尔有限公司 | Prefix detector for WCDMA |
| AU2003294021A1 (en) * | 2003-12-30 | 2005-07-21 | Telefonaktiebolaget Lm Ericsson (Publ) | Method and system for allocation of channelisation codes in a code division multiple access system |
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| CN1925377A (en) | 2007-03-07 |
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