CN201541257U - Serial descrambling and despreading device for mobile communication system - Google Patents

Abstract

The utility model relates to a serial descrambling and despreading device for a mobile communication system. The serial descrambling and despreading device comprises a local code control information generator. The serial descrambling and despreading device is characterized in that the output end of the local code control information generator is connected with the input end of a descrambling and dispreading unit, and the output end of the descrambling and dispreading unit is connected with the input end of a symbol selector; a time schedule controller set to zero is connected at the controlled end of the descrambling and dispreading unit. Accordingly, by using a full adder, the descrambling and despreading to the two components I and Q of a digital signal can be completed. The time schedule control is simple, the logical resource is saved, therefore, the serial descrambling and despreading device is suitable for the realization of a special integrated circuit. Simultaneously, the operation of being multiplied by -1 is not required, thereby reducing the power consumption and saving the processing resource.

Description

Mobile communication system serial descrambling and de-spreading device

Technical field

The utility model relates to a kind of serial descrambling and de-spreading device, relates in particular to a kind of mobile communication system serial descrambling and de-spreading device.

Background technology

Along with the development of mobile communication technology, when the performance of wireless communication system day by day improved, the complexity of system was also constantly improving.And, realizing the high performance while for the user terminal chip of mobile communication system, also require rational cost and power consumption.

In the wireless communication system of code division multiple access, it is common sample mode that receiver (RAKE) receives.In wireless communication system TD SDMA TD-SCDMA, owing to adopted the mode of joint-detection, the numbers of branches of receiver increases greatly.And in the user terminal baseband chip, it is considerable that the receiver of joint-detection receives the resource that consumes.This shows, if can reduce the complexity of each branch in the receiver, can be very beneficial to the cost and the power consumption of chip.

Specifically, there is multiple implementation method in each branch in the receiver at present.Such as, carry out despreading by fast Walsh-Hadamard transform (FWHF) structure, identical but the scrambler of different branches needs, this is not suitable for the TD-SCDMA user terminal that multi-plot joint detects.Same, if directly take advantage of addition afterwards again, then need to multiply by-1 operation by chip data and scrambler spreading code, promptly data are carried out negate and add 1, and I component and Q component add up respectively, relatively take logical resource.Therefore need to adopt a kind of device of saving logical resource, reduction system power dissipation and cost to be used for serial descrambling and de-spreading of mobile communication system.

Summary of the invention

The purpose of this utility model is to overcome the above problem that prior art exists, and a kind of mobile communication system serial descrambling and de-spreading device is provided.

For realizing the purpose of this utility model mobile communication system serial descrambling and de-spreading device, include local code control information generator, it is characterized in that: the output of described local code control information generator connects the input of descrambling and de-spreading unit, the output bound symbol selector input of descrambling and de-spreading unit; Be connected with the zero setting time schedule controller on the controlled terminal of described descrambling and de-spreading unit.

Mobile communication system serial descrambling and de-spreading device further, above-mentioned, wherein, described descrambling and de-spreading unit, comprise the symbol gate, the XOR device, full adder and at least 3 d type flip flops, the output bound symbol gate of local code control information generator, the input of XOR device and full adder, the output of symbol gate is connected into the input of XOR device, the output of XOR device connects the input of full adder, the input of full adder is connected with second d type flip flop, the output of full adder connects the input of first d type flip flop, the output of first d type flip flop connects the input of second d type flip flop and 3d flip-flop, and the output of the output of 3d flip-flop and first d type flip flop is as the output of descrambling and de-spreading unit.

Adopt technical solutions of the utility model, only need a full adder, can finish the descrambling and de-spreading of a way word signal I, two components of Q.Its sequencing control is simple, saves logical resource, is applicable to the realization of application-specific integrated circuit (ASIC).Simultaneously, need not to multiply by-1 operation, can reduce the system Power Cutback and handle resource, on serial descrambling and de-spreading of mobile communication system, good application future is arranged.

The purpose of this utility model, advantage and characteristics will illustrate by the non-limitative illustration of following preferential embodiment and explain that these embodiment only provide as an example with reference to accompanying drawing.

Description of drawings

Fig. 1 is that this mobile communication system is handled organigram with the serial descrambling and de-spreading device.

The implication of each Reference numeral is as follows among the figure:

1 local code control information generator, 2 descrambling and de-spreading unit

3 zero setting time schedule controllers, 4 symbol selectors

5 symbol gates, 6 XOR devices

7 full adders, 8 first d type flip flops

9 second d type flip flops, 10 3d flip-flops

Embodiment

The device that is used for serial descrambling and de-spreading of mobile communication system as shown in Figure 1, its special feature is: include local code control information generator 1, it produces the control information of 2 times of spreading rates according to the scrambler spreading code; Descrambling and de-spreading unit 2, it carries out descrambling and de-spreading according to the sign indicating number control information to data; Zero setting time schedule controller 3, the zero clearing of serial accumulator in its control descrambling and de-spreading unit 2; Symbol selector 4, it carries out symbol sampler to the descrambling and de-spreading result, exports the descrambling and de-spreading result of this branch.Local code control information generator 1, zero setting time schedule controller 3, symbol selector 4 are connected into descrambling and de-spreading unit 2 respectively.And described 2 times of chips comprise the I component of input chip data and the selection control information of Q component, the input signal of XOR unit, the carry input signal of full adder 7.

Further combined with Fig. 1, described descrambling and de-spreading unit 2, comprise symbol selector 4, XOR device 6, full adder 7 and d type flip flop, symbol gate 5 input chip data, the output of symbol gate 5 is connected to the input of XOR device 6, the output of XOR device 6 is connected to the input of full adder 7, another input of full adder 7 is connected into second d type flip flop 9, the output of full adder 7 is connected to first d type flip flop 8, the output of first d type flip flop 8 is connected to the input of second d type flip flop 9 and 3d flip-flop 10, and the output of 3d flip-flop 10 is finished the output of this descrambling interface unit with the output of first d type flip flop 8.

Again specifically, first d type flip flop 8 is with the accumulation result preservation of sampling.Second d type flip flop 9, when the control information of zero setting time schedule controller 3 outputs was effective, output zero setting was used for the beginning that a symbol adds up; All the other the time, feed back to full adder 7 with after the accumulation result time-delay, be used for alternately adding up of I component and Q component.And described zero setting time schedule controller 3, the zero setting control information that produces second d type flip flop 9 is used to begin the descrambling and de-spreading of a symbol.3d flip-flop 10 postpones a clock cycle to accumulation result, I component is as a result of exported, with keep with after the Q component output that adds up of clock cycle synchronous.

Real work in conjunction with each parts: symbol selector 4 is by the I component of local code control information generator 1 generation and the selection control information of Q component, select I component or Q component in the input chip data, produce the data of 2 times of spreading rates, and the output signal of descrambling and de-spreading unit 2 is carried out exporting with character rate behind the symbol sampler.After the input signal that XOR device 6 produces local code control information generator 1 carries out the bit expansion, carry out the bit XOR with the input data.Full adder 7 at first carries out the sign bit expansion with the result of bit XOR, with the accumulation result of feedback and the carry-out bit of local code control information generator generation, adds entirely subsequently.

Simultaneously, zero time schedule controller 3 cooperate downstream spread spectrum codes 16 with 1 totally two kinds of situations present different operating states: when spreading code is 16, the the 1st and 2 clock cycle in corresponding to 32 clock cycle of a symbol period, the signal of zero setting time schedule controller 3 output is effective, the invalidating signal of exporting corresponding to back 30 clock cycle the time; When spreading code was 1, the signal of all clock cycle output was all effective.

Application feature below in conjunction with in the user terminal in the TDS-CDMA system (UE) baseband chip illustrates technical solutions of the utility model.

Specifically, to the chip data that receive, at certain route of transmission of certain code channel, the descrambling and de-spreading of continuous SF chip can be expressed as general formula:

${\tilde{s}}_n=\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}{r}_{(n-1)\·\mathrm{SF}+i}\·c_i^{*}=\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}{r}_{(n-1)\·\mathrm{SF}+i}\·{(\mathrm{spcod}{e}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^i)}^{*}$ (1)

$=\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}{r}_{(n-1)\·\mathrm{SF}+i}\·{\mathrm{spcode}}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^{-i}$

Further, in general formula (1),

Be n the symbol that obtains through descrambling and de-spreading; SF is a spreading code length, and descending SF is 16 or 1 in the TD-SCDMA system; r _{(n-1) SF+i}Be the chip data that receive; c _i ^*Conjugation for scrambler and spreading code dot product result; Spcode _iBe spreading code; Sccode _i(j) ^-iConjugation for multiple scrambler.

Convenience for the integrated circuit hardware logic is realized can be written as I component and Q component respectively with general formula (1):

$\mathrm{real}\left({\tilde{s}}_n\right)=\mathrm{real}(\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}{r}_{(n-1)\·\mathrm{SF}+i}\·{\mathrm{spcode}}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^{-\mathrm{mod}(i,2)}\·{\left(j\right)}^{-i+\mathrm{mod}(i,2)})$ (2)

$=\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}\mathrm{real}(r_{(n-1)\·\mathrm{SF}+i}\·{\left(j\right)}^{-\mathrm{mod}(i,2)})\·{\mathrm{spcode}}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^{-i+\mathrm{mod}(i,2)}$

$\mathrm{imag}\left({\tilde{s}}_n\right)=\mathrm{imag}(\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}{r}_{(n-1)\·\mathrm{SF}+i}\·{\mathrm{spcode}}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^{\mathrm{mod}(i,2)}\·{\left(j\right)}^{-i-\mathrm{mod}(i,2)})$ (3)

$=\underset{i=1}{\overset{\mathrm{SF}}{\mathrm{\Σ}}}\mathrm{imag}(r_{(n-1)\·\mathrm{SF}+i}\·{\left(j\right)}^{\mathrm{mod}(i,2)})\·{\mathrm{spcode}}_i\·{\mathrm{sccode}}_i\·{\left(j\right)}^{-i-\mathrm{mod}(i,2)}$

For result's real part, (r _{(n-1) SF+i}(j) ^{-mod (i, 2)}) reality is exactly to choose r _{(n-1) SF+i}Real part or imaginary part, and (j) ^{-i+mod (i, 2)}Be always real number, spcode _iSccode _i(j) ^{-i+mod (i, 2)}I.e. this time of control add up add operation or reducing.Certainly, like this equally for imaginary part.

When certain chip data being carried out descrambling and de-spreading calculating, the chip data enter the device that is used for serial descrambling and de-spreading of mobile communication system in order successively.Again further, the processing time of each chip data is 2 clock cycle, i.e. first clock cycle, be used for descrambling and de-spreading adding up of I component as a result, and second clock cycle is used for descrambling and de-spreading adding up of Q component as a result.

Simultaneously, local code control information generator 1 is by (j) ^{-mod (i, 2)}Or (j) ^{Mod (i, 2)}Produce the real part of choosing the input data, the control information of imaginary part.The I component or the Q component of input chip selected by this control information in descrambling and de-spreading unit 2, carries out accumulation calculating.Specifically, local code control information generator 1 is taken advantage of spcode as a result by code-point _iSccode _i(j) ^{-i ± mod (i, 2)}Produce the input signal of XOR unit and the carry signal of full adder 7.For the real part result, (j) ^{-i+mod (i, 2)}=1 ,-1 ,-1,1 ... }; For the imaginary part result, (j) ^{-i-mod (i, 2)}=1 ,-1,1,1 ... }.In hardware, { 1 ,-1} is so that { 0,1} represents that the dot product of scrambler and spreading code can be by { 0, the XOR of 1} obtains.

Subsequently, when the carry input of the input signal of XOR unit and full adder 7 equaled 0, the data of 7 pairs of selections of full adder carry out I component or Q component adds up.When the carry input of the input signal of XOR unit and full adder 7 equals 1,1 XOR expanded of the data of Xuan Zeing and position and add 1 and add up again then.It is actual to be exactly that the data negate of selecting is added 1, has promptly carried out reducing, thereby finishes the descrambling and de-spreading operation of general formula (2), general formula (3).

Then, second d type flip flop 9 of descrambling and de-spreading unit 2, the result who adds up postponed a clock cycle after again feedback add up, making adds up carries out at interval at I component result and Q component result.And, when spreading code was 16, the 1st and 2 clock cycle in corresponding to 32 clock cycle of a symbol period, the signal of zero setting time schedule controller 3 outputs was effective, make second d type flip flop 9 of descrambling and de-spreading unit 2 be output as 0, the descrambling and de-spreading of a symbol of beginning.Simultaneously, during the invalidating signal exported when back 30 clock cycle, second d type flip flop 9 of descrambling and de-spreading unit 2 postpones accumulation result to feed back after a clock cycle, adds up normally.And when spreading code was 1, the signal of all clock cycle output was all effective, then imported data through directly output as a result of behind the full adder 7.

Meanwhile, the 3d flip-flop 10 of descrambling and de-spreading unit 2, the I component that descrambling and de-spreading is finished postpones a clock cycle, with after together output to symbol selector 4 after the Q component combination finished.

Then, symbol selector 4 carries out the output signal of descrambling and de-spreading unit 2 symbol sampler and obtains the descrambling and de-spreading result, and exports with character rate after suitably postponing, to mate the output timing of other branches, conveniently the high specific of each follow-up branch outcome merges.

At last, a descrambling and de-spreading ramifying that receives by receiver (RAKE) gets final product.

By above-mentioned description as can be seen, only need a full adder behind employing the utility model, can finish the descrambling and de-spreading of a way word signal I, two components of Q.Its sequencing control is simple, saves logical resource, is applicable to the realization of application-specific integrated circuit (ASIC).Simultaneously, need not to multiply by-1 operation, can reduce the system Power Cutback and handle resource, on serial descrambling and de-spreading of mobile communication system, good application future is arranged.

Certainly, more than only be concrete exemplary applications of the present utility model, protection range of the present utility model is not constituted any limitation.In addition to the implementation, the utility model can also have other execution mode.All employings are equal to the technical scheme of replacement or equivalent transformation formation, all drop within the utility model scope required for protection.

Claims (2)

1. mobile communication system serial descrambling and de-spreading device, include local code control information generator, it is characterized in that: the output of described local code control information generator connects the input of descrambling and de-spreading unit, the output bound symbol selector input of descrambling and de-spreading unit; Be connected with the zero setting time schedule controller on the controlled terminal of described descrambling and de-spreading unit.

2. mobile communication system serial descrambling and de-spreading device according to claim 1, it is characterized in that: described descrambling and de-spreading unit, comprise the symbol gate, the XOR device, full adder and at least 3 d type flip flops, the output bound symbol gate of local code control information generator, the input of XOR device and full adder, the output of symbol gate is connected into the input of XOR device, the output of XOR device connects the input of full adder, the input of full adder is connected with second d type flip flop, the output of full adder connects the input of first d type flip flop, the output of first d type flip flop connects the input of second d type flip flop and 3d flip-flop, and the output of the output of 3d flip-flop and first d type flip flop is as the output of descrambling and de-spreading unit.

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